1 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
31 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
32 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
35 // Hi and Lo nodes are used to handle global addresses. Used on
36 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
37 // static model. (nothing to do with Mips Registers Hi and Lo)
38 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
39 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
40 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
43 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
46 // These are target-independent nodes, but have target-specific formats.
47 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
48 [SDNPHasChain, SDNPOutFlag]>;
49 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
50 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
52 // Select Condition Code
53 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
56 def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
58 //===----------------------------------------------------------------------===//
59 // Mips Instruction Predicate Definitions.
60 //===----------------------------------------------------------------------===//
61 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
62 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
63 def HasSwap : Predicate<"Subtarget.hasSwap()">;
64 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
66 //===----------------------------------------------------------------------===//
67 // Mips Operand, Complex Patterns and Transformations Definitions.
68 //===----------------------------------------------------------------------===//
70 // Instruction operand types
71 def brtarget : Operand<OtherVT>;
72 def calltarget : Operand<i32>;
73 def simm16 : Operand<i32>;
74 def shamt : Operand<i32>;
77 def uimm16 : Operand<i32> {
78 let PrintMethod = "printUnsignedImm";
82 def mem : Operand<i32> {
83 let PrintMethod = "printMemOperand";
84 let MIOperandInfo = (ops simm16, CPURegs);
87 // Transformation Function - get the lower 16 bits.
88 def LO16 : SDNodeXForm<imm, [{
89 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
92 // Transformation Function - get the higher 16 bits.
93 def HI16 : SDNodeXForm<imm, [{
94 return getI32Imm((unsigned)N->getZExtValue() >> 16);
97 // Node immediate fits as 16-bit sign extended on target immediate.
99 def immSExt16 : PatLeaf<(imm), [{
100 if (N->getValueType(0) == MVT::i32)
101 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
103 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
106 // Node immediate fits as 16-bit zero extended on target immediate.
107 // The LO16 param means that only the lower 16 bits of the node
108 // immediate are caught.
110 def immZExt16 : PatLeaf<(imm), [{
111 if (N->getValueType(0) == MVT::i32)
112 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
114 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
117 // shamt field must fit in 5 bits.
118 def immZExt5 : PatLeaf<(imm), [{
119 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
122 // Mips Address Mode! SDNode frameindex could possibily be a match
123 // since load and store instructions from stack used it.
124 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
126 //===----------------------------------------------------------------------===//
127 // Instructions specific format
128 //===----------------------------------------------------------------------===//
130 // Arithmetic 3 register operands
131 let isCommutable = 1 in
132 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
133 InstrItinClass itin>:
137 (ins CPURegs:$b, CPURegs:$c),
138 !strconcat(instr_asm, "\t$dst, $b, $c"),
139 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
141 let isCommutable = 1 in
142 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
146 (ins CPURegs:$b, CPURegs:$c),
147 !strconcat(instr_asm, "\t$dst, $b, $c"),
150 // Arithmetic 2 register operands
151 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
152 Operand Od, PatLeaf imm_type> :
155 (ins CPURegs:$b, Od:$c),
156 !strconcat(instr_asm, "\t$dst, $b, $c"),
157 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
159 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
160 Operand Od, PatLeaf imm_type> :
163 (ins CPURegs:$b, Od:$c),
164 !strconcat(instr_asm, "\t$dst, $b, $c"),
167 // Arithmetic Multiply ADD/SUB
169 class MArithR<bits<6> func, string instr_asm> :
174 !strconcat(instr_asm, "\t$rs, $rt"),
178 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
182 (ins CPURegs:$b, CPURegs:$c),
183 !strconcat(instr_asm, "\t$dst, $b, $c"),
184 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
186 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
189 (ins CPURegs:$b, uimm16:$c),
190 !strconcat(instr_asm, "\t$dst, $b, $c"),
191 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
193 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
197 (ins CPURegs:$b, CPURegs:$c),
198 !strconcat(instr_asm, "\t$dst, $b, $c"),
199 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
203 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
207 (ins CPURegs:$b, shamt:$c),
208 !strconcat(instr_asm, "\t$dst, $b, $c"),
209 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
211 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
215 (ins CPURegs:$b, CPURegs:$c),
216 !strconcat(instr_asm, "\t$dst, $b, $c"),
217 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
219 // Load Upper Imediate
220 class LoadUpper<bits<6> op, string instr_asm>:
224 !strconcat(instr_asm, "\t$dst, $imm"),
228 let canFoldAsLoad = 1, hasDelaySlot = 1 in
229 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
233 !strconcat(instr_asm, "\t$dst, $addr"),
234 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
236 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
239 (ins CPURegs:$dst, mem:$addr),
240 !strconcat(instr_asm, "\t$dst, $addr"),
241 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
243 // Conditional Branch
244 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
245 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
248 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
249 !strconcat(instr_asm, "\t$a, $b, $offset"),
250 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
254 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
257 (ins CPURegs:$src, brtarget:$offset),
258 !strconcat(instr_asm, "\t$src, $offset"),
259 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
264 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
269 (ins CPURegs:$b, CPURegs:$c),
270 !strconcat(instr_asm, "\t$dst, $b, $c"),
271 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
274 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
275 Operand Od, PatLeaf imm_type>:
278 (ins CPURegs:$b, Od:$c),
279 !strconcat(instr_asm, "\t$dst, $b, $c"),
280 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
283 // Unconditional branch
284 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
285 class JumpFJ<bits<6> op, string instr_asm>:
288 (ins brtarget:$target),
289 !strconcat(instr_asm, "\t$target"),
290 [(br bb:$target)], IIBranch>;
292 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
293 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
297 (ins CPURegs:$target),
298 !strconcat(instr_asm, "\t$target"),
299 [(brind CPURegs:$target)], IIBranch>;
301 // Jump and Link (Call)
302 let isCall=1, hasDelaySlot=1,
303 // All calls clobber the non-callee saved registers...
304 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
305 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
306 class JumpLink<bits<6> op, string instr_asm>:
309 (ins calltarget:$target, variable_ops),
310 !strconcat(instr_asm, "\t$target"),
311 [(MipsJmpLink imm:$target)], IIBranch>;
314 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
318 (ins CPURegs:$rs, variable_ops),
319 !strconcat(instr_asm, "\t$rs"),
320 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
322 class BranchLink<string instr_asm>:
325 (ins CPURegs:$rs, brtarget:$target, variable_ops),
326 !strconcat(instr_asm, "\t$rs, $target"),
331 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
335 (ins CPURegs:$a, CPURegs:$b),
336 !strconcat(instr_asm, "\t$a, $b"),
340 class MoveFromLOHI<bits<6> func, string instr_asm>:
345 !strconcat(instr_asm, "\t$dst"),
348 class MoveToLOHI<bits<6> func, string instr_asm>:
353 !strconcat(instr_asm, "\t$src"),
356 class EffectiveAddress<string instr_asm> :
361 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
363 // Count Leading Ones/Zeros in Word
364 class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
365 FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
366 !strconcat(instr_asm, "\t$dst, $src"),
367 [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
369 // Sign Extend in Register.
370 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
371 FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
372 !strconcat(instr_asm, "\t$dst, $src"),
373 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
376 class ByteSwap<bits<6> func, string instr_asm>:
377 FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
378 !strconcat(instr_asm, "\t$dst, $src"),
379 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
382 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
383 FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
384 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
385 [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
386 CPURegs:$cond, MovCode))], NoItinerary>;
388 //===----------------------------------------------------------------------===//
389 // Pseudo instructions
390 //===----------------------------------------------------------------------===//
392 // As stack alignment is always done with addiu, we need a 16-bit immediate
393 let Defs = [SP], Uses = [SP] in {
394 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
395 "!ADJCALLSTACKDOWN $amt",
396 [(callseq_start timm:$amt)]>;
397 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
398 "!ADJCALLSTACKUP $amt1",
399 [(callseq_end timm:$amt1, timm:$amt2)]>;
402 // Some assembly macros need to avoid pseudoinstructions and assembler
403 // automatic reodering, we should reorder ourselves.
404 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
405 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
406 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
407 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
409 // When handling PIC code the assembler needs .cpload and .cprestore
410 // directives. If the real instructions corresponding these directives
411 // are used, we have the same behavior, but get also a bunch of warnings
412 // from the assembler.
413 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
414 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
416 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
417 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
418 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
419 // replace it for real supported nodes into EmitInstrWithCustomInserter
420 let usesCustomInserter = 1 in {
421 class PseudoSelCC<RegisterClass RC, string asmstr>:
422 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
423 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
426 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
428 //===----------------------------------------------------------------------===//
429 // Instruction definition
430 //===----------------------------------------------------------------------===//
432 //===----------------------------------------------------------------------===//
433 // MipsI Instructions
434 //===----------------------------------------------------------------------===//
436 /// Arithmetic Instructions (ALU Immediate)
437 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
438 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
439 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
440 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
441 def ANDi : LogicI<0x0c, "andi", and>;
442 def ORi : LogicI<0x0d, "ori", or>;
443 def XORi : LogicI<0x0e, "xori", xor>;
444 def LUi : LoadUpper<0x0f, "lui">;
446 /// Arithmetic Instructions (3-Operand, R-Type)
447 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
448 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
449 def ADD : ArithOverflowR<0x00, 0x20, "add">;
450 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
451 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
452 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
453 def AND : LogicR<0x24, "and", and>;
454 def OR : LogicR<0x25, "or", or>;
455 def XOR : LogicR<0x26, "xor", xor>;
456 def NOR : LogicNOR<0x00, 0x27, "nor">;
458 /// Shift Instructions
459 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
460 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
461 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
462 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
463 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
464 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
466 /// Load and Store Instructions
467 def LB : LoadM<0x20, "lb", sextloadi8>;
468 def LBu : LoadM<0x24, "lbu", zextloadi8>;
469 def LH : LoadM<0x21, "lh", sextloadi16>;
470 def LHu : LoadM<0x25, "lhu", zextloadi16>;
471 def LW : LoadM<0x23, "lw", load>;
472 def SB : StoreM<0x28, "sb", truncstorei8>;
473 def SH : StoreM<0x29, "sh", truncstorei16>;
474 def SW : StoreM<0x2b, "sw", store>;
476 /// Jump and Branch Instructions
477 def J : JumpFJ<0x02, "j">;
478 def JR : JumpFR<0x00, 0x08, "jr">;
479 def JAL : JumpLink<0x03, "jal">;
480 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
481 def BEQ : CBranch<0x04, "beq", seteq>;
482 def BNE : CBranch<0x05, "bne", setne>;
485 def BGEZ : CBranchZero<0x01, "bgez", setge>;
488 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
489 def BLEZ : CBranchZero<0x07, "blez", setle>;
490 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
493 def BGEZAL : BranchLink<"bgezal">;
494 def BLTZAL : BranchLink<"bltzal">;
496 let isReturn=1, isTerminator=1, hasDelaySlot=1,
497 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
498 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
499 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
501 /// Multiply and Divide Instructions.
502 let Defs = [HI, LO] in {
503 def MULT : MulDiv<0x18, "mult", IIImul>;
504 def MULTu : MulDiv<0x19, "multu", IIImul>;
505 def DIV : MulDiv<0x1a, "div", IIIdiv>;
506 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
510 def MTHI : MoveToLOHI<0x11, "mthi">;
512 def MTLO : MoveToLOHI<0x13, "mtlo">;
515 def MFHI : MoveFromLOHI<0x10, "mfhi">;
517 def MFLO : MoveFromLOHI<0x12, "mflo">;
519 /// Sign Ext In Register Instructions.
520 let Predicates = [HasSEInReg] in {
521 let shamt = 0x10, rs = 0 in
522 def SEB : SignExtInReg<0x21, "seb", i8>;
524 let shamt = 0x18, rs = 0 in
525 def SEH : SignExtInReg<0x20, "seh", i16>;
529 let Predicates = [HasBitCount] in {
531 def CLZ : CountLeading<0b010110, "clz", ctlz>;
535 let Predicates = [HasSwap] in {
536 let shamt = 0x3, rs = 0 in
537 def WSBW : ByteSwap<0x20, "wsbw">;
541 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
542 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
544 let Predicates = [HasCondMov], Constraints = "$F = $dst" in {
545 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
546 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
551 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
553 // FrameIndexes are legalized when they are operands from load/store
554 // instructions. The same not happens for stack address copies, so an
555 // add op with mem ComplexPattern is used and the stack address copy
556 // can be matched. It's similar to Sparc LEA_ADDRi
557 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
559 // MADD*/MSUB* are not part of MipsI either.
560 //def MADD : MArithR<0x00, "madd">;
561 //def MADDU : MArithR<0x01, "maddu">;
562 //def MSUB : MArithR<0x04, "msub">;
563 //def MSUBU : MArithR<0x05, "msubu">;
565 // MUL is a assembly macro in the current used ISAs. In recent ISA's
566 // it is a real instruction.
567 //def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
569 //===----------------------------------------------------------------------===//
570 // Arbitrary patterns that map to one or more instructions
571 //===----------------------------------------------------------------------===//
574 def : Pat<(i32 immSExt16:$in),
575 (ADDiu ZERO, imm:$in)>;
576 def : Pat<(i32 immZExt16:$in),
577 (ORi ZERO, imm:$in)>;
579 // Arbitrary immediates
580 def : Pat<(i32 imm:$imm),
581 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
584 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
585 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
586 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
587 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
588 def : Pat<(addc CPURegs:$src, imm:$imm),
589 (ADDiu CPURegs:$src, imm:$imm)>;
592 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
593 (JAL tglobaladdr:$dst)>;
594 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
595 (JAL texternalsym:$dst)>;
596 //def : Pat<(MipsJmpLink CPURegs:$dst),
597 // (JALR CPURegs:$dst)>;
600 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
601 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
602 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
604 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
605 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
606 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
608 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
609 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
610 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
613 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
614 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
615 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
616 (ADDiu CPURegs:$gp, tconstpool:$in)>;
618 // Mips does not have "not", so we expand our way
619 def : Pat<(not CPURegs:$in),
620 (NOR CPURegs:$in, ZERO)>;
622 // extended load and stores
623 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
624 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
625 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
628 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
631 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
632 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
633 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
634 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
636 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
637 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
638 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
639 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
640 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
641 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
642 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
643 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
645 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
646 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
647 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
648 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
650 def : Pat<(brcond CPURegs:$cond, bb:$dst),
651 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
654 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
655 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
656 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
657 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
658 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
659 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
660 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
661 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
663 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
664 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
665 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
666 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
668 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
669 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
670 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
671 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
673 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
674 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
677 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
678 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
679 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
680 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
682 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
683 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
684 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
685 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
687 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
688 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
689 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
690 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
692 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
693 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
694 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
695 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
697 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
698 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
699 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
700 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
702 //===----------------------------------------------------------------------===//
703 // Floating Point Support
704 //===----------------------------------------------------------------------===//
706 include "MipsInstrFPU.td"