1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
190 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
191 let Predicates = [HasStdEnc];
195 bit isCommutable = 1;
212 bit isTerminator = 1;
215 bit hasExtraSrcRegAllocReq = 1;
216 bit isCodeGenOnly = 1;
219 class IsAsCheapAsAMove {
220 bit isAsCheapAsAMove = 1;
223 class NeverHasSideEffects {
224 bit neverHasSideEffects = 1;
227 //===----------------------------------------------------------------------===//
228 // Instruction format superclass
229 //===----------------------------------------------------------------------===//
231 include "MipsInstrFormats.td"
233 //===----------------------------------------------------------------------===//
234 // Mips Operand, Complex Patterns and Transformations Definitions.
235 //===----------------------------------------------------------------------===//
237 // Instruction operand types
238 def jmptarget : Operand<OtherVT> {
239 let EncoderMethod = "getJumpTargetOpValue";
241 def brtarget : Operand<OtherVT> {
242 let EncoderMethod = "getBranchTargetOpValue";
243 let OperandType = "OPERAND_PCREL";
244 let DecoderMethod = "DecodeBranchTarget";
246 def calltarget : Operand<iPTR> {
247 let EncoderMethod = "getJumpTargetOpValue";
249 def calltarget64: Operand<i64>;
250 def simm16 : Operand<i32> {
251 let DecoderMethod= "DecodeSimm16";
254 def simm20 : Operand<i32> {
257 def uimm20 : Operand<i32> {
260 def uimm10 : Operand<i32> {
263 def simm16_64 : Operand<i64>;
264 def shamt : Operand<i32>;
267 def uimm5 : Operand<i32> {
268 let PrintMethod = "printUnsignedImm";
271 def uimm16 : Operand<i32> {
272 let PrintMethod = "printUnsignedImm";
275 def MipsMemAsmOperand : AsmOperandClass {
277 let ParserMethod = "parseMemOperand";
281 def mem : Operand<iPTR> {
282 let PrintMethod = "printMemOperand";
283 let MIOperandInfo = (ops ptr_rc, simm16);
284 let EncoderMethod = "getMemEncoding";
285 let ParserMatchClass = MipsMemAsmOperand;
286 let OperandType = "OPERAND_MEMORY";
289 def mem_ea : Operand<iPTR> {
290 let PrintMethod = "printMemOperandEA";
291 let MIOperandInfo = (ops ptr_rc, simm16);
292 let EncoderMethod = "getMemEncoding";
293 let OperandType = "OPERAND_MEMORY";
296 def PtrRC : Operand<iPTR> {
297 let MIOperandInfo = (ops ptr_rc);
300 // size operand of ext instruction
301 def size_ext : Operand<i32> {
302 let EncoderMethod = "getSizeExtEncoding";
303 let DecoderMethod = "DecodeExtSize";
306 // size operand of ins instruction
307 def size_ins : Operand<i32> {
308 let EncoderMethod = "getSizeInsEncoding";
309 let DecoderMethod = "DecodeInsSize";
312 // Transformation Function - get the lower 16 bits.
313 def LO16 : SDNodeXForm<imm, [{
314 return getImm(N, N->getZExtValue() & 0xFFFF);
317 // Transformation Function - get the higher 16 bits.
318 def HI16 : SDNodeXForm<imm, [{
319 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
323 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
325 // Node immediate fits as 16-bit sign extended on target immediate.
327 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
329 // Node immediate fits as 16-bit sign extended on target immediate.
331 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
333 // Node immediate fits as 15-bit sign extended on target immediate.
335 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
337 // Node immediate fits as 16-bit zero extended on target immediate.
338 // The LO16 param means that only the lower 16 bits of the node
339 // immediate are caught.
341 def immZExt16 : PatLeaf<(imm), [{
342 if (N->getValueType(0) == MVT::i32)
343 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
345 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
348 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
349 def immLow16Zero : PatLeaf<(imm), [{
350 int64_t Val = N->getSExtValue();
351 return isInt<32>(Val) && !(Val & 0xffff);
354 // shamt field must fit in 5 bits.
355 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
357 // True if (N + 1) fits in 16-bit field.
358 def immSExt16Plus1 : PatLeaf<(imm), [{
359 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
362 // Mips Address Mode! SDNode frameindex could possibily be a match
363 // since load and store instructions from stack used it.
365 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
368 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
371 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
373 //===----------------------------------------------------------------------===//
374 // Instructions specific format
375 //===----------------------------------------------------------------------===//
377 // Arithmetic and logical instructions with 3 register operands.
378 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
379 InstrItinClass Itin = NoItinerary,
380 SDPatternOperator OpNode = null_frag>:
381 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
382 !strconcat(opstr, "\t$rd, $rs, $rt"),
383 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
384 let isCommutable = isComm;
385 let isReMaterializable = 1;
388 // Arithmetic and logical instructions with 2 register operands.
389 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
390 InstrItinClass Itin = NoItinerary,
391 SDPatternOperator imm_type = null_frag,
392 SDPatternOperator OpNode = null_frag> :
393 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
394 !strconcat(opstr, "\t$rt, $rs, $imm16"),
395 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
397 let isReMaterializable = 1;
398 let TwoOperandAliasConstraint = "$rs = $rt";
401 // Arithmetic Multiply ADD/SUB
402 class MArithR<string opstr, bit isComm = 0> :
403 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
404 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
405 let Defs = [HI0, LO0];
406 let Uses = [HI0, LO0];
407 let isCommutable = isComm;
411 class LogicNOR<string opstr, RegisterOperand RO>:
412 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
413 !strconcat(opstr, "\t$rd, $rs, $rt"),
414 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
415 let isCommutable = 1;
419 class shift_rotate_imm<string opstr, Operand ImmOpnd,
420 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
421 SDPatternOperator PF = null_frag> :
422 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
423 !strconcat(opstr, "\t$rd, $rt, $shamt"),
424 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
426 class shift_rotate_reg<string opstr, RegisterOperand RO,
427 SDPatternOperator OpNode = null_frag>:
428 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
429 !strconcat(opstr, "\t$rd, $rt, $rs"),
430 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
432 // Load Upper Imediate
433 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
434 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
435 [], IIArith, FrmI>, IsAsCheapAsAMove {
436 let neverHasSideEffects = 1;
437 let isReMaterializable = 1;
440 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
441 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
443 let Inst{25-21} = addr{20-16};
444 let Inst{15-0} = addr{15-0};
445 let DecoderMethod = "DecodeMem";
449 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
450 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
451 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
452 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
453 let DecoderMethod = "DecodeMem";
454 let canFoldAsLoad = 1;
458 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
459 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
460 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
461 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
462 let DecoderMethod = "DecodeMem";
466 // Load/Store Left/Right
467 let canFoldAsLoad = 1 in
468 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
469 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
470 !strconcat(opstr, "\t$rt, $addr"),
471 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
472 let DecoderMethod = "DecodeMem";
473 string Constraints = "$src = $rt";
476 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
477 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
478 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
479 let DecoderMethod = "DecodeMem";
482 // Conditional Branch
483 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
484 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
485 !strconcat(opstr, "\t$rs, $rt, $offset"),
486 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
489 let isTerminator = 1;
490 let hasDelaySlot = 1;
494 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
495 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
496 !strconcat(opstr, "\t$rs, $offset"),
497 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
499 let isTerminator = 1;
500 let hasDelaySlot = 1;
505 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
506 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
507 !strconcat(opstr, "\t$rd, $rs, $rt"),
508 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
511 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
513 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
514 !strconcat(opstr, "\t$rt, $rs, $imm16"),
515 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
519 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
520 SDPatternOperator targetoperator> :
521 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
522 [(operator targetoperator:$target)], IIBranch, FrmJ> {
525 let hasDelaySlot = 1;
526 let DecoderMethod = "DecodeJumpTarget";
530 // Unconditional branch
531 class UncondBranch<string opstr> :
532 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
533 [(br bb:$offset)], IIBranch, FrmI> {
535 let isTerminator = 1;
537 let hasDelaySlot = 1;
538 let Predicates = [RelocPIC, HasStdEnc];
542 // Base class for indirect branch and return instruction classes.
543 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
544 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
545 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
548 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
550 let isIndirectBranch = 1;
553 // Return instruction
554 class RetBase<RegisterOperand RO>: JumpFR<RO> {
556 let isCodeGenOnly = 1;
558 let hasExtraSrcRegAllocReq = 1;
561 // Jump and Link (Call)
562 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
563 class JumpLink<string opstr> :
564 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
565 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
566 let DecoderMethod = "DecodeJumpTarget";
569 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
570 Register RetReg, RegisterOperand ResRO = RO>:
571 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
572 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
574 class JumpLinkReg<string opstr, RegisterOperand RO>:
575 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
578 class BGEZAL_FT<string opstr, RegisterOperand RO> :
579 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
580 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
584 class BAL_BR_Pseudo<Instruction RealInst> :
585 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
586 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
588 let isTerminator = 1;
590 let hasDelaySlot = 1;
595 class SYS_FT<string opstr> :
596 InstSE<(outs), (ins uimm20:$code_),
597 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
599 class BRK_FT<string opstr> :
600 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
601 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
604 class ER_FT<string opstr> :
605 InstSE<(outs), (ins),
606 opstr, [], NoItinerary, FrmOther>;
609 class DEI_FT<string opstr, RegisterOperand RO> :
610 InstSE<(outs RO:$rt), (ins),
611 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
614 class WAIT_FT<string opstr> :
615 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
616 let Inst{31-26} = 0x10;
619 let Inst{5-0} = 0x20;
623 let hasSideEffects = 1 in
625 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
626 NoItinerary, FrmOther>;
628 let hasSideEffects = 1 in
629 class TEQ_FT<string opstr, RegisterOperand RO> :
630 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
631 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
634 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
635 list<Register> DefRegs> :
636 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
638 let isCommutable = 1;
640 let neverHasSideEffects = 1;
643 // Pseudo multiply/divide instruction with explicit accumulator register
645 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
646 SDPatternOperator OpNode, InstrItinClass Itin,
647 bit IsComm = 1, bit HasSideEffects = 0,
648 bit UsesCustomInserter = 0> :
649 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
650 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
651 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
652 let isCommutable = IsComm;
653 let hasSideEffects = HasSideEffects;
654 let usesCustomInserter = UsesCustomInserter;
657 // Pseudo multiply add/sub instruction with explicit accumulator register
659 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
660 : PseudoSE<(outs ACC64:$ac),
661 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
663 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
665 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
666 string Constraints = "$acin = $ac";
669 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
670 list<Register> DefRegs> :
671 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
677 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
678 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
680 let neverHasSideEffects = 1;
683 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
684 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
686 let neverHasSideEffects = 1;
689 class EffectiveAddress<string opstr, RegisterOperand RO> :
690 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
691 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
692 let isCodeGenOnly = 1;
693 let DecoderMethod = "DecodeMem";
696 // Count Leading Ones/Zeros in Word
697 class CountLeading0<string opstr, RegisterOperand RO>:
698 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
699 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
700 Requires<[HasBitCount, HasStdEnc]>;
702 class CountLeading1<string opstr, RegisterOperand RO>:
703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
704 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
705 Requires<[HasBitCount, HasStdEnc]>;
708 // Sign Extend in Register.
709 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
710 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
711 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
712 let Predicates = [HasSEInReg, HasStdEnc];
716 class SubwordSwap<string opstr, RegisterOperand RO>:
717 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
719 let Predicates = [HasSwap, HasStdEnc];
720 let neverHasSideEffects = 1;
724 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
725 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
729 class ExtBase<string opstr, RegisterOperand RO>:
730 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
731 !strconcat(opstr, " $rt, $rs, $pos, $size"),
732 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
734 let Predicates = [HasMips32r2, HasStdEnc];
737 class InsBase<string opstr, RegisterOperand RO>:
738 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
739 !strconcat(opstr, " $rt, $rs, $pos, $size"),
740 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
742 let Predicates = [HasMips32r2, HasStdEnc];
743 let Constraints = "$src = $rt";
746 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
747 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
748 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
749 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
751 // Atomic Compare & Swap.
752 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
753 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
754 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
756 class LLBase<string opstr, RegisterOperand RO> :
757 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
758 [], NoItinerary, FrmI> {
759 let DecoderMethod = "DecodeMem";
763 class SCBase<string opstr, RegisterOperand RO> :
764 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
765 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
766 let DecoderMethod = "DecodeMem";
768 let Constraints = "$rt = $dst";
771 class MFC3OP<dag outs, dag ins, string asmstr> :
772 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
774 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
775 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
776 let Inst = 0x0000000d;
779 //===----------------------------------------------------------------------===//
780 // Pseudo instructions
781 //===----------------------------------------------------------------------===//
784 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
785 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
787 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
788 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
789 [(callseq_start timm:$amt)]>;
790 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
791 [(callseq_end timm:$amt1, timm:$amt2)]>;
794 let usesCustomInserter = 1 in {
795 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
796 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
797 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
798 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
799 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
800 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
801 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
802 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
803 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
804 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
805 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
806 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
807 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
808 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
809 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
810 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
811 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
812 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
814 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
815 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
816 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
818 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
819 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
820 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
823 /// Pseudo instructions for loading and storing accumulator registers.
824 let isPseudo = 1, isCodeGenOnly = 1 in {
825 def LOAD_ACC64 : Load<"", ACC64>;
826 def STORE_ACC64 : Store<"", ACC64>;
829 //===----------------------------------------------------------------------===//
830 // Instruction definition
831 //===----------------------------------------------------------------------===//
832 //===----------------------------------------------------------------------===//
833 // MipsI Instructions
834 //===----------------------------------------------------------------------===//
836 /// Arithmetic Instructions (ALU Immediate)
837 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
839 ADDI_FM<0x9>, IsAsCheapAsAMove;
840 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
841 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
843 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
845 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
848 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
851 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
854 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
856 /// Arithmetic Instructions (3-Operand, R-Type)
857 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
859 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
861 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
863 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
864 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
865 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
866 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
867 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
869 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
871 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
873 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
875 /// Shift Instructions
876 def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>,
878 def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>,
880 def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>,
882 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
883 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
884 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
886 // Rotate Instructions
887 let Predicates = [HasMips32r2, HasStdEnc] in {
888 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr,
891 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
895 /// Load and Store Instructions
897 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
898 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
900 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
902 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
903 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
905 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
906 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
907 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
909 /// load/store left/right
910 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
911 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
912 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
913 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
915 def SYNC : SYNC_FT, SYNC_FM;
916 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
918 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
919 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
921 def ERET : ER_FT<"eret">, ER_FM<0x18>;
922 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
924 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
925 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
927 def WAIT : WAIT_FT<"wait">;
929 /// Load-linked, Store-conditional
930 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
931 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
933 /// Jump and Branch Instructions
934 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
935 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
936 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
937 def B : UncondBranch<"b">, B_FM;
938 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
939 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
940 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
941 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
942 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
943 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
945 def JAL : JumpLink<"jal">, FJ<3>;
946 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
947 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
948 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
949 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
950 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
951 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
952 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
954 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
956 // Exception handling related node and instructions.
957 // The conversion sequence is:
958 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
959 // MIPSeh_return -> (stack change + indirect branch)
961 // MIPSeh_return takes the place of regular return instruction
962 // but takes two arguments (V1, V0) which are used for storing
963 // the offset and return address respectively.
964 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
966 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
967 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
969 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
970 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
971 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
972 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
974 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
977 /// Multiply and Divide Instructions.
978 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
980 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
982 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
983 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
984 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
985 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
986 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
988 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
991 def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
992 def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
993 def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
994 def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
996 /// Sign Ext In Register Instructions.
997 def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
998 def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1001 def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1002 def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1004 /// Word Swap Bytes Within Halfwords
1005 def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1008 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1010 // FrameIndexes are legalized when they are operands from load/store
1011 // instructions. The same not happens for stack address copies, so an
1012 // add op with mem ComplexPattern is used and the stack address copy
1013 // can be matched. It's similar to Sparc LEA_ADDRi
1014 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1017 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1018 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1019 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1020 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1021 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1022 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1023 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1024 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1026 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1028 def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>;
1029 def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>;
1031 /// Move Control Registers From/To CPU Registers
1032 def MFC0_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1033 (ins GPR32Opnd:$rd, uimm16:$sel),
1034 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1036 def MTC0_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1037 (ins GPR32Opnd:$rt),
1038 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1040 def MFC2_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1041 (ins GPR32Opnd:$rd, uimm16:$sel),
1042 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1044 def MTC2_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1045 (ins GPR32Opnd:$rt),
1046 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1048 //===----------------------------------------------------------------------===//
1049 // Instruction aliases
1050 //===----------------------------------------------------------------------===//
1051 def : InstAlias<"move $dst, $src",
1052 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1053 Requires<[NotMips64]>;
1054 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1055 def : InstAlias<"addu $rs, $rt, $imm",
1056 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1057 def : InstAlias<"add $rs, $rt, $imm",
1058 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1059 def : InstAlias<"and $rs, $rt, $imm",
1060 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1061 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1062 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1063 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1064 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1065 def : InstAlias<"not $rt, $rs",
1066 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1067 def : InstAlias<"neg $rt, $rs",
1068 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1069 def : InstAlias<"negu $rt, $rs",
1070 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1071 def : InstAlias<"slt $rs, $rt, $imm",
1072 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1073 def : InstAlias<"xor $rs, $rt, $imm",
1074 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1075 def : InstAlias<"or $rs, $rt, $imm",
1076 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1077 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1078 def : InstAlias<"mfc0 $rt, $rd",
1079 (MFC0_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1080 def : InstAlias<"mtc0 $rt, $rd",
1081 (MTC0_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1082 def : InstAlias<"mfc2 $rt, $rd",
1083 (MFC2_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1084 def : InstAlias<"mtc2 $rt, $rd",
1085 (MTC2_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1086 def : InstAlias<"bnez $rs,$offset",
1087 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1088 def : InstAlias<"beqz $rs,$offset",
1089 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1090 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1092 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1093 def : InstAlias<"break", (BREAK 0, 0), 1>;
1094 def : InstAlias<"ei", (EI ZERO), 1>;
1095 def : InstAlias<"di", (DI ZERO), 1>;
1096 //===----------------------------------------------------------------------===//
1097 // Assembler Pseudo Instructions
1098 //===----------------------------------------------------------------------===//
1100 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1101 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1102 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1103 def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>;
1105 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1106 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1107 !strconcat(instr_asm, "\t$rt, $addr")> ;
1108 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1110 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1111 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1112 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1113 def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>;
1117 //===----------------------------------------------------------------------===//
1118 // Arbitrary patterns that map to one or more instructions
1119 //===----------------------------------------------------------------------===//
1121 // Load/store pattern templates.
1122 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1123 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1125 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1126 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1129 def : MipsPat<(i32 immSExt16:$in),
1130 (ADDiu ZERO, imm:$in)>;
1131 def : MipsPat<(i32 immZExt16:$in),
1132 (ORi ZERO, imm:$in)>;
1133 def : MipsPat<(i32 immLow16Zero:$in),
1134 (LUi (HI16 imm:$in))>;
1136 // Arbitrary immediates
1137 def : MipsPat<(i32 imm:$imm),
1138 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1140 // Carry MipsPatterns
1141 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1142 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1143 let Predicates = [HasStdEnc, NotDSP] in {
1144 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1145 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1146 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1147 (ADDiu GPR32:$src, imm:$imm)>;
1151 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1152 (JAL tglobaladdr:$dst)>;
1153 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1154 (JAL texternalsym:$dst)>;
1155 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1156 // (JALR GPR32:$dst)>;
1159 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1160 (TAILCALL tglobaladdr:$dst)>;
1161 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1162 (TAILCALL texternalsym:$dst)>;
1164 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1165 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1166 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1167 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1168 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1169 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1171 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1172 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1173 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1174 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1175 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1176 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1178 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1179 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1180 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1181 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1182 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1183 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1184 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1185 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1186 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1187 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1190 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1191 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1192 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1193 (ADDiu GPR32:$gp, tconstpool:$in)>;
1196 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1197 MipsPat<(MipsWrapper RC:$gp, node:$in),
1198 (ADDiuOp RC:$gp, node:$in)>;
1200 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1201 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1202 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1203 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1204 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1205 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1207 // Mips does not have "not", so we expand our way
1208 def : MipsPat<(not GPR32:$in),
1209 (NOR GPR32Opnd:$in, ZERO)>;
1212 let Predicates = [HasStdEnc] in {
1213 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1214 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1215 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1219 let Predicates = [HasStdEnc] in
1220 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1223 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1224 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1225 Instruction SLTiuOp, Register ZEROReg> {
1226 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1227 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1228 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1229 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1231 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1232 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1233 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1234 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1235 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1236 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1237 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1238 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1239 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1240 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1241 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1242 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1244 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1245 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1246 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1247 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1249 def : MipsPat<(brcond RC:$cond, bb:$dst),
1250 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1253 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1255 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1256 (BLEZ i32:$lhs, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1258 (BGEZ i32:$lhs, bb:$dst)>;
1261 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1262 Instruction SLTuOp, Register ZEROReg> {
1263 def : MipsPat<(seteq RC:$lhs, 0),
1264 (SLTiuOp RC:$lhs, 1)>;
1265 def : MipsPat<(setne RC:$lhs, 0),
1266 (SLTuOp ZEROReg, RC:$lhs)>;
1267 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1268 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1269 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1270 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1273 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1274 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1275 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1276 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1277 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1280 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1281 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1282 (SLTOp RC:$rhs, RC:$lhs)>;
1283 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1284 (SLTuOp RC:$rhs, RC:$lhs)>;
1287 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1288 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1289 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1290 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1291 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1294 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1295 Instruction SLTiuOp> {
1296 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1297 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1298 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1299 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1302 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1303 defm : SetlePats<GPR32, SLT, SLTu>;
1304 defm : SetgtPats<GPR32, SLT, SLTu>;
1305 defm : SetgePats<GPR32, SLT, SLTu>;
1306 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1309 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1311 // mflo/hi patterns.
1312 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1313 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1315 // Load halfword/word patterns.
1316 let AddedComplexity = 40 in {
1317 let Predicates = [HasStdEnc] in {
1318 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1319 def : LoadRegImmPat<LH, i32, sextloadi16>;
1320 def : LoadRegImmPat<LW, i32, load>;
1324 //===----------------------------------------------------------------------===//
1325 // Floating Point Support
1326 //===----------------------------------------------------------------------===//
1328 include "MipsInstrFPU.td"
1329 include "Mips64InstrInfo.td"
1330 include "MipsCondMov.td"
1335 include "Mips16InstrFormats.td"
1336 include "Mips16InstrInfo.td"
1339 include "MipsDSPInstrFormats.td"
1340 include "MipsDSPInstrInfo.td"
1343 include "MipsMSAInstrFormats.td"
1344 include "MipsMSAInstrInfo.td"
1347 include "MicroMipsInstrFormats.td"
1348 include "MicroMipsInstrInfo.td"