1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
186 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
187 let Predicates = [HasStdEnc];
191 bit isCommutable = 1;
208 bit isTerminator = 1;
211 bit hasExtraSrcRegAllocReq = 1;
212 bit isCodeGenOnly = 1;
215 class IsAsCheapAsAMove {
216 bit isAsCheapAsAMove = 1;
219 class NeverHasSideEffects {
220 bit neverHasSideEffects = 1;
223 //===----------------------------------------------------------------------===//
224 // Instruction format superclass
225 //===----------------------------------------------------------------------===//
227 include "MipsInstrFormats.td"
229 //===----------------------------------------------------------------------===//
230 // Mips Operand, Complex Patterns and Transformations Definitions.
231 //===----------------------------------------------------------------------===//
233 // Instruction operand types
234 def jmptarget : Operand<OtherVT> {
235 let EncoderMethod = "getJumpTargetOpValue";
237 def brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getBranchTargetOpValue";
239 let OperandType = "OPERAND_PCREL";
240 let DecoderMethod = "DecodeBranchTarget";
242 def calltarget : Operand<iPTR> {
243 let EncoderMethod = "getJumpTargetOpValue";
245 def calltarget64: Operand<i64>;
246 def simm16 : Operand<i32> {
247 let DecoderMethod= "DecodeSimm16";
250 def simm20 : Operand<i32> {
253 def simm16_64 : Operand<i64>;
254 def shamt : Operand<i32>;
257 def uimm16 : Operand<i32> {
258 let PrintMethod = "printUnsignedImm";
261 def MipsMemAsmOperand : AsmOperandClass {
263 let ParserMethod = "parseMemOperand";
267 def mem : Operand<i32> {
268 let PrintMethod = "printMemOperand";
269 let MIOperandInfo = (ops CPURegs, simm16);
270 let EncoderMethod = "getMemEncoding";
271 let ParserMatchClass = MipsMemAsmOperand;
272 let OperandType = "OPERAND_MEMORY";
275 def mem64 : Operand<i64> {
276 let PrintMethod = "printMemOperand";
277 let MIOperandInfo = (ops CPU64Regs, simm16_64);
278 let EncoderMethod = "getMemEncoding";
279 let ParserMatchClass = MipsMemAsmOperand;
280 let OperandType = "OPERAND_MEMORY";
283 def mem_ea : Operand<i32> {
284 let PrintMethod = "printMemOperandEA";
285 let MIOperandInfo = (ops CPURegs, simm16);
286 let EncoderMethod = "getMemEncoding";
287 let OperandType = "OPERAND_MEMORY";
290 def mem_ea_64 : Operand<i64> {
291 let PrintMethod = "printMemOperandEA";
292 let MIOperandInfo = (ops CPU64Regs, simm16_64);
293 let EncoderMethod = "getMemEncoding";
294 let OperandType = "OPERAND_MEMORY";
297 // size operand of ext instruction
298 def size_ext : Operand<i32> {
299 let EncoderMethod = "getSizeExtEncoding";
300 let DecoderMethod = "DecodeExtSize";
303 // size operand of ins instruction
304 def size_ins : Operand<i32> {
305 let EncoderMethod = "getSizeInsEncoding";
306 let DecoderMethod = "DecodeInsSize";
309 // Transformation Function - get the lower 16 bits.
310 def LO16 : SDNodeXForm<imm, [{
311 return getImm(N, N->getZExtValue() & 0xFFFF);
314 // Transformation Function - get the higher 16 bits.
315 def HI16 : SDNodeXForm<imm, [{
316 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
320 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
322 // Node immediate fits as 16-bit sign extended on target immediate.
324 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
326 // Node immediate fits as 16-bit sign extended on target immediate.
328 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
330 // Node immediate fits as 15-bit sign extended on target immediate.
332 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
334 // Node immediate fits as 16-bit zero extended on target immediate.
335 // The LO16 param means that only the lower 16 bits of the node
336 // immediate are caught.
338 def immZExt16 : PatLeaf<(imm), [{
339 if (N->getValueType(0) == MVT::i32)
340 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
342 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
345 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
346 def immLow16Zero : PatLeaf<(imm), [{
347 int64_t Val = N->getSExtValue();
348 return isInt<32>(Val) && !(Val & 0xffff);
351 // shamt field must fit in 5 bits.
352 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
354 // True if (N + 1) fits in 16-bit field.
355 def immSExt16Plus1 : PatLeaf<(imm), [{
356 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
359 // Mips Address Mode! SDNode frameindex could possibily be a match
360 // since load and store instructions from stack used it.
362 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
365 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
368 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
370 //===----------------------------------------------------------------------===//
371 // Instructions specific format
372 //===----------------------------------------------------------------------===//
374 // Arithmetic and logical instructions with 3 register operands.
375 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
376 InstrItinClass Itin = NoItinerary,
377 SDPatternOperator OpNode = null_frag>:
378 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
379 !strconcat(opstr, "\t$rd, $rs, $rt"),
380 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
381 let isCommutable = isComm;
382 let isReMaterializable = 1;
385 // Arithmetic and logical instructions with 2 register operands.
386 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
387 SDPatternOperator imm_type = null_frag,
388 SDPatternOperator OpNode = null_frag> :
389 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
390 !strconcat(opstr, "\t$rt, $rs, $imm16"),
391 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
392 IIAlu, FrmI, opstr> {
393 let isReMaterializable = 1;
394 let TwoOperandAliasConstraint = "$rs = $rt";
397 // Arithmetic Multiply ADD/SUB
398 class MArithR<string opstr, bit isComm = 0> :
399 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
400 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> {
403 let isCommutable = isComm;
407 class LogicNOR<string opstr, RegisterOperand RC>:
408 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
409 !strconcat(opstr, "\t$rd, $rs, $rt"),
410 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
411 let isCommutable = 1;
415 class shift_rotate_imm<string opstr, Operand ImmOpnd,
416 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
417 SDPatternOperator PF = null_frag> :
418 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
419 !strconcat(opstr, "\t$rd, $rt, $shamt"),
420 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>;
422 class shift_rotate_reg<string opstr, RegisterOperand RC,
423 SDPatternOperator OpNode = null_frag>:
424 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
425 !strconcat(opstr, "\t$rd, $rt, $rs"),
426 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>;
428 // Load Upper Imediate
429 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
430 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
431 [], IIAlu, FrmI>, IsAsCheapAsAMove {
432 let neverHasSideEffects = 1;
433 let isReMaterializable = 1;
436 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
437 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
439 let Inst{25-21} = addr{20-16};
440 let Inst{15-0} = addr{15-0};
441 let DecoderMethod = "DecodeMem";
445 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
446 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
447 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
448 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
449 !strconcat(opstr, ofsuffix)> {
450 let DecoderMethod = "DecodeMem";
451 let canFoldAsLoad = 1;
455 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
456 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
457 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
458 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
459 !strconcat(opstr, ofsuffix)> {
460 let DecoderMethod = "DecodeMem";
464 multiclass LoadM<string opstr, RegisterClass RC,
465 SDPatternOperator OpNode = null_frag,
466 ComplexPattern Addr = addr> {
467 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">,
468 Requires<[NotN64, HasStdEnc]>;
469 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">,
470 Requires<[IsN64, HasStdEnc]> {
471 let DecoderNamespace = "Mips64";
472 let isCodeGenOnly = 1;
476 multiclass StoreM<string opstr, RegisterClass RC,
477 SDPatternOperator OpNode = null_frag,
478 ComplexPattern Addr = addr> {
479 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">,
480 Requires<[NotN64, HasStdEnc]>;
481 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">,
482 Requires<[IsN64, HasStdEnc]> {
483 let DecoderNamespace = "Mips64";
484 let isCodeGenOnly = 1;
488 // Load/Store Left/Right
489 let canFoldAsLoad = 1 in
490 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
492 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
493 !strconcat(opstr, "\t$rt, $addr"),
494 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
495 let DecoderMethod = "DecodeMem";
496 string Constraints = "$src = $rt";
499 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
501 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
502 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
503 let DecoderMethod = "DecodeMem";
506 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
507 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
508 Requires<[NotN64, HasStdEnc]>;
509 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
510 Requires<[IsN64, HasStdEnc]> {
511 let DecoderNamespace = "Mips64";
512 let isCodeGenOnly = 1;
516 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
517 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
518 Requires<[NotN64, HasStdEnc]>;
519 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
520 Requires<[IsN64, HasStdEnc]> {
521 let DecoderNamespace = "Mips64";
522 let isCodeGenOnly = 1;
526 // Conditional Branch
527 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
528 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
529 !strconcat(opstr, "\t$rs, $rt, $offset"),
530 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
533 let isTerminator = 1;
534 let hasDelaySlot = 1;
538 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
539 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
540 !strconcat(opstr, "\t$rs, $offset"),
541 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
543 let isTerminator = 1;
544 let hasDelaySlot = 1;
549 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
550 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
551 !strconcat(opstr, "\t$rd, $rs, $rt"),
552 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
555 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
557 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
558 !strconcat(opstr, "\t$rt, $rs, $imm16"),
559 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
563 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
564 SDPatternOperator targetoperator> :
565 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
566 [(operator targetoperator:$target)], IIBranch, FrmJ> {
569 let hasDelaySlot = 1;
570 let DecoderMethod = "DecodeJumpTarget";
574 // Unconditional branch
575 class UncondBranch<string opstr> :
576 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
577 [(br bb:$offset)], IIBranch, FrmI> {
579 let isTerminator = 1;
581 let hasDelaySlot = 1;
582 let Predicates = [RelocPIC, HasStdEnc];
586 // Base class for indirect branch and return instruction classes.
587 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
588 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
589 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
592 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
594 let isIndirectBranch = 1;
597 // Return instruction
598 class RetBase<RegisterClass RC>: JumpFR<RC> {
600 let isCodeGenOnly = 1;
602 let hasExtraSrcRegAllocReq = 1;
605 // Jump and Link (Call)
606 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
607 class JumpLink<string opstr> :
608 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
609 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
610 let DecoderMethod = "DecodeJumpTarget";
613 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
615 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
616 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
618 class JumpLinkReg<string opstr, RegisterClass RC>:
619 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
622 class BGEZAL_FT<string opstr, RegisterOperand RO> :
623 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
624 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
629 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
631 let isTerminator = 1;
633 let hasDelaySlot = 1;
638 let hasSideEffects = 1 in
640 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
641 NoItinerary, FrmOther>;
643 let hasSideEffects = 1 in
644 class TEQ_FT<string opstr, RegisterOperand RO> :
645 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
646 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
649 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
650 list<Register> DefRegs> :
651 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
653 let isCommutable = 1;
655 let neverHasSideEffects = 1;
658 // Pseudo multiply/divide instruction with explicit accumulator register
660 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
661 SDPatternOperator OpNode, InstrItinClass Itin,
662 bit IsComm = 1, bit HasSideEffects = 0,
663 bit UsesCustomInserter = 0> :
664 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
665 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
666 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
667 let isCommutable = IsComm;
668 let hasSideEffects = HasSideEffects;
669 let usesCustomInserter = UsesCustomInserter;
672 // Pseudo multiply add/sub instruction with explicit accumulator register
674 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
675 : PseudoSE<(outs ACRegs:$ac),
676 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
678 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
680 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
681 string Constraints = "$acin = $ac";
684 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
685 list<Register> DefRegs> :
686 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
692 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
693 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
695 let neverHasSideEffects = 1;
698 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
699 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
701 let neverHasSideEffects = 1;
704 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
705 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
706 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
707 let isCodeGenOnly = 1;
708 let DecoderMethod = "DecodeMem";
711 // Count Leading Ones/Zeros in Word
712 class CountLeading0<string opstr, RegisterOperand RO>:
713 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
714 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
715 Requires<[HasBitCount, HasStdEnc]>;
717 class CountLeading1<string opstr, RegisterOperand RO>:
718 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
719 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
720 Requires<[HasBitCount, HasStdEnc]>;
723 // Sign Extend in Register.
724 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
725 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
726 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
727 let Predicates = [HasSEInReg, HasStdEnc];
731 class SubwordSwap<string opstr, RegisterOperand RO>:
732 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
734 let Predicates = [HasSwap, HasStdEnc];
735 let neverHasSideEffects = 1;
739 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
740 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
744 class ExtBase<string opstr, RegisterOperand RO>:
745 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
746 !strconcat(opstr, " $rt, $rs, $pos, $size"),
747 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
749 let Predicates = [HasMips32r2, HasStdEnc];
752 class InsBase<string opstr, RegisterOperand RO>:
753 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
754 !strconcat(opstr, " $rt, $rs, $pos, $size"),
755 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
757 let Predicates = [HasMips32r2, HasStdEnc];
758 let Constraints = "$src = $rt";
761 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
762 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
763 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
764 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
766 multiclass Atomic2Ops32<PatFrag Op> {
767 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
768 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
769 Requires<[IsN64, HasStdEnc]> {
770 let DecoderNamespace = "Mips64";
774 // Atomic Compare & Swap.
775 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
776 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
777 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
779 multiclass AtomicCmpSwap32<PatFrag Op> {
780 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
781 Requires<[NotN64, HasStdEnc]>;
782 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
783 Requires<[IsN64, HasStdEnc]> {
784 let DecoderNamespace = "Mips64";
788 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
789 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
790 [], NoItinerary, FrmI> {
791 let DecoderMethod = "DecodeMem";
795 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
796 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
797 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
798 let DecoderMethod = "DecodeMem";
800 let Constraints = "$rt = $dst";
803 class MFC3OP<dag outs, dag ins, string asmstr> :
804 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
806 //===----------------------------------------------------------------------===//
807 // Pseudo instructions
808 //===----------------------------------------------------------------------===//
811 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
812 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
814 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
815 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
816 [(callseq_start timm:$amt)]>;
817 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
818 [(callseq_end timm:$amt1, timm:$amt2)]>;
821 let usesCustomInserter = 1 in {
822 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
823 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
824 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
825 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
826 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
827 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
828 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
829 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
830 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
831 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
832 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
833 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
834 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
835 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
836 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
837 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
838 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
839 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
841 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
842 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
843 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
845 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
846 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
847 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
850 /// Pseudo instructions for loading and storing accumulator registers.
851 let isPseudo = 1 in {
852 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
853 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
856 //===----------------------------------------------------------------------===//
857 // Instruction definition
858 //===----------------------------------------------------------------------===//
859 //===----------------------------------------------------------------------===//
860 // MipsI Instructions
861 //===----------------------------------------------------------------------===//
863 /// Arithmetic Instructions (ALU Immediate)
864 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
865 ADDI_FM<0x9>, IsAsCheapAsAMove;
866 def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
867 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
869 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
871 def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
873 def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
875 def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
877 def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
879 /// Arithmetic Instructions (3-Operand, R-Type)
880 def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
882 def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
884 def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
886 def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
887 def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
888 def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
889 def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
890 def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
892 def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
894 def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
896 def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
898 /// Shift Instructions
899 def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
901 def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
903 def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
905 def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
906 def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
907 def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
909 // Rotate Instructions
910 let Predicates = [HasMips32r2, HasStdEnc] in {
911 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr,
914 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>,
918 /// Load and Store Instructions
920 defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>;
921 defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>;
922 defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>;
923 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>;
924 defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>;
925 defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>;
926 defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>;
927 defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>;
929 /// load/store left/right
930 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
931 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
932 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
933 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
935 def SYNC : SYNC_FT, SYNC_FM;
936 def TEQ : TEQ_FT<"teq", CPURegsOpnd>, TEQ_FM<0x34>;
938 /// Load-linked, Store-conditional
939 let Predicates = [NotN64, HasStdEnc] in {
940 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
941 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
944 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
945 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
946 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
949 /// Jump and Branch Instructions
950 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
951 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
952 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
953 def B : UncondBranch<"b">, B_FM;
954 def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
955 def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
956 def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>;
957 def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>;
958 def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
959 def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
961 def BAL_BR: BAL_FT, BAL_FM;
963 def JAL : JumpLink<"jal">, FJ<3>;
964 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
965 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
966 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
967 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
968 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
969 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
971 def RET : RetBase<CPURegs>, MTLO_FM<8>;
973 // Exception handling related node and instructions.
974 // The conversion sequence is:
975 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
976 // MIPSeh_return -> (stack change + indirect branch)
978 // MIPSeh_return takes the place of regular return instruction
979 // but takes two arguments (V1, V0) which are used for storing
980 // the offset and return address respectively.
981 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
983 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
984 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
986 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
987 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
988 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
989 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
991 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
994 /// Multiply and Divide Instructions.
995 def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
997 def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
999 def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
1000 def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
1001 def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
1002 def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
1003 def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv,
1005 def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
1008 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
1009 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
1010 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
1011 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
1013 /// Sign Ext In Register Instructions.
1014 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
1015 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
1018 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
1019 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
1021 /// Word Swap Bytes Within Halfwords
1022 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
1025 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1027 // FrameIndexes are legalized when they are operands from load/store
1028 // instructions. The same not happens for stack address copies, so an
1029 // add op with mem ComplexPattern is used and the stack address copy
1030 // can be matched. It's similar to Sparc LEA_ADDRi
1031 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
1034 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1035 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1036 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1037 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1038 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1039 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1040 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1041 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1043 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
1045 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
1046 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
1048 /// Move Control Registers From/To CPU Registers
1049 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1050 (ins CPURegsOpnd:$rd, uimm16:$sel),
1051 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1053 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1054 (ins CPURegsOpnd:$rt),
1055 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1057 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1058 (ins CPURegsOpnd:$rd, uimm16:$sel),
1059 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1061 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1062 (ins CPURegsOpnd:$rt),
1063 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1065 //===----------------------------------------------------------------------===//
1066 // Instruction aliases
1067 //===----------------------------------------------------------------------===//
1068 def : InstAlias<"move $dst, $src",
1069 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1070 Requires<[NotMips64]>;
1071 def : InstAlias<"move $dst, $src",
1072 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1073 Requires<[NotMips64]>;
1074 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
1075 def : InstAlias<"addu $rs, $rt, $imm",
1076 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1077 def : InstAlias<"add $rs, $rt, $imm",
1078 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1079 def : InstAlias<"and $rs, $rt, $imm",
1080 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1081 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
1082 Requires<[NotMips64]>;
1083 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
1084 def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>;
1085 def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>,
1086 Requires<[NotMips64]>;
1087 def : InstAlias<"not $rt, $rs",
1088 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1089 def : InstAlias<"neg $rt, $rs",
1090 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1091 def : InstAlias<"negu $rt, $rs",
1092 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1093 def : InstAlias<"slt $rs, $rt, $imm",
1094 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
1095 def : InstAlias<"xor $rs, $rt, $imm",
1096 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1097 Requires<[NotMips64]>;
1098 def : InstAlias<"or $rs, $rt, $imm",
1099 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1100 Requires<[NotMips64]>;
1101 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1102 def : InstAlias<"mfc0 $rt, $rd",
1103 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1104 def : InstAlias<"mtc0 $rt, $rd",
1105 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1106 def : InstAlias<"mfc2 $rt, $rd",
1107 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1108 def : InstAlias<"mtc2 $rt, $rd",
1109 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1110 def : InstAlias<"bnez $rs,$offset",
1111 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1112 Requires<[NotMips64]>;
1113 def : InstAlias<"beqz $rs,$offset",
1114 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1115 Requires<[NotMips64]>;
1116 //===----------------------------------------------------------------------===//
1117 // Assembler Pseudo Instructions
1118 //===----------------------------------------------------------------------===//
1120 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1121 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1122 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1123 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1125 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1126 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1127 !strconcat(instr_asm, "\t$rt, $addr")> ;
1128 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1130 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1131 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1132 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1133 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1137 //===----------------------------------------------------------------------===//
1138 // Arbitrary patterns that map to one or more instructions
1139 //===----------------------------------------------------------------------===//
1141 // Load/store pattern templates.
1142 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1143 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1145 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1146 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1149 def : MipsPat<(i32 immSExt16:$in),
1150 (ADDiu ZERO, imm:$in)>;
1151 def : MipsPat<(i32 immZExt16:$in),
1152 (ORi ZERO, imm:$in)>;
1153 def : MipsPat<(i32 immLow16Zero:$in),
1154 (LUi (HI16 imm:$in))>;
1156 // Arbitrary immediates
1157 def : MipsPat<(i32 imm:$imm),
1158 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1160 // Carry MipsPatterns
1161 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1162 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1163 let Predicates = [HasStdEnc, NotDSP] in {
1164 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1165 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1166 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1167 (ADDiu CPURegs:$src, imm:$imm)>;
1171 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1172 (JAL tglobaladdr:$dst)>;
1173 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1174 (JAL texternalsym:$dst)>;
1175 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1176 // (JALR CPURegs:$dst)>;
1179 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1180 (TAILCALL tglobaladdr:$dst)>;
1181 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1182 (TAILCALL texternalsym:$dst)>;
1184 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1185 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1186 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1187 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1188 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1189 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1191 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1192 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1193 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1194 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1195 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1196 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1198 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1199 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1200 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1201 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1202 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1203 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1204 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1205 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1206 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1207 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1210 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1211 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1212 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1213 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1216 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1217 MipsPat<(MipsWrapper RC:$gp, node:$in),
1218 (ADDiuOp RC:$gp, node:$in)>;
1220 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1221 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1222 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1223 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1224 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1225 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1227 // Mips does not have "not", so we expand our way
1228 def : MipsPat<(not CPURegs:$in),
1229 (NOR CPURegsOpnd:$in, ZERO)>;
1232 let Predicates = [NotN64, HasStdEnc] in {
1233 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1234 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1235 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1237 let Predicates = [IsN64, HasStdEnc] in {
1238 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1239 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1240 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1244 let Predicates = [NotN64, HasStdEnc] in {
1245 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1247 let Predicates = [IsN64, HasStdEnc] in {
1248 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1252 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1253 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1254 Instruction SLTiuOp, Register ZEROReg> {
1255 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1256 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1258 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1260 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1261 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1262 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1263 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1264 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1265 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1266 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1267 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1269 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1270 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1271 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1272 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1274 def : MipsPat<(brcond RC:$cond, bb:$dst),
1275 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1278 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1280 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1281 (BLEZ i32:$lhs, bb:$dst)>;
1282 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1283 (BGEZ i32:$lhs, bb:$dst)>;
1286 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1287 Instruction SLTuOp, Register ZEROReg> {
1288 def : MipsPat<(seteq RC:$lhs, 0),
1289 (SLTiuOp RC:$lhs, 1)>;
1290 def : MipsPat<(setne RC:$lhs, 0),
1291 (SLTuOp ZEROReg, RC:$lhs)>;
1292 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1293 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1294 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1295 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1298 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1299 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1300 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1301 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1302 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1305 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1306 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1307 (SLTOp RC:$rhs, RC:$lhs)>;
1308 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1309 (SLTuOp RC:$rhs, RC:$lhs)>;
1312 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1313 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1314 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1315 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1316 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1319 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1320 Instruction SLTiuOp> {
1321 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1322 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1323 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1324 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1327 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1328 defm : SetlePats<CPURegs, SLT, SLTu>;
1329 defm : SetgtPats<CPURegs, SLT, SLTu>;
1330 defm : SetgePats<CPURegs, SLT, SLTu>;
1331 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1334 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1336 // mflo/hi patterns.
1337 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1338 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1340 // Load halfword/word patterns.
1341 let AddedComplexity = 40 in {
1342 let Predicates = [NotN64, HasStdEnc] in {
1343 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1344 def : LoadRegImmPat<LH, i32, sextloadi16>;
1345 def : LoadRegImmPat<LW, i32, load>;
1347 let Predicates = [IsN64, HasStdEnc] in {
1348 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1349 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1350 def : LoadRegImmPat<LW_P8, i32, load>;
1354 //===----------------------------------------------------------------------===//
1355 // Floating Point Support
1356 //===----------------------------------------------------------------------===//
1358 include "MipsInstrFPU.td"
1359 include "Mips64InstrInfo.td"
1360 include "MipsCondMov.td"
1365 include "Mips16InstrFormats.td"
1366 include "Mips16InstrInfo.td"
1369 include "MipsDSPInstrFormats.td"
1370 include "MipsDSPInstrInfo.td"
1373 include "MicroMipsInstrFormats.td"
1374 include "MicroMipsInstrInfo.td"