1 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
31 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
32 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag,
35 // Hi and Lo nodes are used to handle global addresses. Used on
36 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
37 // static model. (nothing to do with Mips Registers Hi and Lo)
38 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
39 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
40 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
43 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
46 // These are target-independent nodes, but have target-specific formats.
47 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
48 [SDNPHasChain, SDNPOutFlag]>;
49 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
50 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
52 // Select Condition Code
53 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
56 def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
58 //===----------------------------------------------------------------------===//
59 // Mips Instruction Predicate Definitions.
60 //===----------------------------------------------------------------------===//
61 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
62 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
63 def HasSwap : Predicate<"Subtarget.hasSwap()">;
64 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
66 //===----------------------------------------------------------------------===//
67 // Mips Operand, Complex Patterns and Transformations Definitions.
68 //===----------------------------------------------------------------------===//
70 // Instruction operand types
71 def brtarget : Operand<OtherVT>;
72 def calltarget : Operand<i32>;
73 def simm16 : Operand<i32>;
74 def shamt : Operand<i32>;
77 def uimm16 : Operand<i32> {
78 let PrintMethod = "printUnsignedImm";
82 def mem : Operand<i32> {
83 let PrintMethod = "printMemOperand";
84 let MIOperandInfo = (ops simm16, CPURegs);
87 // Transformation Function - get the lower 16 bits.
88 def LO16 : SDNodeXForm<imm, [{
89 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
92 // Transformation Function - get the higher 16 bits.
93 def HI16 : SDNodeXForm<imm, [{
94 return getI32Imm((unsigned)N->getZExtValue() >> 16);
97 // Node immediate fits as 16-bit sign extended on target immediate.
99 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
101 // Node immediate fits as 16-bit zero extended on target immediate.
102 // The LO16 param means that only the lower 16 bits of the node
103 // immediate are caught.
105 def immZExt16 : PatLeaf<(imm), [{
106 if (N->getValueType(0) == MVT::i32)
107 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
109 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
112 // shamt field must fit in 5 bits.
113 def immZExt5 : PatLeaf<(imm), [{
114 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
117 // Mips Address Mode! SDNode frameindex could possibily be a match
118 // since load and store instructions from stack used it.
119 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
121 //===----------------------------------------------------------------------===//
122 // Instructions specific format
123 //===----------------------------------------------------------------------===//
125 // Arithmetic 3 register operands
126 let isCommutable = 1 in
127 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
128 InstrItinClass itin>:
129 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
130 !strconcat(instr_asm, "\t$dst, $b, $c"),
131 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
133 let isCommutable = 1 in
134 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
135 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
136 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
138 // Arithmetic 2 register operands
139 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
140 Operand Od, PatLeaf imm_type> :
141 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
142 !strconcat(instr_asm, "\t$dst, $b, $c"),
143 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
145 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
146 Operand Od, PatLeaf imm_type> :
147 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
148 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
150 // Arithmetic Multiply ADD/SUB
152 class MArithR<bits<6> func, string instr_asm> :
153 FR<0x1c, func, (outs CPURegs:$rs), (ins CPURegs:$rt),
154 !strconcat(instr_asm, "\t$rs, $rt"), [], IIImul>;
157 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
158 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
159 !strconcat(instr_asm, "\t$dst, $b, $c"),
160 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
162 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
163 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
164 !strconcat(instr_asm, "\t$dst, $b, $c"),
165 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
167 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
168 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
169 !strconcat(instr_asm, "\t$dst, $b, $c"),
170 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
174 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
175 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
176 !strconcat(instr_asm, "\t$dst, $b, $c"),
177 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
179 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
180 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
181 !strconcat(instr_asm, "\t$dst, $b, $c"),
182 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
184 // Load Upper Imediate
185 class LoadUpper<bits<6> op, string instr_asm>:
189 !strconcat(instr_asm, "\t$dst, $imm"),
193 let canFoldAsLoad = 1, hasDelaySlot = 1 in
194 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
195 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
196 !strconcat(instr_asm, "\t$dst, $addr"),
197 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
199 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
200 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
201 !strconcat(instr_asm, "\t$dst, $addr"),
202 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
204 // Conditional Branch
205 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
206 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
207 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
208 !strconcat(instr_asm, "\t$a, $b, $offset"),
209 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
212 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
213 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
214 !strconcat(instr_asm, "\t$src, $offset"),
215 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
220 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
222 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
223 !strconcat(instr_asm, "\t$dst, $b, $c"),
224 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
227 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
228 Operand Od, PatLeaf imm_type>:
229 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
230 !strconcat(instr_asm, "\t$dst, $b, $c"),
231 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
234 // Unconditional branch
235 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
236 class JumpFJ<bits<6> op, string instr_asm>:
237 FJ<op, (outs), (ins brtarget:$target),
238 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
240 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
241 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
242 FR<op, func, (outs), (ins CPURegs:$target),
243 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
245 // Jump and Link (Call)
246 let isCall=1, hasDelaySlot=1,
247 // All calls clobber the non-callee saved registers...
248 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
249 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
250 class JumpLink<bits<6> op, string instr_asm>:
251 FJ<op, (outs), (ins calltarget:$target, variable_ops),
252 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
256 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
257 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
258 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
260 class BranchLink<string instr_asm>:
261 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
262 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
266 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
267 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
268 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
271 class MoveFromLOHI<bits<6> func, string instr_asm>:
272 FR<0x00, func, (outs CPURegs:$dst), (ins),
273 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
275 class MoveToLOHI<bits<6> func, string instr_asm>:
276 FR<0x00, func, (outs), (ins CPURegs:$src),
277 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
279 class EffectiveAddress<string instr_asm> :
280 FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
281 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
283 // Count Leading Ones/Zeros in Word
284 class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
285 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
286 !strconcat(instr_asm, "\t$dst, $src"),
287 [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
289 // Sign Extend in Register.
290 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
291 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
292 !strconcat(instr_asm, "\t$dst, $src"),
293 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
296 class ByteSwap<bits<6> func, string instr_asm>:
297 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
298 !strconcat(instr_asm, "\t$dst, $src"),
299 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
302 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
303 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
304 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
305 [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
306 CPURegs:$cond, MovCode))], NoItinerary>;
308 //===----------------------------------------------------------------------===//
309 // Pseudo instructions
310 //===----------------------------------------------------------------------===//
312 // As stack alignment is always done with addiu, we need a 16-bit immediate
313 let Defs = [SP], Uses = [SP] in {
314 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
315 "!ADJCALLSTACKDOWN $amt",
316 [(callseq_start timm:$amt)]>;
317 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
318 "!ADJCALLSTACKUP $amt1",
319 [(callseq_end timm:$amt1, timm:$amt2)]>;
322 // Some assembly macros need to avoid pseudoinstructions and assembler
323 // automatic reodering, we should reorder ourselves.
324 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
325 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
326 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
327 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
329 // When handling PIC code the assembler needs .cpload and .cprestore
330 // directives. If the real instructions corresponding these directives
331 // are used, we have the same behavior, but get also a bunch of warnings
332 // from the assembler.
333 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
334 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
336 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
337 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
338 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
339 // replace it for real supported nodes into EmitInstrWithCustomInserter
340 let usesCustomInserter = 1 in {
341 class PseudoSelCC<RegisterClass RC, string asmstr>:
342 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
343 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
346 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
348 //===----------------------------------------------------------------------===//
349 // Instruction definition
350 //===----------------------------------------------------------------------===//
352 //===----------------------------------------------------------------------===//
353 // MipsI Instructions
354 //===----------------------------------------------------------------------===//
356 /// Arithmetic Instructions (ALU Immediate)
357 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
358 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
359 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
360 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
361 def ANDi : LogicI<0x0c, "andi", and>;
362 def ORi : LogicI<0x0d, "ori", or>;
363 def XORi : LogicI<0x0e, "xori", xor>;
364 def LUi : LoadUpper<0x0f, "lui">;
366 /// Arithmetic Instructions (3-Operand, R-Type)
367 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
368 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
369 def ADD : ArithOverflowR<0x00, 0x20, "add">;
370 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
371 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
372 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
373 def AND : LogicR<0x24, "and", and>;
374 def OR : LogicR<0x25, "or", or>;
375 def XOR : LogicR<0x26, "xor", xor>;
376 def NOR : LogicNOR<0x00, 0x27, "nor">;
378 /// Shift Instructions
379 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
380 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
381 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
382 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
383 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
384 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
386 /// Load and Store Instructions
387 def LB : LoadM<0x20, "lb", sextloadi8>;
388 def LBu : LoadM<0x24, "lbu", zextloadi8>;
389 def LH : LoadM<0x21, "lh", sextloadi16>;
390 def LHu : LoadM<0x25, "lhu", zextloadi16>;
391 def LW : LoadM<0x23, "lw", load>;
392 def SB : StoreM<0x28, "sb", truncstorei8>;
393 def SH : StoreM<0x29, "sh", truncstorei16>;
394 def SW : StoreM<0x2b, "sw", store>;
396 /// Jump and Branch Instructions
397 def J : JumpFJ<0x02, "j">;
398 def JR : JumpFR<0x00, 0x08, "jr">;
399 def JAL : JumpLink<0x03, "jal">;
400 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
401 def BEQ : CBranch<0x04, "beq", seteq>;
402 def BNE : CBranch<0x05, "bne", setne>;
405 def BGEZ : CBranchZero<0x01, "bgez", setge>;
408 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
409 def BLEZ : CBranchZero<0x07, "blez", setle>;
410 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
413 def BGEZAL : BranchLink<"bgezal">;
414 def BLTZAL : BranchLink<"bltzal">;
416 let isReturn=1, isTerminator=1, hasDelaySlot=1,
417 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
418 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
419 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
421 /// Multiply and Divide Instructions.
422 let Defs = [HI, LO] in {
423 def MULT : MulDiv<0x18, "mult", IIImul>;
424 def MULTu : MulDiv<0x19, "multu", IIImul>;
425 def DIV : MulDiv<0x1a, "div", IIIdiv>;
426 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
430 def MTHI : MoveToLOHI<0x11, "mthi">;
432 def MTLO : MoveToLOHI<0x13, "mtlo">;
435 def MFHI : MoveFromLOHI<0x10, "mfhi">;
437 def MFLO : MoveFromLOHI<0x12, "mflo">;
439 /// Sign Ext In Register Instructions.
440 let Predicates = [HasSEInReg] in {
441 let shamt = 0x10, rs = 0 in
442 def SEB : SignExtInReg<0x21, "seb", i8>;
444 let shamt = 0x18, rs = 0 in
445 def SEH : SignExtInReg<0x20, "seh", i16>;
449 let Predicates = [HasBitCount] in {
451 def CLZ : CountLeading<0b010110, "clz", ctlz>;
455 let Predicates = [HasSwap] in {
456 let shamt = 0x3, rs = 0 in
457 def WSBW : ByteSwap<0x20, "wsbw">;
461 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
462 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
464 let Predicates = [HasCondMov], Constraints = "$F = $dst" in {
465 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
466 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
471 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
473 // FrameIndexes are legalized when they are operands from load/store
474 // instructions. The same not happens for stack address copies, so an
475 // add op with mem ComplexPattern is used and the stack address copy
476 // can be matched. It's similar to Sparc LEA_ADDRi
477 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
479 // MADD*/MSUB* are not part of MipsI either.
480 //def MADD : MArithR<0x00, "madd">;
481 //def MADDU : MArithR<0x01, "maddu">;
482 //def MSUB : MArithR<0x04, "msub">;
483 //def MSUBU : MArithR<0x05, "msubu">;
485 // MUL is a assembly macro in the current used ISAs. In recent ISA's
486 // it is a real instruction.
487 //def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
489 //===----------------------------------------------------------------------===//
490 // Arbitrary patterns that map to one or more instructions
491 //===----------------------------------------------------------------------===//
494 def : Pat<(i32 immSExt16:$in),
495 (ADDiu ZERO, imm:$in)>;
496 def : Pat<(i32 immZExt16:$in),
497 (ORi ZERO, imm:$in)>;
499 // Arbitrary immediates
500 def : Pat<(i32 imm:$imm),
501 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
504 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
505 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
506 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
507 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
508 def : Pat<(addc CPURegs:$src, imm:$imm),
509 (ADDiu CPURegs:$src, imm:$imm)>;
512 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
513 (JAL tglobaladdr:$dst)>;
514 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
515 (JAL texternalsym:$dst)>;
516 //def : Pat<(MipsJmpLink CPURegs:$dst),
517 // (JALR CPURegs:$dst)>;
520 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
521 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
522 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
524 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
525 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
526 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
528 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
529 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
530 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
533 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
534 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
535 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
536 (ADDiu CPURegs:$gp, tconstpool:$in)>;
538 // Mips does not have "not", so we expand our way
539 def : Pat<(not CPURegs:$in),
540 (NOR CPURegs:$in, ZERO)>;
542 // extended load and stores
543 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
544 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
545 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
548 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
551 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
552 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
553 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
554 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
556 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
557 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
558 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
559 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
560 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
561 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
562 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
563 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
565 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
566 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
567 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
568 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
570 def : Pat<(brcond CPURegs:$cond, bb:$dst),
571 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
574 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
575 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
576 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
577 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
578 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
579 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
580 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
581 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
583 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
584 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
585 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
586 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
588 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
589 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
590 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
591 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
593 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
594 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
597 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
598 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
599 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
600 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
602 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
603 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
604 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
605 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
607 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
608 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
609 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
610 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
612 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
613 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
614 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
615 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
617 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
618 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
619 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
620 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
622 //===----------------------------------------------------------------------===//
623 // Floating Point Support
624 //===----------------------------------------------------------------------===//
626 include "MipsInstrFPU.td"