1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are used to handle global addresses. Used on
26 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
27 // static model. (nothing to do with Mips Registers Hi and Lo)
28 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
29 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
32 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
33 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
36 // These are target-independent nodes, but have target-specific formats.
37 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
38 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
41 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
42 [SDNPHasChain, SDNPOutFlag]>;
43 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
46 //===----------------------------------------------------------------------===//
47 // Mips Instruction Predicate Definitions.
48 //===----------------------------------------------------------------------===//
49 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
51 //===----------------------------------------------------------------------===//
52 // Mips Operand, Complex Patterns and Transformations Definitions.
53 //===----------------------------------------------------------------------===//
55 // Instruction operand types
56 def brtarget : Operand<OtherVT>;
57 def calltarget : Operand<i32>;
58 def uimm16 : Operand<i32>;
59 def simm16 : Operand<i32>;
60 def shamt : Operand<i32>;
61 def addrlabel : Operand<i32>;
64 def mem : Operand<i32> {
65 let PrintMethod = "printMemOperand";
66 let MIOperandInfo = (ops simm16, CPURegs);
69 // Transformation Function - get the lower 16 bits.
70 def LO16 : SDNodeXForm<imm, [{
71 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
74 // Transformation Function - get the higher 16 bits.
75 def HI16 : SDNodeXForm<imm, [{
76 return getI32Imm((unsigned)N->getValue() >> 16);
79 // Node immediate fits as 16-bit sign extended on target immediate.
81 def immSExt16 : PatLeaf<(imm), [{
82 if (N->getValueType(0) == MVT::i32)
83 return (int32_t)N->getValue() == (short)N->getValue();
85 return (int64_t)N->getValue() == (short)N->getValue();
88 // Node immediate fits as 16-bit zero extended on target immediate.
89 // The LO16 param means that only the lower 16 bits of the node
90 // immediate are caught.
92 def immZExt16 : PatLeaf<(imm), [{
93 if (N->getValueType(0) == MVT::i32)
94 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
96 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
99 // Node immediate fits as 32-bit zero extended on target immediate.
100 //def immZExt32 : PatLeaf<(imm), [{
101 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
104 // shamt field must fit in 5 bits.
105 def immZExt5 : PatLeaf<(imm), [{
106 return N->getValue() == ((N->getValue()) & 0x1f) ;
109 // Mips Address Mode! SDNode frameindex could possibily be a match
110 // since load and store instructions from stack used it.
111 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
113 //===----------------------------------------------------------------------===//
114 // Instructions specific format
115 //===----------------------------------------------------------------------===//
117 // Arithmetic 3 register operands
118 let isCommutable = 1 in
119 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
120 InstrItinClass itin>:
124 (ins CPURegs:$b, CPURegs:$c),
125 !strconcat(instr_asm, " $dst, $b, $c"),
126 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
128 let isCommutable = 1 in
129 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
133 (ins CPURegs:$b, CPURegs:$c),
134 !strconcat(instr_asm, " $dst, $b, $c"),
137 // Arithmetic 2 register operands
138 let isCommutable = 1 in
139 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
140 Operand Od, PatLeaf imm_type> :
143 (ins CPURegs:$b, Od:$c),
144 !strconcat(instr_asm, " $dst, $b, $c"),
145 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
147 // Arithmetic Multiply ADD/SUB
149 class MArithR<bits<6> func, string instr_asm> :
154 !strconcat(instr_asm, " $rs, $rt"),
158 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
162 (ins CPURegs:$b, CPURegs:$c),
163 !strconcat(instr_asm, " $dst, $b, $c"),
164 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
166 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
169 (ins CPURegs:$b, uimm16:$c),
170 !strconcat(instr_asm, " $dst, $b, $c"),
171 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
173 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
177 (ins CPURegs:$b, CPURegs:$c),
178 !strconcat(instr_asm, " $dst, $b, $c"),
179 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
183 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
187 (ins CPURegs:$b, shamt:$c),
188 !strconcat(instr_asm, " $dst, $b, $c"),
189 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
191 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
195 (ins CPURegs:$b, CPURegs:$c),
196 !strconcat(instr_asm, " $dst, $b, $c"),
197 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
199 // Load Upper Imediate
200 class LoadUpper<bits<6> op, string instr_asm>:
204 !strconcat(instr_asm, " $dst, $imm"),
208 let isLoad = 1, hasDelaySlot = 1 in
209 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
213 !strconcat(instr_asm, " $dst, $addr"),
214 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
217 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
220 (ins CPURegs:$dst, mem:$addr),
221 !strconcat(instr_asm, " $dst, $addr"),
222 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
224 // Conditional Branch
225 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
226 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
229 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
230 !strconcat(instr_asm, " $a, $b, $offset"),
231 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
235 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
238 (ins CPURegs:$src, brtarget:$offset),
239 !strconcat(instr_asm, " $src, $offset"),
240 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
245 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
250 (ins CPURegs:$b, CPURegs:$c),
251 !strconcat(instr_asm, " $dst, $b, $c"),
252 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
255 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
256 Operand Od, PatLeaf imm_type>:
259 (ins CPURegs:$b, Od:$c),
260 !strconcat(instr_asm, " $dst, $b, $c"),
261 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
264 // Unconditional branch
265 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
266 class JumpFJ<bits<6> op, string instr_asm>:
269 (ins brtarget:$target),
270 !strconcat(instr_asm, " $target"),
271 [(br bb:$target)], IIBranch>;
273 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
274 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
278 (ins CPURegs:$target),
279 !strconcat(instr_asm, " $target"),
280 [(brind CPURegs:$target)], IIBranch>;
282 // Jump and Link (Call)
283 let isCall=1, hasDelaySlot=1,
284 // All calls clobber the non-callee saved registers...
285 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
286 T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in {
287 class JumpLink<bits<6> op, string instr_asm>:
290 (ins calltarget:$target),
291 !strconcat(instr_asm, " $target"),
292 [(MipsJmpLink imm:$target)], IIBranch>;
295 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
300 !strconcat(instr_asm, " $rs"),
301 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
303 class BranchLink<string instr_asm>:
306 (ins CPURegs:$rs, brtarget:$target),
307 !strconcat(instr_asm, " $rs, $target"),
312 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
316 (ins CPURegs:$a, CPURegs:$b),
317 !strconcat(instr_asm, " $a, $b"),
321 class MoveFromTo<bits<6> func, string instr_asm>:
326 !strconcat(instr_asm, " $dst"),
329 // Count Leading Ones/Zeros in Word
330 class CountLeading<bits<6> func, string instr_asm>:
335 !strconcat(instr_asm, " $dst, $src"),
338 class EffectiveAddress<string instr_asm> :
343 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
345 //===----------------------------------------------------------------------===//
346 // Pseudo instructions
347 //===----------------------------------------------------------------------===//
349 // As stack alignment is always done with addiu, we need a 16-bit immediate
350 let Defs = [SP], Uses = [SP] in {
351 def ADJCALLSTACKDOWN : PseudoInstMips<(outs), (ins uimm16:$amt),
352 "!ADJCALLSTACKDOWN $amt",
353 [(callseq_start imm:$amt)]>;
354 def ADJCALLSTACKUP : PseudoInstMips<(outs), (ins uimm16:$amt1, uimm16:$amt2),
355 "!ADJCALLSTACKUP $amt1",
356 [(callseq_end imm:$amt1, imm:$amt2)]>;
359 let isImplicitDef = 1 in
360 def IMPLICIT_DEF_CPURegs : PseudoInstMips<(outs CPURegs:$dst), (ins),
361 "!IMPLICIT_DEF $dst",
362 [(set CPURegs:$dst, (undef))]>;
364 // When handling PIC code the assembler needs .cpload and .cprestore
365 // directives. If the real instructions corresponding these directives
366 // are used, we have the same behavior, but get also a bunch of warnings
367 // from the assembler.
368 def CPLOAD: PseudoInstMips<(outs), (ins CPURegs:$reg),
369 ".set noreorder\n\t.cpload $reg\n\t.set reorder\n", []>;
370 def CPRESTORE: PseudoInstMips<(outs), (ins uimm16:$loc),
371 ".cprestore $loc\n", []>;
373 //===----------------------------------------------------------------------===//
374 // Instruction definition
375 //===----------------------------------------------------------------------===//
377 //===----------------------------------------------------------------------===//
378 // MipsI Instructions
379 //===----------------------------------------------------------------------===//
383 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
384 // immZExt32 is used here so it can match GlobalAddress immediates.
385 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
386 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
387 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
388 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
389 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
390 def ADD : ArithOverflowR<0x00, 0x20, "add">;
391 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
394 def AND : LogicR<0x24, "and", and>;
395 def OR : LogicR<0x25, "or", or>;
396 def XOR : LogicR<0x26, "xor", xor>;
397 def ANDi : LogicI<0x0c, "andi", and>;
398 def ORi : LogicI<0x0d, "ori", or>;
399 def XORi : LogicI<0x0e, "xori", xor>;
400 def NOR : LogicNOR<0x00, 0x27, "nor">;
403 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
404 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
405 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
406 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
407 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
408 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
410 // Load Upper Immediate
411 def LUi : LoadUpper<0x0f, "lui">;
414 def LB : LoadM<0x20, "lb", sextloadi8>;
415 def LBu : LoadM<0x24, "lbu", zextloadi8>;
416 def LH : LoadM<0x21, "lh", sextloadi16>;
417 def LHu : LoadM<0x25, "lhu", zextloadi16>;
418 def LW : LoadM<0x23, "lw", load>;
419 def SB : StoreM<0x28, "sb", truncstorei8>;
420 def SH : StoreM<0x29, "sh", truncstorei16>;
421 def SW : StoreM<0x2b, "sw", store>;
423 // Conditional Branch
424 def BEQ : CBranch<0x04, "beq", seteq>;
425 def BNE : CBranch<0x05, "bne", setne>;
428 def BGEZ : CBranchZero<0x01, "bgez", setge>;
431 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
432 def BLEZ : CBranchZero<0x07, "blez", setle>;
433 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
436 // Set Condition Code
437 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
438 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
439 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
440 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
442 // Unconditional jump
443 def J : JumpFJ<0x02, "j">;
444 def JR : JumpFR<0x00, 0x08, "jr">;
446 // Jump and Link (Call)
447 def JAL : JumpLink<0x03, "jal">;
448 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
449 def BGEZAL : BranchLink<"bgezal">;
450 def BLTZAL : BranchLink<"bltzal">;
452 // MulDiv and Move From Hi/Lo operations, have
453 // their correpondent SDNodes created on ISelDAG.
454 // Special Mul, Div operations
455 def MULT : MulDiv<0x18, "mult", IIImul>;
456 def MULTu : MulDiv<0x19, "multu", IIImul>;
457 def DIV : MulDiv<0x1a, "div", IIIdiv>;
458 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
461 def MFHI : MoveFromTo<0x10, "mfhi">;
462 def MFLO : MoveFromTo<0x12, "mflo">;
463 def MTHI : MoveFromTo<0x11, "mthi">;
464 def MTLO : MoveFromTo<0x13, "mtlo">;
467 // CLO/CLZ are part of the newer MIPS32(tm) instruction
468 // set and not older Mips I keep this for future use
470 //def CLO : CountLeading<0x21, "clo">;
471 //def CLZ : CountLeading<0x20, "clz">;
473 // MADD*/MSUB* are not part of MipsI either.
474 //def MADD : MArithR<0x00, "madd">;
475 //def MADDU : MArithR<0x01, "maddu">;
476 //def MSUB : MArithR<0x04, "msub">;
477 //def MSUBU : MArithR<0x05, "msubu">;
481 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
483 // Ret instruction - as mips does not have "ret" a
484 // jr $ra must be generated.
485 let isReturn=1, isTerminator=1, hasDelaySlot=1,
486 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
488 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
489 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
492 // FrameIndexes are legalized when they are operands from load/store
493 // instructions. The same not happens for stack address copies, so an
494 // add op with mem ComplexPattern is used and the stack address copy
495 // can be matched. It's similar to Sparc LEA_ADDRi
496 def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
498 //===----------------------------------------------------------------------===//
499 // Arbitrary patterns that map to one or more instructions
500 //===----------------------------------------------------------------------===//
503 def : Pat<(i32 immSExt16:$in),
504 (ADDiu ZERO, imm:$in)>;
505 def : Pat<(i32 immZExt16:$in),
506 (ORi ZERO, imm:$in)>;
508 // Arbitrary immediates
509 def : Pat<(i32 imm:$imm),
510 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
513 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
514 (JAL tglobaladdr:$dst)>;
515 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
516 (JAL texternalsym:$dst)>;
517 def : Pat<(MipsJmpLink CPURegs:$dst),
518 (JALR CPURegs:$dst)>;
520 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
521 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
522 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
523 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
524 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
525 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
526 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
527 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
528 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
530 // Mips does not have not, so we increase the operation
531 def : Pat<(not CPURegs:$in),
532 (NOR CPURegs:$in, ZERO)>;
534 // extended load and stores
535 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
536 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
537 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
538 def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
539 (SB CPURegs:$src, addr:$addr)>;
542 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
548 // direct match equal/notequal zero branches
549 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
550 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
551 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
552 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
554 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
555 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
556 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
557 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
559 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
560 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
561 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
562 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
564 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
565 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
566 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
567 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
569 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
570 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
571 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
572 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
573 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
574 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
575 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
576 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
578 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
579 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
580 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
581 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
583 // generic brcond pattern
584 def : Pat<(brcond CPURegs:$cond, bb:$dst),
585 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
588 /// setcc patterns, only matched when there
589 /// is no brcond following a setcc operation
592 // setcc 2 register operands
593 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
594 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
595 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
596 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
598 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
599 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
600 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
601 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
603 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
604 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
605 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
606 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
608 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
609 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
610 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
612 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
613 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
614 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
616 // setcc reg/imm operands
617 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
618 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
619 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
620 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;