1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32 but were removed in
251 // MIPS32r6 and MIPS64r6.
252 class INSN_MIPS3_32_NOT_32R6_64R6 {
253 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
256 // The portions of MIPS-III that were also added to MIPS32
257 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
259 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS4_32_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
271 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
272 // MIPS32r6 and MIPS64r6.
273 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
274 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
277 //===----------------------------------------------------------------------===//
279 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
280 let EncodingPredicates = [HasStdEnc];
283 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
284 InstAlias<Asm, Result, Emit>, PredicateControl;
287 bit isCommutable = 1;
304 bit isTerminator = 1;
307 bit hasExtraSrcRegAllocReq = 1;
308 bit isCodeGenOnly = 1;
311 class IsAsCheapAsAMove {
312 bit isAsCheapAsAMove = 1;
315 class NeverHasSideEffects {
316 bit neverHasSideEffects = 1;
319 //===----------------------------------------------------------------------===//
320 // Instruction format superclass
321 //===----------------------------------------------------------------------===//
323 include "MipsInstrFormats.td"
325 //===----------------------------------------------------------------------===//
326 // Mips Operand, Complex Patterns and Transformations Definitions.
327 //===----------------------------------------------------------------------===//
329 def MipsJumpTargetAsmOperand : AsmOperandClass {
330 let Name = "JumpTarget";
331 let ParserMethod = "ParseJumpTarget";
332 let PredicateMethod = "isImm";
333 let RenderMethod = "addImmOperands";
336 // Instruction operand types
337 def jmptarget : Operand<OtherVT> {
338 let EncoderMethod = "getJumpTargetOpValue";
339 let ParserMatchClass = MipsJumpTargetAsmOperand;
341 def brtarget : Operand<OtherVT> {
342 let EncoderMethod = "getBranchTargetOpValue";
343 let OperandType = "OPERAND_PCREL";
344 let DecoderMethod = "DecodeBranchTarget";
345 let ParserMatchClass = MipsJumpTargetAsmOperand;
347 def calltarget : Operand<iPTR> {
348 let EncoderMethod = "getJumpTargetOpValue";
349 let ParserMatchClass = MipsJumpTargetAsmOperand;
352 def simm9 : Operand<i32>;
353 def simm10 : Operand<i32>;
354 def simm11 : Operand<i32>;
356 def simm16 : Operand<i32> {
357 let DecoderMethod= "DecodeSimm16";
360 def simm19_lsl2 : Operand<i32> {
361 let EncoderMethod = "getSimm19Lsl2Encoding";
362 let DecoderMethod = "DecodeSimm19Lsl2";
363 let ParserMatchClass = MipsJumpTargetAsmOperand;
366 def simm18_lsl3 : Operand<i32> {
367 let EncoderMethod = "getSimm18Lsl3Encoding";
368 let DecoderMethod = "DecodeSimm18Lsl3";
369 let ParserMatchClass = MipsJumpTargetAsmOperand;
372 def simm20 : Operand<i32> {
375 def uimm20 : Operand<i32> {
378 def uimm10 : Operand<i32> {
381 def simm16_64 : Operand<i64> {
382 let DecoderMethod = "DecodeSimm16";
386 def uimmz : Operand<i32> {
387 let PrintMethod = "printUnsignedImm";
391 def uimm2 : Operand<i32> {
392 let PrintMethod = "printUnsignedImm";
395 def uimm3 : Operand<i32> {
396 let PrintMethod = "printUnsignedImm";
399 def uimm5 : Operand<i32> {
400 let PrintMethod = "printUnsignedImm";
403 def uimm6 : Operand<i32> {
404 let PrintMethod = "printUnsignedImm";
407 def uimm16 : Operand<i32> {
408 let PrintMethod = "printUnsignedImm";
411 def pcrel16 : Operand<i32> {
414 def MipsMemAsmOperand : AsmOperandClass {
416 let ParserMethod = "parseMemOperand";
419 def MipsMemSimm11AsmOperand : AsmOperandClass {
420 let Name = "MemOffsetSimm11";
421 let SuperClasses = [MipsMemAsmOperand];
422 let RenderMethod = "addMemOperands";
423 let ParserMethod = "parseMemOperand";
424 let PredicateMethod = "isMemWithSimmOffset<11>";
425 //let DiagnosticType = "Simm11";
428 def MipsInvertedImmoperand : AsmOperandClass {
430 let RenderMethod = "addImmOperands";
431 let ParserMethod = "parseInvNum";
434 def InvertedImOperand : Operand<i32> {
435 let ParserMatchClass = MipsInvertedImmoperand;
438 def InvertedImOperand64 : Operand<i64> {
439 let ParserMatchClass = MipsInvertedImmoperand;
442 class mem_generic : Operand<iPTR> {
443 let PrintMethod = "printMemOperand";
444 let MIOperandInfo = (ops ptr_rc, simm16);
445 let EncoderMethod = "getMemEncoding";
446 let ParserMatchClass = MipsMemAsmOperand;
447 let OperandType = "OPERAND_MEMORY";
451 def mem : mem_generic;
453 // MSA specific address operand
454 def mem_msa : mem_generic {
455 let MIOperandInfo = (ops ptr_rc, simm10);
456 let EncoderMethod = "getMSAMemEncoding";
459 def mem_simm9 : mem_generic {
460 let MIOperandInfo = (ops ptr_rc, simm9);
461 let EncoderMethod = "getMemEncoding";
464 def mem_simm11 : mem_generic {
465 let MIOperandInfo = (ops ptr_rc, simm11);
466 let EncoderMethod = "getMemEncoding";
467 let ParserMatchClass = MipsMemSimm11AsmOperand;
470 def mem_ea : Operand<iPTR> {
471 let PrintMethod = "printMemOperandEA";
472 let MIOperandInfo = (ops ptr_rc, simm16);
473 let EncoderMethod = "getMemEncoding";
474 let OperandType = "OPERAND_MEMORY";
477 def PtrRC : Operand<iPTR> {
478 let MIOperandInfo = (ops ptr_rc);
479 let DecoderMethod = "DecodePtrRegisterClass";
480 let ParserMatchClass = GPR32AsmOperand;
483 // size operand of ext instruction
484 def size_ext : Operand<i32> {
485 let EncoderMethod = "getSizeExtEncoding";
486 let DecoderMethod = "DecodeExtSize";
489 // size operand of ins instruction
490 def size_ins : Operand<i32> {
491 let EncoderMethod = "getSizeInsEncoding";
492 let DecoderMethod = "DecodeInsSize";
495 // Transformation Function - get the lower 16 bits.
496 def LO16 : SDNodeXForm<imm, [{
497 return getImm(N, N->getZExtValue() & 0xFFFF);
500 // Transformation Function - get the higher 16 bits.
501 def HI16 : SDNodeXForm<imm, [{
502 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
506 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
508 // Node immediate is zero (e.g. insve.d)
509 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
511 // Node immediate fits as 16-bit sign extended on target immediate.
513 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
515 // Node immediate fits as 16-bit sign extended on target immediate.
517 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
519 // Node immediate fits as 15-bit sign extended on target immediate.
521 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
523 // Node immediate fits as 16-bit zero extended on target immediate.
524 // The LO16 param means that only the lower 16 bits of the node
525 // immediate are caught.
527 def immZExt16 : PatLeaf<(imm), [{
528 if (N->getValueType(0) == MVT::i32)
529 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
531 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
534 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
535 def immLow16Zero : PatLeaf<(imm), [{
536 int64_t Val = N->getSExtValue();
537 return isInt<32>(Val) && !(Val & 0xffff);
540 // shamt field must fit in 5 bits.
541 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
543 // True if (N + 1) fits in 16-bit field.
544 def immSExt16Plus1 : PatLeaf<(imm), [{
545 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
548 // Mips Address Mode! SDNode frameindex could possibily be a match
549 // since load and store instructions from stack used it.
551 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
554 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
557 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
560 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
562 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
564 //===----------------------------------------------------------------------===//
565 // Instructions specific format
566 //===----------------------------------------------------------------------===//
568 // Arithmetic and logical instructions with 3 register operands.
569 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
570 InstrItinClass Itin = NoItinerary,
571 SDPatternOperator OpNode = null_frag>:
572 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
573 !strconcat(opstr, "\t$rd, $rs, $rt"),
574 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
575 let isCommutable = isComm;
576 let isReMaterializable = 1;
577 let TwoOperandAliasConstraint = "$rd = $rs";
580 // Arithmetic and logical instructions with 2 register operands.
581 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
582 InstrItinClass Itin = NoItinerary,
583 SDPatternOperator imm_type = null_frag,
584 SDPatternOperator OpNode = null_frag> :
585 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
586 !strconcat(opstr, "\t$rt, $rs, $imm16"),
587 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
589 let isReMaterializable = 1;
590 let TwoOperandAliasConstraint = "$rs = $rt";
593 // Arithmetic Multiply ADD/SUB
594 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
595 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
596 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
597 let Defs = [HI0, LO0];
598 let Uses = [HI0, LO0];
599 let isCommutable = isComm;
603 class LogicNOR<string opstr, RegisterOperand RO>:
604 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
605 !strconcat(opstr, "\t$rd, $rs, $rt"),
606 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
607 let isCommutable = 1;
611 class shift_rotate_imm<string opstr, Operand ImmOpnd,
612 RegisterOperand RO, InstrItinClass itin,
613 SDPatternOperator OpNode = null_frag,
614 SDPatternOperator PF = null_frag> :
615 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
616 !strconcat(opstr, "\t$rd, $rt, $shamt"),
617 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
618 let TwoOperandAliasConstraint = "$rt = $rd";
621 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
622 SDPatternOperator OpNode = null_frag>:
623 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
624 !strconcat(opstr, "\t$rd, $rt, $rs"),
625 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
628 // Load Upper Imediate
629 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
630 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
631 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
632 let neverHasSideEffects = 1;
633 let isReMaterializable = 1;
637 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
638 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
639 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
640 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
641 let DecoderMethod = "DecodeMem";
642 let canFoldAsLoad = 1;
646 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
647 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
648 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
649 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
650 let DecoderMethod = "DecodeMem";
654 // Load/Store Left/Right
655 let canFoldAsLoad = 1 in
656 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
657 InstrItinClass Itin> :
658 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
659 !strconcat(opstr, "\t$rt, $addr"),
660 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
661 let DecoderMethod = "DecodeMem";
662 string Constraints = "$src = $rt";
665 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
666 InstrItinClass Itin> :
667 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
668 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
669 let DecoderMethod = "DecodeMem";
672 // Conditional Branch
673 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
674 RegisterOperand RO> :
675 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
676 !strconcat(opstr, "\t$rs, $rt, $offset"),
677 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
680 let isTerminator = 1;
681 let hasDelaySlot = 1;
685 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
686 RegisterOperand RO> :
687 InstSE<(outs), (ins RO:$rs, opnd:$offset),
688 !strconcat(opstr, "\t$rs, $offset"),
689 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
692 let isTerminator = 1;
693 let hasDelaySlot = 1;
698 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
699 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
700 !strconcat(opstr, "\t$rd, $rs, $rt"),
701 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
702 II_SLT_SLTU, FrmR, opstr>;
704 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
706 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
707 !strconcat(opstr, "\t$rt, $rs, $imm16"),
708 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
709 II_SLTI_SLTIU, FrmI, opstr>;
712 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
713 SDPatternOperator targetoperator, string bopstr> :
714 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
715 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
718 let hasDelaySlot = 1;
719 let DecoderMethod = "DecodeJumpTarget";
723 // Unconditional branch
724 class UncondBranch<Instruction BEQInst> :
725 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
726 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
728 let isTerminator = 1;
730 let hasDelaySlot = 1;
731 let AdditionalPredicates = [RelocPIC];
735 // Base class for indirect branch and return instruction classes.
736 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
737 class JumpFR<string opstr, RegisterOperand RO,
738 SDPatternOperator operator = null_frag>:
739 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
743 class IndirectBranch<string opstr, RegisterOperand RO> :
744 JumpFR<opstr, RO, brind> {
746 let isIndirectBranch = 1;
749 // Return instruction
750 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
752 let isCodeGenOnly = 1;
754 let hasExtraSrcRegAllocReq = 1;
757 // Jump and Link (Call)
758 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
759 class JumpLink<string opstr, DAGOperand opnd> :
760 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
761 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
762 let DecoderMethod = "DecodeJumpTarget";
765 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
766 Register RetReg, RegisterOperand ResRO = RO>:
767 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
768 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
770 class JumpLinkReg<string opstr, RegisterOperand RO>:
771 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
774 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
775 InstSE<(outs), (ins RO:$rs, opnd:$offset),
776 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
780 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
781 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
782 class TailCall<Instruction JumpInst> :
783 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
784 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
786 class TailCallReg<RegisterOperand RO, Instruction JRInst,
787 RegisterOperand ResRO = RO> :
788 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
789 PseudoInstExpansion<(JRInst ResRO:$rs)>;
792 class BAL_BR_Pseudo<Instruction RealInst> :
793 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
794 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
796 let isTerminator = 1;
798 let hasDelaySlot = 1;
803 class SYS_FT<string opstr> :
804 InstSE<(outs), (ins uimm20:$code_),
805 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
807 class BRK_FT<string opstr> :
808 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
809 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
813 class ER_FT<string opstr> :
814 InstSE<(outs), (ins),
815 opstr, [], NoItinerary, FrmOther, opstr>;
818 class DEI_FT<string opstr, RegisterOperand RO> :
819 InstSE<(outs RO:$rt), (ins),
820 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
823 class WAIT_FT<string opstr> :
824 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
827 let hasSideEffects = 1 in
828 class SYNC_FT<string opstr> :
829 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
830 NoItinerary, FrmOther, opstr>;
832 let hasSideEffects = 1 in
833 class TEQ_FT<string opstr, RegisterOperand RO> :
834 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
835 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
838 class TEQI_FT<string opstr, RegisterOperand RO> :
839 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
840 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
842 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
843 list<Register> DefRegs> :
844 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
846 let isCommutable = 1;
848 let neverHasSideEffects = 1;
851 // Pseudo multiply/divide instruction with explicit accumulator register
853 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
854 SDPatternOperator OpNode, InstrItinClass Itin,
855 bit IsComm = 1, bit HasSideEffects = 0,
856 bit UsesCustomInserter = 0> :
857 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
858 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
859 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
860 let isCommutable = IsComm;
861 let hasSideEffects = HasSideEffects;
862 let usesCustomInserter = UsesCustomInserter;
865 // Pseudo multiply add/sub instruction with explicit accumulator register
867 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
869 : PseudoSE<(outs ACC64:$ac),
870 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
872 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
874 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
875 string Constraints = "$acin = $ac";
878 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
879 list<Register> DefRegs> :
880 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
881 [], itin, FrmR, opstr> {
886 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
887 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
888 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
890 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
891 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
894 let neverHasSideEffects = 1;
897 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
898 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
899 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
902 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
903 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
906 let neverHasSideEffects = 1;
909 class EffectiveAddress<string opstr, RegisterOperand RO> :
910 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
911 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
912 !strconcat(opstr, "_lea")> {
913 let isCodeGenOnly = 1;
914 let DecoderMethod = "DecodeMem";
917 // Count Leading Ones/Zeros in Word
918 class CountLeading0<string opstr, RegisterOperand RO>:
919 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
920 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
922 class CountLeading1<string opstr, RegisterOperand RO>:
923 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
924 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
926 // Sign Extend in Register.
927 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
928 InstrItinClass itin> :
929 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
930 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
933 class SubwordSwap<string opstr, RegisterOperand RO>:
934 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
935 NoItinerary, FrmR, opstr> {
936 let neverHasSideEffects = 1;
940 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
941 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
945 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
946 SDPatternOperator Op = null_frag>:
947 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
948 !strconcat(opstr, " $rt, $rs, $pos, $size"),
949 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
950 FrmR, opstr>, ISA_MIPS32R2;
952 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
953 SDPatternOperator Op = null_frag>:
954 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
955 !strconcat(opstr, " $rt, $rs, $pos, $size"),
956 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
957 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
958 let Constraints = "$src = $rt";
961 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
962 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
963 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
964 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
966 // Atomic Compare & Swap.
967 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
968 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
969 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
971 class LLBase<string opstr, RegisterOperand RO> :
972 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
973 [], NoItinerary, FrmI> {
974 let DecoderMethod = "DecodeMem";
978 class SCBase<string opstr, RegisterOperand RO> :
979 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
980 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
981 let DecoderMethod = "DecodeMem";
983 let Constraints = "$rt = $dst";
986 class MFC3OP<string asmstr, RegisterOperand RO> :
987 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
988 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
990 class TrapBase<Instruction RealInst>
991 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
992 PseudoInstExpansion<(RealInst 0, 0)> {
994 let isTerminator = 1;
995 let isCodeGenOnly = 1;
998 //===----------------------------------------------------------------------===//
999 // Pseudo instructions
1000 //===----------------------------------------------------------------------===//
1003 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1004 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1006 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1007 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1008 [(callseq_start timm:$amt)]>;
1009 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1010 [(callseq_end timm:$amt1, timm:$amt2)]>;
1013 let usesCustomInserter = 1 in {
1014 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1015 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1016 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1017 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1018 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1019 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1020 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1021 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1022 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1023 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1024 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1025 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1026 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1027 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1028 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1029 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1030 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1031 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1033 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1034 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1035 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1037 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1038 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1039 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1042 /// Pseudo instructions for loading and storing accumulator registers.
1043 let isPseudo = 1, isCodeGenOnly = 1 in {
1044 def LOAD_ACC64 : Load<"", ACC64>;
1045 def STORE_ACC64 : Store<"", ACC64>;
1048 // We need these two pseudo instructions to avoid offset calculation for long
1049 // branches. See the comment in file MipsLongBranch.cpp for detailed
1052 // Expands to: lui $dst, %hi($tgt - $baltgt)
1053 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1054 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1056 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1057 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1058 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1060 //===----------------------------------------------------------------------===//
1061 // Instruction definition
1062 //===----------------------------------------------------------------------===//
1063 //===----------------------------------------------------------------------===//
1064 // MipsI Instructions
1065 //===----------------------------------------------------------------------===//
1067 /// Arithmetic Instructions (ALU Immediate)
1068 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1070 ADDI_FM<0x9>, IsAsCheapAsAMove;
1071 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1072 ISA_MIPS1_NOT_32R6_64R6;
1073 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1075 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1077 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1080 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1083 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1086 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1088 /// Arithmetic Instructions (3-Operand, R-Type)
1089 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1091 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1093 let Defs = [HI0, LO0] in
1094 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1095 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1096 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1097 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1098 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1099 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1100 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1102 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1104 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1106 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1108 /// Shift Instructions
1109 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1110 immZExt5>, SRA_FM<0, 0>;
1111 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1112 immZExt5>, SRA_FM<2, 0>;
1113 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1114 immZExt5>, SRA_FM<3, 0>;
1115 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1117 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1119 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1122 // Rotate Instructions
1123 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1125 SRA_FM<2, 1>, ISA_MIPS32R2;
1126 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1127 SRLV_FM<6, 1>, ISA_MIPS32R2;
1129 /// Load and Store Instructions
1131 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1132 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1134 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1136 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1137 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1139 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1140 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1141 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1143 /// load/store left/right
1144 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1145 AdditionalPredicates = [NotInMicroMips] in {
1146 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1147 ISA_MIPS1_NOT_32R6_64R6;
1148 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1149 ISA_MIPS1_NOT_32R6_64R6;
1150 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1151 ISA_MIPS1_NOT_32R6_64R6;
1152 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1153 ISA_MIPS1_NOT_32R6_64R6;
1156 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1157 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1158 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1159 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1160 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1161 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1162 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1164 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1165 ISA_MIPS2_NOT_32R6_64R6;
1166 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1167 ISA_MIPS2_NOT_32R6_64R6;
1168 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1169 ISA_MIPS2_NOT_32R6_64R6;
1170 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1171 ISA_MIPS2_NOT_32R6_64R6;
1172 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1173 ISA_MIPS2_NOT_32R6_64R6;
1174 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1175 ISA_MIPS2_NOT_32R6_64R6;
1177 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1178 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1179 def TRAP : TrapBase<BREAK>;
1181 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1182 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1184 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1185 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1187 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1188 AdditionalPredicates = [NotInMicroMips] in {
1189 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1191 /// Load-linked, Store-conditional
1192 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1193 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1196 /// Jump and Branch Instructions
1197 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1198 AdditionalRequires<[RelocStatic]>, IsBranch;
1199 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1200 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1201 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1202 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1204 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1206 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1208 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1210 def B : UncondBranch<BEQ>;
1212 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1213 let AdditionalPredicates = [NotInMicroMips] in {
1214 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1215 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1218 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1219 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1220 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1221 ISA_MIPS1_NOT_32R6_64R6;
1222 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1223 ISA_MIPS1_NOT_32R6_64R6;
1224 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1225 def TAILCALL : TailCall<J>;
1226 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1228 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1230 // Exception handling related node and instructions.
1231 // The conversion sequence is:
1232 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1233 // MIPSeh_return -> (stack change + indirect branch)
1235 // MIPSeh_return takes the place of regular return instruction
1236 // but takes two arguments (V1, V0) which are used for storing
1237 // the offset and return address respectively.
1238 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1240 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1241 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1243 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1244 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1245 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1246 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1248 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1251 /// Multiply and Divide Instructions.
1252 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1253 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1254 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1255 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1256 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1257 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1258 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1259 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1261 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1262 ISA_MIPS1_NOT_32R6_64R6;
1263 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1264 ISA_MIPS1_NOT_32R6_64R6;
1265 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1266 AdditionalPredicates = [NotInMicroMips] in {
1267 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1268 ISA_MIPS1_NOT_32R6_64R6;
1269 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1270 ISA_MIPS1_NOT_32R6_64R6;
1273 /// Sign Ext In Register Instructions.
1274 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1275 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1276 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1277 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1280 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1281 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1283 /// Word Swap Bytes Within Halfwords
1284 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1287 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1289 // FrameIndexes are legalized when they are operands from load/store
1290 // instructions. The same not happens for stack address copies, so an
1291 // add op with mem ComplexPattern is used and the stack address copy
1292 // can be matched. It's similar to Sparc LEA_ADDRi
1293 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1296 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1297 ISA_MIPS32_NOT_32R6_64R6;
1298 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1299 ISA_MIPS32_NOT_32R6_64R6;
1300 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1301 ISA_MIPS32_NOT_32R6_64R6;
1302 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1303 ISA_MIPS32_NOT_32R6_64R6;
1305 let AdditionalPredicates = [NotDSP] in {
1306 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1307 ISA_MIPS1_NOT_32R6_64R6;
1308 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1309 ISA_MIPS1_NOT_32R6_64R6;
1310 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1311 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1312 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1313 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1314 ISA_MIPS32_NOT_32R6_64R6;
1315 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1316 ISA_MIPS32_NOT_32R6_64R6;
1317 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1318 ISA_MIPS32_NOT_32R6_64R6;
1319 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1320 ISA_MIPS32_NOT_32R6_64R6;
1323 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1324 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1325 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1326 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1328 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1330 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1331 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1333 /// Move Control Registers From/To CPU Registers
1334 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1335 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1336 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1337 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1339 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1341 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1342 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1343 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1345 // JR_HB and JALR_HB are defined here using the new style naming
1346 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1347 // and because of that it doesn't follow the naming convention of the
1348 // rest of the file. To avoid a mixture of old vs new style, the new
1349 // style was chosen.
1350 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1351 dag OutOperandList = (outs);
1352 dag InOperandList = (ins GPROpnd:$rs);
1353 string AsmString = !strconcat(instr_asm, "\t$rs");
1354 list<dag> Pattern = [];
1357 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1358 dag OutOperandList = (outs GPROpnd:$rd);
1359 dag InOperandList = (ins GPROpnd:$rs);
1360 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1361 list<dag> Pattern = [];
1364 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1365 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1367 let isIndirectBranch=1;
1373 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1374 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1375 let isIndirectBranch=1;
1379 class JR_HB_ENC : JR_HB_FM<8>;
1380 class JALR_HB_ENC : JALR_HB_FM<9>;
1382 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1383 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1385 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1387 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1388 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1389 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1390 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1392 class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
1393 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1394 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
1396 def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
1397 INSN_MIPS3_32_NOT_32R6_64R6;
1398 def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
1399 INSN_MIPS3_32_NOT_32R6_64R6;
1401 //===----------------------------------------------------------------------===//
1402 // Instruction aliases
1403 //===----------------------------------------------------------------------===//
1404 def : MipsInstAlias<"move $dst, $src",
1405 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1407 let AdditionalPredicates = [NotInMicroMips];
1409 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1410 ISA_MIPS1_NOT_32R6_64R6;
1411 def : MipsInstAlias<"addu $rs, $rt, $imm",
1412 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1413 def : MipsInstAlias<"add $rs, $rt, $imm",
1414 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1415 def : MipsInstAlias<"and $rs, $rt, $imm",
1416 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1417 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1418 let Predicates = [NotInMicroMips] in {
1419 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1421 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1422 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1423 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1424 def : MipsInstAlias<"not $rt, $rs",
1425 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1426 def : MipsInstAlias<"neg $rt, $rs",
1427 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1428 def : MipsInstAlias<"negu $rt",
1429 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1430 def : MipsInstAlias<"negu $rt, $rs",
1431 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1432 def : MipsInstAlias<"slt $rs, $rt, $imm",
1433 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1434 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1435 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1436 def : MipsInstAlias<"xor $rs, $rt, $imm",
1437 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1438 def : MipsInstAlias<"or $rs, $rt, $imm",
1439 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1440 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1441 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1442 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1443 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1444 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1445 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1446 def : MipsInstAlias<"bnez $rs,$offset",
1447 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1448 def : MipsInstAlias<"beqz $rs,$offset",
1449 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1450 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1452 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1453 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1454 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1455 def : MipsInstAlias<"di", (DI ZERO), 1>;
1457 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1458 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1459 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1461 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1462 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1464 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1465 def : MipsInstAlias<"sll $rd, $rt, $rs",
1466 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1467 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1468 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1469 InvertedImOperand:$imm), 0>;
1470 def : MipsInstAlias<"sub $rs, $imm",
1471 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1473 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1474 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1475 InvertedImOperand:$imm), 0>;
1476 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1477 InvertedImOperand:$imm), 0>;
1478 def : MipsInstAlias<"sra $rd, $rt, $rs",
1479 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1480 def : MipsInstAlias<"srl $rd, $rt, $rs",
1481 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1482 //===----------------------------------------------------------------------===//
1483 // Assembler Pseudo Instructions
1484 //===----------------------------------------------------------------------===//
1486 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1487 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1488 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1489 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1491 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1492 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1493 !strconcat(instr_asm, "\t$rt, $addr")> ;
1494 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1496 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1497 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1498 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1499 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1501 //===----------------------------------------------------------------------===//
1502 // Arbitrary patterns that map to one or more instructions
1503 //===----------------------------------------------------------------------===//
1505 // Load/store pattern templates.
1506 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1507 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1509 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1510 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1513 def : MipsPat<(i32 immSExt16:$in),
1514 (ADDiu ZERO, imm:$in)>;
1515 def : MipsPat<(i32 immZExt16:$in),
1516 (ORi ZERO, imm:$in)>;
1517 def : MipsPat<(i32 immLow16Zero:$in),
1518 (LUi (HI16 imm:$in))>;
1520 // Arbitrary immediates
1521 def : MipsPat<(i32 imm:$imm),
1522 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1524 // Carry MipsPatterns
1525 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1526 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1527 let AdditionalPredicates = [NotDSP] in {
1528 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1529 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1530 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1531 (ADDiu GPR32:$src, imm:$imm)>;
1535 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1536 (JAL tglobaladdr:$dst)>;
1537 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1538 (JAL texternalsym:$dst)>;
1539 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1540 // (JALR GPR32:$dst)>;
1543 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1544 (TAILCALL tglobaladdr:$dst)>;
1545 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1546 (TAILCALL texternalsym:$dst)>;
1548 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1549 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1550 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1551 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1552 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1553 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1555 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1556 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1557 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1558 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1559 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1560 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1562 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1563 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1564 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1565 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1566 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1567 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1568 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1569 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1570 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1571 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1574 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1575 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1576 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1577 (ADDiu GPR32:$gp, tconstpool:$in)>;
1580 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1581 MipsPat<(MipsWrapper RC:$gp, node:$in),
1582 (ADDiuOp RC:$gp, node:$in)>;
1584 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1585 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1586 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1587 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1588 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1589 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1591 // Mips does not have "not", so we expand our way
1592 def : MipsPat<(not GPR32:$in),
1593 (NOR GPR32Opnd:$in, ZERO)>;
1596 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1597 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1598 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1601 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1604 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1605 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1606 Instruction SLTiuOp, Register ZEROReg> {
1607 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1608 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1609 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1610 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1612 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1613 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1614 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1615 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1616 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1617 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1618 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1619 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1620 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1621 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1622 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1623 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1625 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1626 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1627 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1628 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1630 def : MipsPat<(brcond RC:$cond, bb:$dst),
1631 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1634 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1636 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1637 (BLEZ i32:$lhs, bb:$dst)>;
1638 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1639 (BGEZ i32:$lhs, bb:$dst)>;
1642 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1643 Instruction SLTuOp, Register ZEROReg> {
1644 def : MipsPat<(seteq RC:$lhs, 0),
1645 (SLTiuOp RC:$lhs, 1)>;
1646 def : MipsPat<(setne RC:$lhs, 0),
1647 (SLTuOp ZEROReg, RC:$lhs)>;
1648 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1649 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1650 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1651 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1654 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1655 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1656 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1657 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1658 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1661 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1662 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1663 (SLTOp RC:$rhs, RC:$lhs)>;
1664 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1665 (SLTuOp RC:$rhs, RC:$lhs)>;
1668 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1669 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1670 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1671 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1672 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1675 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1676 Instruction SLTiuOp> {
1677 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1678 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1679 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1680 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1683 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1684 defm : SetlePats<GPR32, SLT, SLTu>;
1685 defm : SetgtPats<GPR32, SLT, SLTu>;
1686 defm : SetgePats<GPR32, SLT, SLTu>;
1687 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1690 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1692 // Load halfword/word patterns.
1693 let AddedComplexity = 40 in {
1694 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1695 def : LoadRegImmPat<LH, i32, sextloadi16>;
1696 def : LoadRegImmPat<LW, i32, load>;
1699 //===----------------------------------------------------------------------===//
1700 // Floating Point Support
1701 //===----------------------------------------------------------------------===//
1703 include "MipsInstrFPU.td"
1704 include "Mips64InstrInfo.td"
1705 include "MipsCondMov.td"
1707 include "Mips32r6InstrInfo.td"
1708 include "Mips64r6InstrInfo.td"
1713 include "Mips16InstrFormats.td"
1714 include "Mips16InstrInfo.td"
1717 include "MipsDSPInstrFormats.td"
1718 include "MipsDSPInstrInfo.td"
1721 include "MipsMSAInstrFormats.td"
1722 include "MipsMSAInstrInfo.td"
1725 include "MicroMipsInstrFormats.td"
1726 include "MicroMipsInstrInfo.td"
1727 include "MicroMipsInstrFPU.td"