1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are used to handle global addresses. Used on
26 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
27 // static model. (nothing to do with Mips Registers Hi and Lo)
28 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
29 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
32 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
33 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
36 // These are target-independent nodes, but have target-specific formats.
37 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
38 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>,
41 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
42 [SDNPHasChain, SDNPOutFlag]>;
43 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
44 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
47 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>,
48 SDTCisSameAs<1, 2>, SDTCisInt<3>]>;
49 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
51 //===----------------------------------------------------------------------===//
52 // Mips Instruction Predicate Definitions.
53 //===----------------------------------------------------------------------===//
54 def IsStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
56 //===----------------------------------------------------------------------===//
57 // Mips Operand, Complex Patterns and Transformations Definitions.
58 //===----------------------------------------------------------------------===//
60 // Instruction operand types
61 def brtarget : Operand<OtherVT>;
62 def calltarget : Operand<i32>;
63 def uimm16 : Operand<i32>;
64 def simm16 : Operand<i32>;
65 def shamt : Operand<i32>;
66 def addrlabel : Operand<i32>;
69 def mem : Operand<i32> {
70 let PrintMethod = "printMemOperand";
71 let MIOperandInfo = (ops simm16, CPURegs);
74 // Transformation Function - get the lower 16 bits.
75 def LO16 : SDNodeXForm<imm, [{
76 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
79 // Transformation Function - get the higher 16 bits.
80 def HI16 : SDNodeXForm<imm, [{
81 return getI32Imm((unsigned)N->getValue() >> 16);
84 // Node immediate fits as 16-bit sign extended on target immediate.
86 def immSExt16 : PatLeaf<(imm), [{
87 if (N->getValueType(0) == MVT::i32)
88 return (int32_t)N->getValue() == (short)N->getValue();
90 return (int64_t)N->getValue() == (short)N->getValue();
93 // Node immediate fits as 16-bit zero extended on target immediate.
94 // The LO16 param means that only the lower 16 bits of the node
95 // immediate are caught.
97 def immZExt16 : PatLeaf<(imm), [{
98 if (N->getValueType(0) == MVT::i32)
99 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
101 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
104 // Node immediate fits as 32-bit zero extended on target immediate.
105 //def immZExt32 : PatLeaf<(imm), [{
106 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
109 // shamt field must fit in 5 bits.
110 def immZExt5 : PatLeaf<(imm), [{
111 return N->getValue() == ((N->getValue()) & 0x1f) ;
114 // Mips Address Mode! SDNode frameindex could possibily be a match
115 // since load and store instructions from stack used it.
116 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
118 //===----------------------------------------------------------------------===//
119 // Instructions specific format
120 //===----------------------------------------------------------------------===//
122 // Arithmetic 3 register operands
123 let isCommutable = 1 in
124 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
125 InstrItinClass itin>:
129 (ins CPURegs:$b, CPURegs:$c),
130 !strconcat(instr_asm, " $dst, $b, $c"),
131 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
133 let isCommutable = 1 in
134 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
138 (ins CPURegs:$b, CPURegs:$c),
139 !strconcat(instr_asm, " $dst, $b, $c"),
142 // Arithmetic 2 register operands
143 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
144 Operand Od, PatLeaf imm_type> :
147 (ins CPURegs:$b, Od:$c),
148 !strconcat(instr_asm, " $dst, $b, $c"),
149 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
151 // Arithmetic Multiply ADD/SUB
153 class MArithR<bits<6> func, string instr_asm> :
158 !strconcat(instr_asm, " $rs, $rt"),
162 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
166 (ins CPURegs:$b, CPURegs:$c),
167 !strconcat(instr_asm, " $dst, $b, $c"),
168 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
170 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
173 (ins CPURegs:$b, uimm16:$c),
174 !strconcat(instr_asm, " $dst, $b, $c"),
175 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
177 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
181 (ins CPURegs:$b, CPURegs:$c),
182 !strconcat(instr_asm, " $dst, $b, $c"),
183 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
187 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
191 (ins CPURegs:$b, shamt:$c),
192 !strconcat(instr_asm, " $dst, $b, $c"),
193 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
195 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
199 (ins CPURegs:$b, CPURegs:$c),
200 !strconcat(instr_asm, " $dst, $b, $c"),
201 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
203 // Load Upper Imediate
204 class LoadUpper<bits<6> op, string instr_asm>:
208 !strconcat(instr_asm, " $dst, $imm"),
212 let isSimpleLoad = 1, hasDelaySlot = 1 in
213 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
217 !strconcat(instr_asm, " $dst, $addr"),
218 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
220 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
223 (ins CPURegs:$dst, mem:$addr),
224 !strconcat(instr_asm, " $dst, $addr"),
225 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
227 // Conditional Branch
228 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
229 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
232 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
233 !strconcat(instr_asm, " $a, $b, $offset"),
234 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
238 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
241 (ins CPURegs:$src, brtarget:$offset),
242 !strconcat(instr_asm, " $src, $offset"),
243 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
248 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
253 (ins CPURegs:$b, CPURegs:$c),
254 !strconcat(instr_asm, " $dst, $b, $c"),
255 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
258 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
259 Operand Od, PatLeaf imm_type>:
262 (ins CPURegs:$b, Od:$c),
263 !strconcat(instr_asm, " $dst, $b, $c"),
264 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
267 // Unconditional branch
268 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
269 class JumpFJ<bits<6> op, string instr_asm>:
272 (ins brtarget:$target),
273 !strconcat(instr_asm, " $target"),
274 [(br bb:$target)], IIBranch>;
276 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
277 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
281 (ins CPURegs:$target),
282 !strconcat(instr_asm, " $target"),
283 [(brind CPURegs:$target)], IIBranch>;
285 // Jump and Link (Call)
286 let isCall=1, hasDelaySlot=1,
287 // All calls clobber the non-callee saved registers...
288 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
289 T3, T4, T5, T6, T7, T8, T9, K0, K1], Uses = [GP] in {
290 class JumpLink<bits<6> op, string instr_asm>:
293 (ins calltarget:$target),
294 !strconcat(instr_asm, " $target"),
295 [(MipsJmpLink imm:$target)], IIBranch>;
298 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
303 !strconcat(instr_asm, " $rs"),
304 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
306 class BranchLink<string instr_asm>:
309 (ins CPURegs:$rs, brtarget:$target),
310 !strconcat(instr_asm, " $rs, $target"),
315 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
319 (ins CPURegs:$a, CPURegs:$b),
320 !strconcat(instr_asm, " $a, $b"),
324 class MoveFromTo<bits<6> func, string instr_asm>:
329 !strconcat(instr_asm, " $dst"),
332 // Count Leading Ones/Zeros in Word
333 class CountLeading<bits<6> func, string instr_asm>:
338 !strconcat(instr_asm, " $dst, $src"),
341 class EffectiveAddress<string instr_asm> :
346 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
348 //===----------------------------------------------------------------------===//
349 // Pseudo instructions
350 //===----------------------------------------------------------------------===//
352 // As stack alignment is always done with addiu, we need a 16-bit immediate
353 let Defs = [SP], Uses = [SP] in {
354 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
355 "!ADJCALLSTACKDOWN $amt",
356 [(callseq_start imm:$amt)]>;
357 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
358 "!ADJCALLSTACKUP $amt1",
359 [(callseq_end imm:$amt1, imm:$amt2)]>;
362 // When handling PIC code the assembler needs .cpload and .cprestore
363 // directives. If the real instructions corresponding these directives
364 // are used, we have the same behavior, but get also a bunch of warnings
365 // from the assembler.
366 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$reg),
367 ".set noreorder\n\t.cpload $reg\n\t.set reorder\n",
369 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc),
370 ".cprestore $loc\n", []>;
372 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
373 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
374 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
375 // replace it for real supported nodes into EmitInstrWithCustomInserter
376 let usesCustomDAGSchedInserter = 1 in {
377 def Select_CC : MipsPseudo<(outs CPURegs:$dst),
378 (ins CPURegs:$CmpRes, CPURegs:$T, CPURegs:$F), "# MipsSelect_CC",
379 [(set CPURegs:$dst, (MipsSelectCC CPURegs:$CmpRes,
380 CPURegs:$T, CPURegs:$F))]>;
383 //===----------------------------------------------------------------------===//
384 // Instruction definition
385 //===----------------------------------------------------------------------===//
387 //===----------------------------------------------------------------------===//
388 // MipsI Instructions
389 //===----------------------------------------------------------------------===//
393 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
394 // immZExt32 is used here so it can match GlobalAddress immediates.
395 // MUL is a assembly macro in the current used ISAs.
396 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immZExt16>;
397 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
398 //def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
399 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
400 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
401 def ADD : ArithOverflowR<0x00, 0x20, "add">;
402 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
405 def AND : LogicR<0x24, "and", and>;
406 def OR : LogicR<0x25, "or", or>;
407 def XOR : LogicR<0x26, "xor", xor>;
408 def ANDi : LogicI<0x0c, "andi", and>;
409 def ORi : LogicI<0x0d, "ori", or>;
410 def XORi : LogicI<0x0e, "xori", xor>;
411 def NOR : LogicNOR<0x00, 0x27, "nor">;
414 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
415 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
416 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
417 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
418 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
419 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
421 // Load Upper Immediate
422 def LUi : LoadUpper<0x0f, "lui">;
425 def LB : LoadM<0x20, "lb", sextloadi8>;
426 def LBu : LoadM<0x24, "lbu", zextloadi8>;
427 def LH : LoadM<0x21, "lh", sextloadi16>;
428 def LHu : LoadM<0x25, "lhu", zextloadi16>;
429 def LW : LoadM<0x23, "lw", load>;
430 def SB : StoreM<0x28, "sb", truncstorei8>;
431 def SH : StoreM<0x29, "sh", truncstorei16>;
432 def SW : StoreM<0x2b, "sw", store>;
434 // Conditional Branch
435 def BEQ : CBranch<0x04, "beq", seteq>;
436 def BNE : CBranch<0x05, "bne", setne>;
439 def BGEZ : CBranchZero<0x01, "bgez", setge>;
442 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
443 def BLEZ : CBranchZero<0x07, "blez", setle>;
444 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
447 // Set Condition Code
448 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
449 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
450 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
451 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
453 // Unconditional jump
454 def J : JumpFJ<0x02, "j">;
455 def JR : JumpFR<0x00, 0x08, "jr">;
457 // Jump and Link (Call)
458 def JAL : JumpLink<0x03, "jal">;
459 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
460 def BGEZAL : BranchLink<"bgezal">;
461 def BLTZAL : BranchLink<"bltzal">;
463 // MulDiv and Move From Hi/Lo operations, have
464 // their correpondent SDNodes created on ISelDAG.
465 // Special Mul, Div operations
466 def MULT : MulDiv<0x18, "mult", IIImul>;
467 def MULTu : MulDiv<0x19, "multu", IIImul>;
468 def DIV : MulDiv<0x1a, "div", IIIdiv>;
469 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
472 def MFHI : MoveFromTo<0x10, "mfhi">;
473 def MFLO : MoveFromTo<0x12, "mflo">;
474 def MTHI : MoveFromTo<0x11, "mthi">;
475 def MTLO : MoveFromTo<0x13, "mtlo">;
478 // CLO/CLZ are part of the newer MIPS32(tm) instruction
479 // set and not older Mips I keep this for future use
481 //def CLO : CountLeading<0x21, "clo">;
482 //def CLZ : CountLeading<0x20, "clz">;
484 // MADD*/MSUB* are not part of MipsI either.
485 //def MADD : MArithR<0x00, "madd">;
486 //def MADDU : MArithR<0x01, "maddu">;
487 //def MSUB : MArithR<0x04, "msub">;
488 //def MSUBU : MArithR<0x05, "msubu">;
492 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
494 // Ret instruction - as mips does not have "ret" a
495 // jr $ra must be generated.
496 let isReturn=1, isTerminator=1, hasDelaySlot=1,
497 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
499 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
500 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
503 // FrameIndexes are legalized when they are operands from load/store
504 // instructions. The same not happens for stack address copies, so an
505 // add op with mem ComplexPattern is used and the stack address copy
506 // can be matched. It's similar to Sparc LEA_ADDRi
507 def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
509 //===----------------------------------------------------------------------===//
510 // Arbitrary patterns that map to one or more instructions
511 //===----------------------------------------------------------------------===//
514 def : Pat<(i32 immSExt16:$in),
515 (ADDiu ZERO, imm:$in)>;
516 def : Pat<(i32 immZExt16:$in),
517 (ORi ZERO, imm:$in)>;
519 // Arbitrary immediates
520 def : Pat<(i32 imm:$imm),
521 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
524 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
525 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
526 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
527 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
528 def : Pat<(addc CPURegs:$src, imm:$imm),
529 (ADDiu CPURegs:$src, imm:$imm)>;
532 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
533 (JAL tglobaladdr:$dst)>;
534 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
535 (JAL texternalsym:$dst)>;
536 def : Pat<(MipsJmpLink CPURegs:$dst),
537 (JALR CPURegs:$dst)>;
539 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
540 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
541 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
542 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
543 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
544 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
545 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
546 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
547 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
549 // Mips does not have not, so we increase the operation
550 def : Pat<(not CPURegs:$in),
551 (NOR CPURegs:$in, ZERO)>;
553 // extended load and stores
554 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
555 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
556 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
559 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
565 // direct match equal/notequal zero branches
566 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
567 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
568 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
569 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
571 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
572 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
573 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
574 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
576 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
577 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
578 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
579 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
581 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
582 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
583 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
584 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
586 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
587 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
588 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
589 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
590 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
591 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
592 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
593 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
595 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
596 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
597 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
598 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
600 // generic brcond pattern
601 def : Pat<(brcond CPURegs:$cond, bb:$dst),
602 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
605 /// setcc patterns, only matched when there
606 /// is no brcond following a setcc operation
609 // setcc 2 register operands
610 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
611 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
612 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
613 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
615 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
616 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
617 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
618 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
620 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
621 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
622 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
623 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
625 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
626 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
627 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
629 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
630 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
631 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
633 // setcc reg/imm operands
634 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
635 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
636 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
637 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;