1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
186 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
187 let Predicates = [HasStdEnc];
191 bit isCommutable = 1;
208 bit isTerminator = 1;
211 bit hasExtraSrcRegAllocReq = 1;
212 bit isCodeGenOnly = 1;
215 class IsAsCheapAsAMove {
216 bit isAsCheapAsAMove = 1;
219 class NeverHasSideEffects {
220 bit neverHasSideEffects = 1;
223 //===----------------------------------------------------------------------===//
224 // Instruction format superclass
225 //===----------------------------------------------------------------------===//
227 include "MipsInstrFormats.td"
229 //===----------------------------------------------------------------------===//
230 // Mips Operand, Complex Patterns and Transformations Definitions.
231 //===----------------------------------------------------------------------===//
233 // Instruction operand types
234 def jmptarget : Operand<OtherVT> {
235 let EncoderMethod = "getJumpTargetOpValue";
237 def brtarget : Operand<OtherVT> {
238 let EncoderMethod = "getBranchTargetOpValue";
239 let OperandType = "OPERAND_PCREL";
240 let DecoderMethod = "DecodeBranchTarget";
242 def calltarget : Operand<iPTR> {
243 let EncoderMethod = "getJumpTargetOpValue";
245 def calltarget64: Operand<i64>;
246 def simm16 : Operand<i32> {
247 let DecoderMethod= "DecodeSimm16";
250 def simm20 : Operand<i32> {
253 def uimm20 : Operand<i32> {
256 def uimm10 : Operand<i32> {
259 def simm16_64 : Operand<i64>;
260 def shamt : Operand<i32>;
263 def uimm16 : Operand<i32> {
264 let PrintMethod = "printUnsignedImm";
267 def MipsMemAsmOperand : AsmOperandClass {
269 let ParserMethod = "parseMemOperand";
273 def mem : Operand<i32> {
274 let PrintMethod = "printMemOperand";
275 let MIOperandInfo = (ops GPR32, simm16);
276 let EncoderMethod = "getMemEncoding";
277 let ParserMatchClass = MipsMemAsmOperand;
278 let OperandType = "OPERAND_MEMORY";
281 def mem64 : Operand<i64> {
282 let PrintMethod = "printMemOperand";
283 let MIOperandInfo = (ops GPR64, simm16_64);
284 let EncoderMethod = "getMemEncoding";
285 let ParserMatchClass = MipsMemAsmOperand;
286 let OperandType = "OPERAND_MEMORY";
289 def mem_ea : Operand<i32> {
290 let PrintMethod = "printMemOperandEA";
291 let MIOperandInfo = (ops GPR32, simm16);
292 let EncoderMethod = "getMemEncoding";
293 let OperandType = "OPERAND_MEMORY";
296 def mem_ea_64 : Operand<i64> {
297 let PrintMethod = "printMemOperandEA";
298 let MIOperandInfo = (ops GPR64, simm16_64);
299 let EncoderMethod = "getMemEncoding";
300 let OperandType = "OPERAND_MEMORY";
303 // size operand of ext instruction
304 def size_ext : Operand<i32> {
305 let EncoderMethod = "getSizeExtEncoding";
306 let DecoderMethod = "DecodeExtSize";
309 // size operand of ins instruction
310 def size_ins : Operand<i32> {
311 let EncoderMethod = "getSizeInsEncoding";
312 let DecoderMethod = "DecodeInsSize";
315 // Transformation Function - get the lower 16 bits.
316 def LO16 : SDNodeXForm<imm, [{
317 return getImm(N, N->getZExtValue() & 0xFFFF);
320 // Transformation Function - get the higher 16 bits.
321 def HI16 : SDNodeXForm<imm, [{
322 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
326 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
328 // Node immediate fits as 16-bit sign extended on target immediate.
330 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
332 // Node immediate fits as 16-bit sign extended on target immediate.
334 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
336 // Node immediate fits as 15-bit sign extended on target immediate.
338 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
340 // Node immediate fits as 16-bit zero extended on target immediate.
341 // The LO16 param means that only the lower 16 bits of the node
342 // immediate are caught.
344 def immZExt16 : PatLeaf<(imm), [{
345 if (N->getValueType(0) == MVT::i32)
346 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
348 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
351 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
352 def immLow16Zero : PatLeaf<(imm), [{
353 int64_t Val = N->getSExtValue();
354 return isInt<32>(Val) && !(Val & 0xffff);
357 // shamt field must fit in 5 bits.
358 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
360 // True if (N + 1) fits in 16-bit field.
361 def immSExt16Plus1 : PatLeaf<(imm), [{
362 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
365 // Mips Address Mode! SDNode frameindex could possibily be a match
366 // since load and store instructions from stack used it.
368 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
371 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
374 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
376 //===----------------------------------------------------------------------===//
377 // Instructions specific format
378 //===----------------------------------------------------------------------===//
380 // Arithmetic and logical instructions with 3 register operands.
381 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
382 InstrItinClass Itin = NoItinerary,
383 SDPatternOperator OpNode = null_frag>:
384 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
385 !strconcat(opstr, "\t$rd, $rs, $rt"),
386 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
387 let isCommutable = isComm;
388 let isReMaterializable = 1;
391 // Arithmetic and logical instructions with 2 register operands.
392 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
393 InstrItinClass Itin = NoItinerary,
394 SDPatternOperator imm_type = null_frag,
395 SDPatternOperator OpNode = null_frag> :
396 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
397 !strconcat(opstr, "\t$rt, $rs, $imm16"),
398 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
400 let isReMaterializable = 1;
401 let TwoOperandAliasConstraint = "$rs = $rt";
404 // Arithmetic Multiply ADD/SUB
405 class MArithR<string opstr, bit isComm = 0> :
406 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
407 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
410 let isCommutable = isComm;
414 class LogicNOR<string opstr, RegisterOperand RO>:
415 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
416 !strconcat(opstr, "\t$rd, $rs, $rt"),
417 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
418 let isCommutable = 1;
422 class shift_rotate_imm<string opstr, Operand ImmOpnd,
423 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
424 SDPatternOperator PF = null_frag> :
425 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
426 !strconcat(opstr, "\t$rd, $rt, $shamt"),
427 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
429 class shift_rotate_reg<string opstr, RegisterOperand RO,
430 SDPatternOperator OpNode = null_frag>:
431 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
432 !strconcat(opstr, "\t$rd, $rt, $rs"),
433 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
435 // Load Upper Imediate
436 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
437 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
438 [], IIArith, FrmI>, IsAsCheapAsAMove {
439 let neverHasSideEffects = 1;
440 let isReMaterializable = 1;
443 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
444 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
446 let Inst{25-21} = addr{20-16};
447 let Inst{15-0} = addr{15-0};
448 let DecoderMethod = "DecodeMem";
452 class Load<string opstr, SDPatternOperator OpNode, DAGOperand RO,
453 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
455 InstSE<(outs RO:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
456 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
457 !strconcat(opstr, ofsuffix)> {
458 let DecoderMethod = "DecodeMem";
459 let canFoldAsLoad = 1;
463 class Store<string opstr, SDPatternOperator OpNode, DAGOperand RO,
464 InstrItinClass Itin, Operand MemOpnd, ComplexPattern Addr,
466 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
467 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI,
468 !strconcat(opstr, ofsuffix)> {
469 let DecoderMethod = "DecodeMem";
473 multiclass LoadM<string opstr, DAGOperand RO,
474 SDPatternOperator OpNode = null_frag,
475 InstrItinClass Itin = NoItinerary,
476 ComplexPattern Addr = addr> {
477 def NAME : Load<opstr, OpNode, RO, Itin, mem, Addr, "">,
478 Requires<[NotN64, HasStdEnc]>;
479 def _P8 : Load<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
480 Requires<[IsN64, HasStdEnc]> {
481 let DecoderNamespace = "Mips64";
482 let isCodeGenOnly = 1;
486 multiclass StoreM<string opstr, DAGOperand RO,
487 SDPatternOperator OpNode = null_frag,
488 InstrItinClass Itin = NoItinerary,
489 ComplexPattern Addr = addr> {
490 def NAME : Store<opstr, OpNode, RO, Itin, mem, Addr, "">,
491 Requires<[NotN64, HasStdEnc]>;
492 def _P8 : Store<opstr, OpNode, RO, Itin, mem64, Addr, "_p8">,
493 Requires<[IsN64, HasStdEnc]> {
494 let DecoderNamespace = "Mips64";
495 let isCodeGenOnly = 1;
499 // Load/Store Left/Right
500 let canFoldAsLoad = 1 in
501 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
503 InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src),
504 !strconcat(opstr, "\t$rt, $addr"),
505 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
506 let DecoderMethod = "DecodeMem";
507 string Constraints = "$src = $rt";
510 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
512 InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
513 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
514 let DecoderMethod = "DecodeMem";
517 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
518 def NAME : LoadLeftRight<opstr, OpNode, RO, mem>,
519 Requires<[NotN64, HasStdEnc]>;
520 def _P8 : LoadLeftRight<opstr, OpNode, RO, mem64>,
521 Requires<[IsN64, HasStdEnc]> {
522 let DecoderNamespace = "Mips64";
523 let isCodeGenOnly = 1;
527 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterOperand RO> {
528 def NAME : StoreLeftRight<opstr, OpNode, RO, mem>,
529 Requires<[NotN64, HasStdEnc]>;
530 def _P8 : StoreLeftRight<opstr, OpNode, RO, mem64>,
531 Requires<[IsN64, HasStdEnc]> {
532 let DecoderNamespace = "Mips64";
533 let isCodeGenOnly = 1;
537 // Conditional Branch
538 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
539 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
540 !strconcat(opstr, "\t$rs, $rt, $offset"),
541 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
544 let isTerminator = 1;
545 let hasDelaySlot = 1;
549 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
550 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
551 !strconcat(opstr, "\t$rs, $offset"),
552 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
554 let isTerminator = 1;
555 let hasDelaySlot = 1;
560 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
561 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
562 !strconcat(opstr, "\t$rd, $rs, $rt"),
563 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
566 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
568 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
569 !strconcat(opstr, "\t$rt, $rs, $imm16"),
570 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
574 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
575 SDPatternOperator targetoperator> :
576 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
577 [(operator targetoperator:$target)], IIBranch, FrmJ> {
580 let hasDelaySlot = 1;
581 let DecoderMethod = "DecodeJumpTarget";
585 // Unconditional branch
586 class UncondBranch<string opstr> :
587 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
588 [(br bb:$offset)], IIBranch, FrmI> {
590 let isTerminator = 1;
592 let hasDelaySlot = 1;
593 let Predicates = [RelocPIC, HasStdEnc];
597 // Base class for indirect branch and return instruction classes.
598 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
599 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
600 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
603 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
605 let isIndirectBranch = 1;
608 // Return instruction
609 class RetBase<RegisterOperand RO>: JumpFR<RO> {
611 let isCodeGenOnly = 1;
613 let hasExtraSrcRegAllocReq = 1;
616 // Jump and Link (Call)
617 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
618 class JumpLink<string opstr> :
619 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
620 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
621 let DecoderMethod = "DecodeJumpTarget";
624 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
625 Register RetReg, RegisterOperand ResRO = RO>:
626 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
627 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
629 class JumpLinkReg<string opstr, RegisterOperand RO>:
630 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
633 class BGEZAL_FT<string opstr, RegisterOperand RO> :
634 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
635 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
639 class BAL_BR_Pseudo<Instruction RealInst> :
640 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
641 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
643 let isTerminator = 1;
645 let hasDelaySlot = 1;
650 class SYS_FT<string opstr> :
651 InstSE<(outs), (ins uimm20:$code_),
652 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
654 class BRK_FT<string opstr> :
655 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
656 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
659 class ER_FT<string opstr> :
660 InstSE<(outs), (ins),
661 opstr, [], NoItinerary, FrmOther>;
664 class DEI_FT<string opstr, RegisterOperand RO> :
665 InstSE<(outs RO:$rt), (ins),
666 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
669 let hasSideEffects = 1 in
671 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
672 NoItinerary, FrmOther>;
674 let hasSideEffects = 1 in
675 class TEQ_FT<string opstr, RegisterOperand RO> :
676 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
677 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
680 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
681 list<Register> DefRegs> :
682 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
684 let isCommutable = 1;
686 let neverHasSideEffects = 1;
689 // Pseudo multiply/divide instruction with explicit accumulator register
691 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
692 SDPatternOperator OpNode, InstrItinClass Itin,
693 bit IsComm = 1, bit HasSideEffects = 0,
694 bit UsesCustomInserter = 0> :
695 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
696 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
697 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
698 let isCommutable = IsComm;
699 let hasSideEffects = HasSideEffects;
700 let usesCustomInserter = UsesCustomInserter;
703 // Pseudo multiply add/sub instruction with explicit accumulator register
705 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
706 : PseudoSE<(outs ACC64:$ac),
707 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
709 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
711 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
712 string Constraints = "$acin = $ac";
715 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
716 list<Register> DefRegs> :
717 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
723 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
724 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
726 let neverHasSideEffects = 1;
729 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
730 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
732 let neverHasSideEffects = 1;
735 class EffectiveAddress<string opstr, RegisterOperand RO, Operand Mem> :
736 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
737 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
738 let isCodeGenOnly = 1;
739 let DecoderMethod = "DecodeMem";
742 // Count Leading Ones/Zeros in Word
743 class CountLeading0<string opstr, RegisterOperand RO>:
744 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
745 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
746 Requires<[HasBitCount, HasStdEnc]>;
748 class CountLeading1<string opstr, RegisterOperand RO>:
749 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
750 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
751 Requires<[HasBitCount, HasStdEnc]>;
754 // Sign Extend in Register.
755 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
756 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
757 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
758 let Predicates = [HasSEInReg, HasStdEnc];
762 class SubwordSwap<string opstr, RegisterOperand RO>:
763 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
765 let Predicates = [HasSwap, HasStdEnc];
766 let neverHasSideEffects = 1;
770 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
771 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
775 class ExtBase<string opstr, RegisterOperand RO>:
776 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
777 !strconcat(opstr, " $rt, $rs, $pos, $size"),
778 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
780 let Predicates = [HasMips32r2, HasStdEnc];
783 class InsBase<string opstr, RegisterOperand RO>:
784 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
785 !strconcat(opstr, " $rt, $rs, $pos, $size"),
786 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
788 let Predicates = [HasMips32r2, HasStdEnc];
789 let Constraints = "$src = $rt";
792 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
793 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
794 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
795 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
797 multiclass Atomic2Ops32<PatFrag Op> {
798 def NAME : Atomic2Ops<Op, GPR32, GPR32>, Requires<[NotN64, HasStdEnc]>;
799 def _P8 : Atomic2Ops<Op, GPR32, GPR64>, Requires<[IsN64, HasStdEnc]>;
802 // Atomic Compare & Swap.
803 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
804 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
805 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
807 multiclass AtomicCmpSwap32<PatFrag Op> {
808 def NAME : AtomicCmpSwap<Op, GPR32, GPR32>,
809 Requires<[NotN64, HasStdEnc]>;
810 def _P8 : AtomicCmpSwap<Op, GPR32, GPR64>,
811 Requires<[IsN64, HasStdEnc]>;
814 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
815 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
816 [], NoItinerary, FrmI> {
817 let DecoderMethod = "DecodeMem";
821 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
822 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
823 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
824 let DecoderMethod = "DecodeMem";
826 let Constraints = "$rt = $dst";
829 class MFC3OP<dag outs, dag ins, string asmstr> :
830 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
832 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
833 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
834 let Inst = 0x0000000d;
837 //===----------------------------------------------------------------------===//
838 // Pseudo instructions
839 //===----------------------------------------------------------------------===//
842 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
843 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
845 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
846 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
847 [(callseq_start timm:$amt)]>;
848 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
849 [(callseq_end timm:$amt1, timm:$amt2)]>;
852 let usesCustomInserter = 1 in {
853 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
854 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
855 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
856 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
857 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
858 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
859 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
860 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
861 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
862 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
863 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
864 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
865 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
866 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
867 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
868 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
869 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
870 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
872 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
873 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
874 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
876 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
877 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
878 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
881 /// Pseudo instructions for loading and storing accumulator registers.
882 let isPseudo = 1, isCodeGenOnly = 1 in {
883 defm LOAD_ACC64 : LoadM<"", ACC64>;
884 defm STORE_ACC64 : StoreM<"", ACC64>;
887 //===----------------------------------------------------------------------===//
888 // Instruction definition
889 //===----------------------------------------------------------------------===//
890 //===----------------------------------------------------------------------===//
891 // MipsI Instructions
892 //===----------------------------------------------------------------------===//
894 /// Arithmetic Instructions (ALU Immediate)
895 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
897 ADDI_FM<0x9>, IsAsCheapAsAMove;
898 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
899 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
901 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
903 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
906 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
909 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
912 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
914 /// Arithmetic Instructions (3-Operand, R-Type)
915 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
917 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
919 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
921 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
922 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
923 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
924 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
925 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
927 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
929 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
931 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
933 /// Shift Instructions
934 def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>,
936 def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>,
938 def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>,
940 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
941 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
942 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
944 // Rotate Instructions
945 let Predicates = [HasMips32r2, HasStdEnc] in {
946 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr,
949 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
953 /// Load and Store Instructions
955 defm LB : LoadM<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
956 defm LBu : LoadM<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
958 defm LH : LoadM<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
960 defm LHu : LoadM<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
961 defm LW : LoadM<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
963 defm SB : StoreM<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
964 defm SH : StoreM<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
965 defm SW : StoreM<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
967 /// load/store left/right
968 defm LWL : LoadLeftRightM<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
969 defm LWR : LoadLeftRightM<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
970 defm SWL : StoreLeftRightM<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
971 defm SWR : StoreLeftRightM<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
973 def SYNC : SYNC_FT, SYNC_FM;
974 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
976 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
977 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
979 def ERET : ER_FT<"eret">, ER_FM<0x18>;
980 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
982 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
983 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
985 /// Load-linked, Store-conditional
986 let Predicates = [NotN64, HasStdEnc] in {
987 def LL : LLBase<"ll", GPR32Opnd, mem>, LW_FM<0x30>;
988 def SC : SCBase<"sc", GPR32Opnd, mem>, LW_FM<0x38>;
991 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
992 def LL_P8 : LLBase<"ll", GPR32Opnd, mem64>, LW_FM<0x30>;
993 def SC_P8 : SCBase<"sc", GPR32Opnd, mem64>, LW_FM<0x38>;
996 /// Jump and Branch Instructions
997 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
998 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
999 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
1000 def B : UncondBranch<"b">, B_FM;
1001 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
1002 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
1003 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
1004 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
1005 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
1006 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
1008 def JAL : JumpLink<"jal">, FJ<3>;
1009 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1010 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1011 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
1012 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
1013 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1014 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
1015 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
1017 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
1019 // Exception handling related node and instructions.
1020 // The conversion sequence is:
1021 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1022 // MIPSeh_return -> (stack change + indirect branch)
1024 // MIPSeh_return takes the place of regular return instruction
1025 // but takes two arguments (V1, V0) which are used for storing
1026 // the offset and return address respectively.
1027 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1029 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1030 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1032 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1033 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1034 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1035 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1037 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1040 /// Multiply and Divide Instructions.
1041 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI, LO]>,
1043 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI, LO]>,
1045 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1046 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1047 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1a>;
1048 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI, LO]>, MULT_FM<0, 0x1b>;
1049 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1051 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1054 def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI]>, MTLO_FM<0x11>;
1055 def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO]>, MTLO_FM<0x13>;
1056 def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI]>, MFLO_FM<0x10>;
1057 def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO]>, MFLO_FM<0x12>;
1059 /// Sign Ext In Register Instructions.
1060 def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1061 def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1064 def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1065 def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1067 /// Word Swap Bytes Within Halfwords
1068 def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1071 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1073 // FrameIndexes are legalized when they are operands from load/store
1074 // instructions. The same not happens for stack address copies, so an
1075 // add op with mem ComplexPattern is used and the stack address copy
1076 // can be matched. It's similar to Sparc LEA_ADDRi
1077 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd, mem_ea>, LW_FM<9>;
1080 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1081 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1082 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1083 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1084 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1085 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1086 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1087 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1089 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1091 def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>;
1092 def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>;
1094 /// Move Control Registers From/To CPU Registers
1095 def MFC0_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1096 (ins GPR32Opnd:$rd, uimm16:$sel),
1097 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1099 def MTC0_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1100 (ins GPR32Opnd:$rt),
1101 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1103 def MFC2_3OP : MFC3OP<(outs GPR32Opnd:$rt),
1104 (ins GPR32Opnd:$rd, uimm16:$sel),
1105 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1107 def MTC2_3OP : MFC3OP<(outs GPR32Opnd:$rd, uimm16:$sel),
1108 (ins GPR32Opnd:$rt),
1109 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1111 //===----------------------------------------------------------------------===//
1112 // Instruction aliases
1113 //===----------------------------------------------------------------------===//
1114 def : InstAlias<"move $dst, $src",
1115 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1116 Requires<[NotMips64]>;
1117 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1118 def : InstAlias<"addu $rs, $rt, $imm",
1119 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1120 def : InstAlias<"add $rs, $rt, $imm",
1121 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1122 def : InstAlias<"and $rs, $rt, $imm",
1123 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1124 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1125 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1126 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1127 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1128 def : InstAlias<"not $rt, $rs",
1129 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1130 def : InstAlias<"neg $rt, $rs",
1131 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1132 def : InstAlias<"negu $rt, $rs",
1133 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1134 def : InstAlias<"slt $rs, $rt, $imm",
1135 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1136 def : InstAlias<"xor $rs, $rt, $imm",
1137 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1138 def : InstAlias<"or $rs, $rt, $imm",
1139 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1140 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1141 def : InstAlias<"mfc0 $rt, $rd",
1142 (MFC0_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1143 def : InstAlias<"mtc0 $rt, $rd",
1144 (MTC0_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1145 def : InstAlias<"mfc2 $rt, $rd",
1146 (MFC2_3OP GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1147 def : InstAlias<"mtc2 $rt, $rd",
1148 (MTC2_3OP GPR32Opnd:$rd, 0, GPR32Opnd:$rt), 0>;
1149 def : InstAlias<"bnez $rs,$offset",
1150 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1151 def : InstAlias<"beqz $rs,$offset",
1152 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1153 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1155 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1156 def : InstAlias<"break", (BREAK 0, 0), 1>;
1157 def : InstAlias<"ei", (EI ZERO), 1>;
1158 def : InstAlias<"di", (DI ZERO), 1>;
1159 //===----------------------------------------------------------------------===//
1160 // Assembler Pseudo Instructions
1161 //===----------------------------------------------------------------------===//
1163 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1164 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1165 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1166 def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>;
1168 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1169 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1170 !strconcat(instr_asm, "\t$rt, $addr")> ;
1171 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1173 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1174 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1175 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1176 def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>;
1180 //===----------------------------------------------------------------------===//
1181 // Arbitrary patterns that map to one or more instructions
1182 //===----------------------------------------------------------------------===//
1184 // Load/store pattern templates.
1185 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1186 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1188 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1189 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1192 def : MipsPat<(i32 immSExt16:$in),
1193 (ADDiu ZERO, imm:$in)>;
1194 def : MipsPat<(i32 immZExt16:$in),
1195 (ORi ZERO, imm:$in)>;
1196 def : MipsPat<(i32 immLow16Zero:$in),
1197 (LUi (HI16 imm:$in))>;
1199 // Arbitrary immediates
1200 def : MipsPat<(i32 imm:$imm),
1201 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1203 // Carry MipsPatterns
1204 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1205 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1206 let Predicates = [HasStdEnc, NotDSP] in {
1207 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1208 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1209 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1210 (ADDiu GPR32:$src, imm:$imm)>;
1214 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1215 (JAL tglobaladdr:$dst)>;
1216 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1217 (JAL texternalsym:$dst)>;
1218 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1219 // (JALR GPR32:$dst)>;
1222 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1223 (TAILCALL tglobaladdr:$dst)>;
1224 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1225 (TAILCALL texternalsym:$dst)>;
1227 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1228 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1229 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1230 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1231 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1232 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1234 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1235 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1236 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1237 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1238 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1239 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1241 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1242 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1243 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1244 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1245 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1246 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1247 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1248 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1249 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1250 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1253 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1254 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1255 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1256 (ADDiu GPR32:$gp, tconstpool:$in)>;
1259 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1260 MipsPat<(MipsWrapper RC:$gp, node:$in),
1261 (ADDiuOp RC:$gp, node:$in)>;
1263 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1264 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1265 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1266 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1267 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1268 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1270 // Mips does not have "not", so we expand our way
1271 def : MipsPat<(not GPR32:$in),
1272 (NOR GPR32Opnd:$in, ZERO)>;
1275 let Predicates = [NotN64, HasStdEnc] in {
1276 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1277 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1278 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1280 let Predicates = [IsN64, HasStdEnc] in {
1281 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1282 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1283 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1287 let Predicates = [NotN64, HasStdEnc] in {
1288 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1290 let Predicates = [IsN64, HasStdEnc] in {
1291 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1295 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1296 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1297 Instruction SLTiuOp, Register ZEROReg> {
1298 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1299 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1300 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1301 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1303 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1304 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1305 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1306 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1307 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1308 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1309 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1310 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1311 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1312 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1313 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1314 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1316 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1317 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1318 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1319 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1321 def : MipsPat<(brcond RC:$cond, bb:$dst),
1322 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1325 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1327 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1328 (BLEZ i32:$lhs, bb:$dst)>;
1329 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1330 (BGEZ i32:$lhs, bb:$dst)>;
1333 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1334 Instruction SLTuOp, Register ZEROReg> {
1335 def : MipsPat<(seteq RC:$lhs, 0),
1336 (SLTiuOp RC:$lhs, 1)>;
1337 def : MipsPat<(setne RC:$lhs, 0),
1338 (SLTuOp ZEROReg, RC:$lhs)>;
1339 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1340 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1341 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1342 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1345 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1346 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1347 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1348 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1349 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1352 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1353 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1354 (SLTOp RC:$rhs, RC:$lhs)>;
1355 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1356 (SLTuOp RC:$rhs, RC:$lhs)>;
1359 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1360 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1361 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1362 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1363 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1366 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1367 Instruction SLTiuOp> {
1368 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1369 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1370 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1371 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1374 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1375 defm : SetlePats<GPR32, SLT, SLTu>;
1376 defm : SetgtPats<GPR32, SLT, SLTu>;
1377 defm : SetgePats<GPR32, SLT, SLTu>;
1378 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1381 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1383 // mflo/hi patterns.
1384 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1385 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1387 // Load halfword/word patterns.
1388 let AddedComplexity = 40 in {
1389 let Predicates = [NotN64, HasStdEnc] in {
1390 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1391 def : LoadRegImmPat<LH, i32, sextloadi16>;
1392 def : LoadRegImmPat<LW, i32, load>;
1394 let Predicates = [IsN64, HasStdEnc] in {
1395 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1396 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1397 def : LoadRegImmPat<LW_P8, i32, load>;
1401 //===----------------------------------------------------------------------===//
1402 // Floating Point Support
1403 //===----------------------------------------------------------------------===//
1405 include "MipsInstrFPU.td"
1406 include "Mips64InstrInfo.td"
1407 include "MipsCondMov.td"
1412 include "Mips16InstrFormats.td"
1413 include "Mips16InstrInfo.td"
1416 include "MipsDSPInstrFormats.td"
1417 include "MipsDSPInstrInfo.td"
1420 include "MicroMipsInstrFormats.td"
1421 include "MicroMipsInstrInfo.td"