1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"!FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
170 AssemblerPredicate<"FeatureMips32r5">;
171 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"FeatureMips32r6">;
173 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
174 AssemblerPredicate<"!FeatureMips32r6">;
175 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
176 AssemblerPredicate<"FeatureGP64Bit">;
177 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
178 AssemblerPredicate<"!FeatureGP64Bit">;
179 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
180 AssemblerPredicate<"FeatureMips64">;
181 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
182 AssemblerPredicate<"FeatureMips64r2">;
183 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"FeatureMips64r6">;
185 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
186 AssemblerPredicate<"!FeatureMips64r6">;
187 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
188 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
189 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
190 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
191 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
192 AssemblerPredicate<"FeatureMips16">;
193 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
194 AssemblerPredicate<"FeatureCnMips">;
195 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
196 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
197 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
198 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
199 AssemblerPredicate<"!FeatureMips16">;
200 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
201 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
202 AssemblerPredicate<"FeatureMicroMips">;
203 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
204 AssemblerPredicate<"!FeatureMicroMips">;
205 def IsLE : Predicate<"Subtarget->isLittle()">;
206 def IsBE : Predicate<"!Subtarget->isLittle()">;
207 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
208 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
209 def HasEVA : Predicate<"Subtarget->hasEVA()">,
210 AssemblerPredicate<"FeatureEVA,FeatureMips32r2">;
211 def HasMSA : Predicate<"Subtarget->hasMSA()">,
212 AssemblerPredicate<"FeatureMSA">;
215 //===----------------------------------------------------------------------===//
216 // Mips GPR size adjectives.
217 // They are mutually exclusive.
218 //===----------------------------------------------------------------------===//
220 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
221 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
223 //===----------------------------------------------------------------------===//
224 // Mips ISA/ASE membership and instruction group membership adjectives.
225 // They are mutually exclusive.
226 //===----------------------------------------------------------------------===//
228 // FIXME: I'd prefer to use additive predicates to build the instruction sets
229 // but we are short on assembler feature bits at the moment. Using a
230 // subtractive predicate will hopefully keep us under the 32 predicate
231 // limit long enough to develop an alternative way to handle P1||P2
233 class ISA_MIPS1_NOT_4_32 {
234 list<Predicate> InsnPredicates = [NotMips4_32];
236 class ISA_MIPS1_NOT_32R6_64R6 {
237 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
239 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
240 class ISA_MIPS2_NOT_32R6_64R6 {
241 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
243 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
244 class ISA_MIPS3_NOT_32R6_64R6 {
245 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
247 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
248 class ISA_MIPS32_NOT_32R6_64R6 {
249 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
251 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
252 class ISA_MIPS32R2_NOT_32R6_64R6 {
253 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
255 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
256 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
257 class ISA_MIPS64_NOT_64R6 {
258 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
260 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
261 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
262 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
263 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
264 class ISA_MICROMIPS32R6 {
265 list<Predicate> InsnPredicates = [HasMicroMips32r6];
267 class ISA_MICROMIPS64R6 {
268 list<Predicate> InsnPredicates = [HasMicroMips64r6];
270 class ISA_MICROMIPS32_NOT_MIPS32R6 {
271 list<Predicate> InsnPredicates = [InMicroMips, NotMips32r6];
274 class INSN_EVA { list<Predicate> InsnPredicates = [HasEVA]; }
275 class INSN_EVA_NOT_32R6_64R6 {
276 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6, HasEVA];
279 // The portions of MIPS-III that were also added to MIPS32
280 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
282 // The portions of MIPS-III that were also added to MIPS32 but were removed in
283 // MIPS32r6 and MIPS64r6.
284 class INSN_MIPS3_32_NOT_32R6_64R6 {
285 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
288 // The portions of MIPS-III that were also added to MIPS32
289 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
291 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
292 // MIPS32r6 and MIPS64r6.
293 class INSN_MIPS4_32_NOT_32R6_64R6 {
294 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
297 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
298 // MIPS32r6 and MIPS64r6.
299 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
300 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
303 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
304 // MIPS32r6 and MIPS64r6.
305 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
306 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
310 list<Predicate> InsnPredicates = [HasMSA];
314 list<Predicate> InsnPredicates = [HasMSA, HasMips64];
317 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
318 // It can be used only on instructions that doesn't inherit PredicateControl.
319 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
320 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
323 //===----------------------------------------------------------------------===//
325 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
326 let EncodingPredicates = [HasStdEnc];
329 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
330 InstAlias<Asm, Result, Emit>, PredicateControl;
333 bit isCommutable = 1;
350 bit isTerminator = 1;
353 bit hasExtraSrcRegAllocReq = 1;
354 bit isCodeGenOnly = 1;
357 class IsAsCheapAsAMove {
358 bit isAsCheapAsAMove = 1;
361 class NeverHasSideEffects {
362 bit hasSideEffects = 0;
365 //===----------------------------------------------------------------------===//
366 // Instruction format superclass
367 //===----------------------------------------------------------------------===//
369 include "MipsInstrFormats.td"
371 //===----------------------------------------------------------------------===//
372 // Mips Operand, Complex Patterns and Transformations Definitions.
373 //===----------------------------------------------------------------------===//
375 def MipsJumpTargetAsmOperand : AsmOperandClass {
376 let Name = "JumpTarget";
377 let ParserMethod = "parseJumpTarget";
378 let PredicateMethod = "isImm";
379 let RenderMethod = "addImmOperands";
382 // Instruction operand types
383 def jmptarget : Operand<OtherVT> {
384 let EncoderMethod = "getJumpTargetOpValue";
385 let ParserMatchClass = MipsJumpTargetAsmOperand;
387 def brtarget : Operand<OtherVT> {
388 let EncoderMethod = "getBranchTargetOpValue";
389 let OperandType = "OPERAND_PCREL";
390 let DecoderMethod = "DecodeBranchTarget";
391 let ParserMatchClass = MipsJumpTargetAsmOperand;
393 def calltarget : Operand<iPTR> {
394 let EncoderMethod = "getJumpTargetOpValue";
395 let ParserMatchClass = MipsJumpTargetAsmOperand;
398 def imm64: Operand<i64>;
400 def simm9 : Operand<i32>;
401 def simm10 : Operand<i32>;
402 def simm11 : Operand<i32>;
404 def simm16 : Operand<i32> {
405 let DecoderMethod= "DecodeSimm16";
408 def simm19_lsl2 : Operand<i32> {
409 let EncoderMethod = "getSimm19Lsl2Encoding";
410 let DecoderMethod = "DecodeSimm19Lsl2";
411 let ParserMatchClass = MipsJumpTargetAsmOperand;
414 def simm18_lsl3 : Operand<i32> {
415 let EncoderMethod = "getSimm18Lsl3Encoding";
416 let DecoderMethod = "DecodeSimm18Lsl3";
417 let ParserMatchClass = MipsJumpTargetAsmOperand;
420 def simm20 : Operand<i32> {
423 def uimm20 : Operand<i32> {
426 def MipsUImm10AsmOperand : AsmOperandClass {
428 let RenderMethod = "addImmOperands";
429 let ParserMethod = "parseImm";
430 let PredicateMethod = "isUImm<10>";
433 def uimm10 : Operand<i32> {
434 let ParserMatchClass = MipsUImm10AsmOperand;
437 def simm16_64 : Operand<i64> {
438 let DecoderMethod = "DecodeSimm16";
442 def uimmz : Operand<i32> {
443 let PrintMethod = "printUnsignedImm";
447 def uimm2 : Operand<i32> {
448 let PrintMethod = "printUnsignedImm";
451 def uimm3 : Operand<i32> {
452 let PrintMethod = "printUnsignedImm";
455 def uimm5 : Operand<i32> {
456 let PrintMethod = "printUnsignedImm";
459 def uimm6 : Operand<i32> {
460 let PrintMethod = "printUnsignedImm";
463 def uimm16 : Operand<i32> {
464 let PrintMethod = "printUnsignedImm";
467 def pcrel16 : Operand<i32> {
470 def MipsMemAsmOperand : AsmOperandClass {
472 let ParserMethod = "parseMemOperand";
475 def MipsMemSimm9AsmOperand : AsmOperandClass {
476 let Name = "MemOffsetSimm9";
477 let SuperClasses = [MipsMemAsmOperand];
478 let RenderMethod = "addMemOperands";
479 let ParserMethod = "parseMemOperand";
480 let PredicateMethod = "isMemWithSimmOffset<9>";
483 def MipsMemSimm9GPRAsmOperand : AsmOperandClass {
484 let Name = "MemOffsetSimm9GPR";
485 let SuperClasses = [MipsMemAsmOperand];
486 let RenderMethod = "addMemOperands";
487 let ParserMethod = "parseMemOperand";
488 let PredicateMethod = "isMemWithSimmOffsetGPR<9>";
491 def MipsMemSimm11AsmOperand : AsmOperandClass {
492 let Name = "MemOffsetSimm11";
493 let SuperClasses = [MipsMemAsmOperand];
494 let RenderMethod = "addMemOperands";
495 let ParserMethod = "parseMemOperand";
496 let PredicateMethod = "isMemWithSimmOffset<11>";
499 def MipsMemSimm16AsmOperand : AsmOperandClass {
500 let Name = "MemOffsetSimm16";
501 let SuperClasses = [MipsMemAsmOperand];
502 let RenderMethod = "addMemOperands";
503 let ParserMethod = "parseMemOperand";
504 let PredicateMethod = "isMemWithSimmOffset<16>";
507 def MipsInvertedImmoperand : AsmOperandClass {
509 let RenderMethod = "addImmOperands";
510 let ParserMethod = "parseInvNum";
513 def InvertedImOperand : Operand<i32> {
514 let ParserMatchClass = MipsInvertedImmoperand;
517 def InvertedImOperand64 : Operand<i64> {
518 let ParserMatchClass = MipsInvertedImmoperand;
521 class mem_generic : Operand<iPTR> {
522 let PrintMethod = "printMemOperand";
523 let MIOperandInfo = (ops ptr_rc, simm16);
524 let EncoderMethod = "getMemEncoding";
525 let ParserMatchClass = MipsMemAsmOperand;
526 let OperandType = "OPERAND_MEMORY";
530 def mem : mem_generic;
532 // MSA specific address operand
533 def mem_msa : mem_generic {
534 let MIOperandInfo = (ops ptr_rc, simm10);
535 let EncoderMethod = "getMSAMemEncoding";
538 def mem_simm9 : mem_generic {
539 let MIOperandInfo = (ops ptr_rc, simm9);
540 let EncoderMethod = "getMemEncoding";
541 let ParserMatchClass = MipsMemSimm9AsmOperand;
544 def mem_simm9gpr : mem_generic {
545 let MIOperandInfo = (ops ptr_rc, simm9);
546 let EncoderMethod = "getMemEncoding";
547 let ParserMatchClass = MipsMemSimm9GPRAsmOperand;
550 def mem_simm11 : mem_generic {
551 let MIOperandInfo = (ops ptr_rc, simm11);
552 let EncoderMethod = "getMemEncoding";
553 let ParserMatchClass = MipsMemSimm11AsmOperand;
556 def mem_simm16 : mem_generic {
557 let MIOperandInfo = (ops ptr_rc, simm16);
558 let EncoderMethod = "getMemEncoding";
559 let ParserMatchClass = MipsMemSimm16AsmOperand;
562 def mem_ea : Operand<iPTR> {
563 let PrintMethod = "printMemOperandEA";
564 let MIOperandInfo = (ops ptr_rc, simm16);
565 let EncoderMethod = "getMemEncoding";
566 let OperandType = "OPERAND_MEMORY";
569 def PtrRC : Operand<iPTR> {
570 let MIOperandInfo = (ops ptr_rc);
571 let DecoderMethod = "DecodePtrRegisterClass";
572 let ParserMatchClass = GPR32AsmOperand;
575 // size operand of ext instruction
576 def size_ext : Operand<i32> {
577 let EncoderMethod = "getSizeExtEncoding";
578 let DecoderMethod = "DecodeExtSize";
581 // size operand of ins instruction
582 def size_ins : Operand<i32> {
583 let EncoderMethod = "getSizeInsEncoding";
584 let DecoderMethod = "DecodeInsSize";
587 // Transformation Function - get the lower 16 bits.
588 def LO16 : SDNodeXForm<imm, [{
589 return getImm(N, N->getZExtValue() & 0xFFFF);
592 // Transformation Function - get the higher 16 bits.
593 def HI16 : SDNodeXForm<imm, [{
594 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
598 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
600 // Node immediate is zero (e.g. insve.d)
601 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
603 // Node immediate fits as 16-bit sign extended on target immediate.
605 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
607 // Node immediate fits as 16-bit sign extended on target immediate.
609 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
611 // Node immediate fits as 15-bit sign extended on target immediate.
613 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
615 // Node immediate fits as 16-bit zero extended on target immediate.
616 // The LO16 param means that only the lower 16 bits of the node
617 // immediate are caught.
619 def immZExt16 : PatLeaf<(imm), [{
620 if (N->getValueType(0) == MVT::i32)
621 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
623 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
626 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
627 def immLow16Zero : PatLeaf<(imm), [{
628 int64_t Val = N->getSExtValue();
629 return isInt<32>(Val) && !(Val & 0xffff);
632 // shamt field must fit in 5 bits.
633 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
635 // True if (N + 1) fits in 16-bit field.
636 def immSExt16Plus1 : PatLeaf<(imm), [{
637 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
640 // Mips Address Mode! SDNode frameindex could possibily be a match
641 // since load and store instructions from stack used it.
643 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
646 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
649 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
652 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
654 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
656 //===----------------------------------------------------------------------===//
657 // Instructions specific format
658 //===----------------------------------------------------------------------===//
660 // Arithmetic and logical instructions with 3 register operands.
661 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
662 InstrItinClass Itin = NoItinerary,
663 SDPatternOperator OpNode = null_frag>:
664 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
665 !strconcat(opstr, "\t$rd, $rs, $rt"),
666 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
667 let isCommutable = isComm;
668 let isReMaterializable = 1;
669 let TwoOperandAliasConstraint = "$rd = $rs";
672 // Arithmetic and logical instructions with 2 register operands.
673 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
674 InstrItinClass Itin = NoItinerary,
675 SDPatternOperator imm_type = null_frag,
676 SDPatternOperator OpNode = null_frag> :
677 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
678 !strconcat(opstr, "\t$rt, $rs, $imm16"),
679 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
681 let isReMaterializable = 1;
682 let TwoOperandAliasConstraint = "$rs = $rt";
685 // Arithmetic Multiply ADD/SUB
686 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
687 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
688 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
689 let Defs = [HI0, LO0];
690 let Uses = [HI0, LO0];
691 let isCommutable = isComm;
695 class LogicNOR<string opstr, RegisterOperand RO>:
696 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
697 !strconcat(opstr, "\t$rd, $rs, $rt"),
698 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
699 let isCommutable = 1;
703 class shift_rotate_imm<string opstr, Operand ImmOpnd,
704 RegisterOperand RO, InstrItinClass itin,
705 SDPatternOperator OpNode = null_frag,
706 SDPatternOperator PF = null_frag> :
707 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
708 !strconcat(opstr, "\t$rd, $rt, $shamt"),
709 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
710 let TwoOperandAliasConstraint = "$rt = $rd";
713 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
714 SDPatternOperator OpNode = null_frag>:
715 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
716 !strconcat(opstr, "\t$rd, $rt, $rs"),
717 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
720 // Load Upper Immediate
721 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
722 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
723 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
724 let hasSideEffects = 0;
725 let isReMaterializable = 1;
729 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
730 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
731 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
732 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
733 let DecoderMethod = "DecodeMem";
734 let canFoldAsLoad = 1;
738 class StoreMemory<string opstr, DAGOperand RO, DAGOperand MO,
739 SDPatternOperator OpNode = null_frag,
740 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
741 InstSE<(outs), (ins RO:$rt, MO:$addr), !strconcat(opstr, "\t$rt, $addr"),
742 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
743 let DecoderMethod = "DecodeMem";
747 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
748 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
749 StoreMemory<opstr, RO, mem, OpNode, Itin, Addr>;
751 // Load/Store Left/Right
752 let canFoldAsLoad = 1 in
753 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
754 InstrItinClass Itin> :
755 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
756 !strconcat(opstr, "\t$rt, $addr"),
757 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
758 let DecoderMethod = "DecodeMem";
759 string Constraints = "$src = $rt";
762 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
763 InstrItinClass Itin> :
764 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
765 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
766 let DecoderMethod = "DecodeMem";
770 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
771 SDPatternOperator OpNode= null_frag> :
772 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
773 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
774 let DecoderMethod = "DecodeFMem2";
778 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
779 SDPatternOperator OpNode= null_frag> :
780 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
781 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
782 let DecoderMethod = "DecodeFMem2";
787 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
788 SDPatternOperator OpNode= null_frag> :
789 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
790 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
791 let DecoderMethod = "DecodeFMem3";
795 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
796 SDPatternOperator OpNode= null_frag> :
797 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
798 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
799 let DecoderMethod = "DecodeFMem3";
803 // Conditional Branch
804 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
805 RegisterOperand RO, bit DelaySlot = 1> :
806 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
807 !strconcat(opstr, "\t$rs, $rt, $offset"),
808 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], II_BCC,
811 let isTerminator = 1;
812 let hasDelaySlot = DelaySlot;
816 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
817 RegisterOperand RO, bit DelaySlot = 1> :
818 InstSE<(outs), (ins RO:$rs, opnd:$offset),
819 !strconcat(opstr, "\t$rs, $offset"),
820 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], II_BCCZ,
823 let isTerminator = 1;
824 let hasDelaySlot = DelaySlot;
829 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
830 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
831 !strconcat(opstr, "\t$rd, $rs, $rt"),
832 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
833 II_SLT_SLTU, FrmR, opstr>;
835 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
837 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
838 !strconcat(opstr, "\t$rt, $rs, $imm16"),
839 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
840 II_SLTI_SLTIU, FrmI, opstr>;
843 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
844 SDPatternOperator targetoperator, string bopstr> :
845 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
846 [(operator targetoperator:$target)], II_J, FrmJ, bopstr> {
849 let hasDelaySlot = 1;
850 let DecoderMethod = "DecodeJumpTarget";
854 // Unconditional branch
855 class UncondBranch<Instruction BEQInst> :
856 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], II_B>,
857 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
859 let isTerminator = 1;
861 let hasDelaySlot = 1;
862 let AdditionalPredicates = [RelocPIC];
866 // Base class for indirect branch and return instruction classes.
867 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
868 class JumpFR<string opstr, RegisterOperand RO,
869 SDPatternOperator operator = null_frag>:
870 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], II_JR,
874 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
876 let isIndirectBranch = 1;
879 // Jump and Link (Call)
880 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
881 class JumpLink<string opstr, DAGOperand opnd> :
882 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
883 [(MipsJmpLink imm:$target)], II_JAL, FrmJ, opstr> {
884 let DecoderMethod = "DecodeJumpTarget";
887 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
888 Register RetReg, RegisterOperand ResRO = RO>:
889 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], II_JALR>,
890 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
892 class JumpLinkReg<string opstr, RegisterOperand RO>:
893 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
894 [], II_JALR, FrmR, opstr>;
896 class BGEZAL_FT<string opstr, DAGOperand opnd,
897 RegisterOperand RO, bit DelaySlot = 1> :
898 InstSE<(outs), (ins RO:$rs, opnd:$offset),
899 !strconcat(opstr, "\t$rs, $offset"), [], II_BCCZAL, FrmI, opstr> {
900 let hasDelaySlot = DelaySlot;
905 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
906 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
907 class TailCall<Instruction JumpInst> :
908 PseudoSE<(outs), (ins calltarget:$target), [], II_J>,
909 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
911 class TailCallReg<RegisterOperand RO, Instruction JRInst,
912 RegisterOperand ResRO = RO> :
913 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], II_JR>,
914 PseudoInstExpansion<(JRInst ResRO:$rs)>;
917 class BAL_BR_Pseudo<Instruction RealInst> :
918 PseudoSE<(outs), (ins brtarget:$offset), [], II_BCCZAL>,
919 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
921 let isTerminator = 1;
923 let hasDelaySlot = 1;
928 class SYS_FT<string opstr> :
929 InstSE<(outs), (ins uimm20:$code_),
930 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
932 class BRK_FT<string opstr> :
933 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
934 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
938 class ER_FT<string opstr> :
939 InstSE<(outs), (ins),
940 opstr, [], NoItinerary, FrmOther, opstr>;
943 class DEI_FT<string opstr, RegisterOperand RO> :
944 InstSE<(outs RO:$rt), (ins),
945 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
948 class WAIT_FT<string opstr> :
949 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
952 let hasSideEffects = 1 in
953 class SYNC_FT<string opstr> :
954 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
955 NoItinerary, FrmOther, opstr>;
957 class SYNCI_FT<string opstr> :
958 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
959 NoItinerary, FrmOther, opstr> {
960 let hasSideEffects = 1;
961 let DecoderMethod = "DecodeSyncI";
964 let hasSideEffects = 1 in
965 class TEQ_FT<string opstr, RegisterOperand RO> :
966 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
967 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
970 class TEQI_FT<string opstr, RegisterOperand RO> :
971 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
972 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
974 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
975 list<Register> DefRegs> :
976 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
978 let isCommutable = 1;
980 let hasSideEffects = 0;
983 // Pseudo multiply/divide instruction with explicit accumulator register
985 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
986 SDPatternOperator OpNode, InstrItinClass Itin,
987 bit IsComm = 1, bit HasSideEffects = 0,
988 bit UsesCustomInserter = 0> :
989 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
990 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
991 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
992 let isCommutable = IsComm;
993 let hasSideEffects = HasSideEffects;
994 let usesCustomInserter = UsesCustomInserter;
997 // Pseudo multiply add/sub instruction with explicit accumulator register
999 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
1000 InstrItinClass itin>
1001 : PseudoSE<(outs ACC64:$ac),
1002 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
1004 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
1006 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
1007 string Constraints = "$acin = $ac";
1010 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
1011 list<Register> DefRegs> :
1012 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
1013 [], itin, FrmR, opstr> {
1018 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
1019 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
1020 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
1022 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
1023 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
1025 let Uses = [UseReg];
1026 let hasSideEffects = 0;
1029 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
1030 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
1031 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
1034 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1035 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
1038 let hasSideEffects = 0;
1041 class EffectiveAddress<string opstr, RegisterOperand RO> :
1042 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1043 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1044 !strconcat(opstr, "_lea")> {
1045 let isCodeGenOnly = 1;
1046 let DecoderMethod = "DecodeMem";
1049 // Count Leading Ones/Zeros in Word
1050 class CountLeading0<string opstr, RegisterOperand RO>:
1051 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1052 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1054 class CountLeading1<string opstr, RegisterOperand RO>:
1055 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1056 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1058 // Sign Extend in Register.
1059 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1060 InstrItinClass itin> :
1061 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1062 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1065 class SubwordSwap<string opstr, RegisterOperand RO,
1066 InstrItinClass itin = NoItinerary>:
1067 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [], itin,
1069 let hasSideEffects = 0;
1073 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1074 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1075 II_RDHWR, FrmR, "rdhwr">;
1078 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1079 SDPatternOperator Op = null_frag>:
1080 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1081 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1082 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1083 FrmR, opstr>, ISA_MIPS32R2;
1085 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1086 SDPatternOperator Op = null_frag>:
1087 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1088 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1089 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1090 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1091 let Constraints = "$src = $rt";
1094 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1095 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1096 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1097 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1099 // Atomic Compare & Swap.
1100 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1101 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1102 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1104 class LLBase<string opstr, RegisterOperand RO> :
1105 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1106 [], NoItinerary, FrmI> {
1107 let DecoderMethod = "DecodeMem";
1111 class SCBase<string opstr, RegisterOperand RO> :
1112 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1113 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1114 let DecoderMethod = "DecodeMem";
1116 let Constraints = "$rt = $dst";
1119 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1120 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1121 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1123 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1124 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1125 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1127 class TrapBase<Instruction RealInst>
1128 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1129 PseudoInstExpansion<(RealInst 0, 0)> {
1131 let isTerminator = 1;
1132 let isCodeGenOnly = 1;
1135 //===----------------------------------------------------------------------===//
1136 // Pseudo instructions
1137 //===----------------------------------------------------------------------===//
1140 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1141 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1143 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1144 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1145 [(callseq_start timm:$amt)]>;
1146 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1147 [(callseq_end timm:$amt1, timm:$amt2)]>;
1150 let usesCustomInserter = 1 in {
1151 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1152 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1153 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1154 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1155 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1156 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1157 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1158 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1159 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1160 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1161 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1162 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1163 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1164 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1165 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1166 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1167 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1168 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1170 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1171 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1172 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1174 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1175 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1176 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1179 /// Pseudo instructions for loading and storing accumulator registers.
1180 let isPseudo = 1, isCodeGenOnly = 1 in {
1181 def LOAD_ACC64 : Load<"", ACC64>;
1182 def STORE_ACC64 : Store<"", ACC64>;
1185 // We need these two pseudo instructions to avoid offset calculation for long
1186 // branches. See the comment in file MipsLongBranch.cpp for detailed
1189 // Expands to: lui $dst, %hi($tgt - $baltgt)
1190 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1191 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1193 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1194 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1195 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1197 //===----------------------------------------------------------------------===//
1198 // Instruction definition
1199 //===----------------------------------------------------------------------===//
1200 //===----------------------------------------------------------------------===//
1201 // MipsI Instructions
1202 //===----------------------------------------------------------------------===//
1204 /// Arithmetic Instructions (ALU Immediate)
1205 let AdditionalPredicates = [NotInMicroMips] in {
1206 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1207 II_ADDIU, immSExt16, add>,
1208 ADDI_FM<0x9>, IsAsCheapAsAMove;
1210 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1211 ISA_MIPS1_NOT_32R6_64R6;
1212 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1214 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1216 let AdditionalPredicates = [NotInMicroMips] in {
1217 def ANDi : MMRel, StdMMR6Rel,
1218 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1221 def ORi : MMRel, StdMMR6Rel,
1222 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1224 def XORi : MMRel, StdMMR6Rel,
1225 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1227 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1228 let AdditionalPredicates = [NotInMicroMips] in {
1229 /// Arithmetic Instructions (3-Operand, R-Type)
1230 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1232 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1235 let Defs = [HI0, LO0] in
1236 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1237 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1238 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1239 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1240 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1241 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1242 let AdditionalPredicates = [NotInMicroMips] in {
1243 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1245 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1247 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1250 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1252 /// Shift Instructions
1253 let AdditionalPredicates = [NotInMicroMips] in {
1254 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1255 immZExt5>, SRA_FM<0, 0>;
1256 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1257 immZExt5>, SRA_FM<2, 0>;
1259 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1260 immZExt5>, SRA_FM<3, 0>;
1261 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1263 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1265 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1268 // Rotate Instructions
1269 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1271 SRA_FM<2, 1>, ISA_MIPS32R2;
1272 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1273 SRLV_FM<6, 1>, ISA_MIPS32R2;
1275 /// Load and Store Instructions
1277 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1278 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1280 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1282 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1283 let AdditionalPredicates = [NotInMicroMips] in {
1284 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1287 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
1289 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1290 let AdditionalPredicates = [NotInMicroMips] in {
1291 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1294 /// load/store left/right
1295 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1296 AdditionalPredicates = [NotInMicroMips] in {
1297 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1298 ISA_MIPS1_NOT_32R6_64R6;
1299 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1300 ISA_MIPS1_NOT_32R6_64R6;
1301 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1302 ISA_MIPS1_NOT_32R6_64R6;
1303 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1304 ISA_MIPS1_NOT_32R6_64R6;
1307 let AdditionalPredicates = [NotInMicroMips] in {
1308 // COP2 Memory Instructions
1309 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1310 ISA_MIPS1_NOT_32R6_64R6;
1311 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1312 ISA_MIPS1_NOT_32R6_64R6;
1313 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1314 ISA_MIPS2_NOT_32R6_64R6;
1315 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1316 ISA_MIPS2_NOT_32R6_64R6;
1318 // COP3 Memory Instructions
1319 let DecoderNamespace = "COP3_" in {
1320 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1321 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1322 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1324 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1329 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1330 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1332 let AdditionalPredicates = [NotInMicroMips] in {
1333 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1334 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1335 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1336 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1337 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1338 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1341 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1342 ISA_MIPS2_NOT_32R6_64R6;
1343 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1344 ISA_MIPS2_NOT_32R6_64R6;
1345 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1346 ISA_MIPS2_NOT_32R6_64R6;
1347 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1348 ISA_MIPS2_NOT_32R6_64R6;
1349 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1350 ISA_MIPS2_NOT_32R6_64R6;
1351 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1352 ISA_MIPS2_NOT_32R6_64R6;
1354 let AdditionalPredicates = [NotInMicroMips] in {
1355 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1357 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1358 def TRAP : TrapBase<BREAK>;
1359 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1361 let AdditionalPredicates = [NotInMicroMips] in {
1362 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
1363 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
1365 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
1367 let AdditionalPredicates = [NotInMicroMips] in {
1368 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1370 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1372 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1373 AdditionalPredicates = [NotInMicroMips] in {
1374 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1376 /// Load-linked, Store-conditional
1377 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1378 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1381 /// Jump and Branch Instructions
1382 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1383 AdditionalRequires<[RelocStatic]>, IsBranch;
1384 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1385 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1386 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1387 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1388 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1389 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1390 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1391 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1393 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1394 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1395 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1397 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1398 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1399 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1401 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1402 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1403 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1405 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1406 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1407 def B : UncondBranch<BEQ>;
1409 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1410 let AdditionalPredicates = [NotInMicroMips] in {
1411 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1412 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1415 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1416 ISA_MIPS32_NOT_32R6_64R6;
1417 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1418 ISA_MIPS1_NOT_32R6_64R6;
1419 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1420 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1421 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1422 ISA_MIPS1_NOT_32R6_64R6;
1423 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1424 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1425 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1426 def TAILCALL : TailCall<J>;
1427 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1429 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1430 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1431 class PseudoIndirectBranchBase<RegisterOperand RO> :
1432 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)],
1433 II_IndirectBranchPseudo> {
1436 let hasDelaySlot = 1;
1438 let isIndirectBranch = 1;
1441 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1443 // Return instructions are matched as a RetRA instruction, then are expanded
1444 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1445 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1447 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1448 [], II_ReturnPseudo> {
1449 let isTerminator = 1;
1451 let hasDelaySlot = 1;
1453 let isCodeGenOnly = 1;
1455 let hasExtraSrcRegAllocReq = 1;
1458 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1460 // Exception handling related node and instructions.
1461 // The conversion sequence is:
1462 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1463 // MIPSeh_return -> (stack change + indirect branch)
1465 // MIPSeh_return takes the place of regular return instruction
1466 // but takes two arguments (V1, V0) which are used for storing
1467 // the offset and return address respectively.
1468 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1470 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1471 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1473 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1474 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1475 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1476 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1478 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1481 /// Multiply and Divide Instructions.
1482 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1483 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1484 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1485 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1486 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1487 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1488 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1489 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1491 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1492 ISA_MIPS1_NOT_32R6_64R6;
1493 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1494 ISA_MIPS1_NOT_32R6_64R6;
1495 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1496 AdditionalPredicates = [NotInMicroMips] in {
1497 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1498 ISA_MIPS1_NOT_32R6_64R6;
1499 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1500 ISA_MIPS1_NOT_32R6_64R6;
1503 /// Sign Ext In Register Instructions.
1504 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1505 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1506 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1507 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1510 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1511 ISA_MIPS32_NOT_32R6_64R6;
1512 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1513 ISA_MIPS32_NOT_32R6_64R6;
1515 let AdditionalPredicates = [NotInMicroMips] in {
1516 /// Word Swap Bytes Within Halfwords
1517 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd, II_WSBH>, SEB_FM<2, 0x20>,
1522 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1524 // FrameIndexes are legalized when they are operands from load/store
1525 // instructions. The same not happens for stack address copies, so an
1526 // add op with mem ComplexPattern is used and the stack address copy
1527 // can be matched. It's similar to Sparc LEA_ADDRi
1528 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1531 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1532 ISA_MIPS32_NOT_32R6_64R6;
1533 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1534 ISA_MIPS32_NOT_32R6_64R6;
1535 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1536 ISA_MIPS32_NOT_32R6_64R6;
1537 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1538 ISA_MIPS32_NOT_32R6_64R6;
1540 let AdditionalPredicates = [NotDSP] in {
1541 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1542 ISA_MIPS1_NOT_32R6_64R6;
1543 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1544 ISA_MIPS1_NOT_32R6_64R6;
1545 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1546 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1547 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1548 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1549 ISA_MIPS32_NOT_32R6_64R6;
1550 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1551 ISA_MIPS32_NOT_32R6_64R6;
1552 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1553 ISA_MIPS32_NOT_32R6_64R6;
1554 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1555 ISA_MIPS32_NOT_32R6_64R6;
1558 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1559 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1560 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1561 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1563 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1565 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1566 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1568 /// Move Control Registers From/To CPU Registers
1569 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1570 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1571 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1572 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1574 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1576 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1577 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1578 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1580 // JR_HB and JALR_HB are defined here using the new style naming
1581 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1582 // and because of that it doesn't follow the naming convention of the
1583 // rest of the file. To avoid a mixture of old vs new style, the new
1584 // style was chosen.
1585 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1586 dag OutOperandList = (outs);
1587 dag InOperandList = (ins GPROpnd:$rs);
1588 string AsmString = !strconcat(instr_asm, "\t$rs");
1589 list<dag> Pattern = [];
1592 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1593 dag OutOperandList = (outs GPROpnd:$rd);
1594 dag InOperandList = (ins GPROpnd:$rs);
1595 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1596 list<dag> Pattern = [];
1599 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1600 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1602 let isIndirectBranch=1;
1608 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1609 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1610 let isIndirectBranch=1;
1614 class JR_HB_ENC : JR_HB_FM<8>;
1615 class JALR_HB_ENC : JALR_HB_FM<9>;
1617 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1618 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1620 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1622 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1623 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1624 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1625 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1627 class CacheOp<string instr_asm, Operand MemOpnd> :
1628 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1629 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1631 let DecoderMethod = "DecodeCacheOp";
1634 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1635 INSN_MIPS3_32_NOT_32R6_64R6;
1636 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1637 INSN_MIPS3_32_NOT_32R6_64R6;
1639 //===----------------------------------------------------------------------===//
1640 // Instruction aliases
1641 //===----------------------------------------------------------------------===//
1642 def : MipsInstAlias<"move $dst, $src",
1643 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1645 let AdditionalPredicates = [NotInMicroMips];
1647 def : MipsInstAlias<"move $dst, $src",
1648 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1650 let AdditionalPredicates = [NotInMicroMips];
1652 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1653 ISA_MIPS1_NOT_32R6_64R6;
1654 def : MipsInstAlias<"addu $rs, $rt, $imm",
1655 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1656 def : MipsInstAlias<"addu $rs, $imm",
1657 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1658 def : MipsInstAlias<"add $rs, $rt, $imm",
1659 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1660 ISA_MIPS1_NOT_32R6_64R6;
1661 def : MipsInstAlias<"add $rs, $imm",
1662 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1663 ISA_MIPS1_NOT_32R6_64R6;
1664 def : MipsInstAlias<"and $rs, $rt, $imm",
1665 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1666 def : MipsInstAlias<"and $rs, $imm",
1667 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1668 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1669 let Predicates = [NotInMicroMips] in {
1670 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1672 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1673 def : MipsInstAlias<"not $rt, $rs",
1674 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1675 def : MipsInstAlias<"neg $rt, $rs",
1676 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1677 def : MipsInstAlias<"negu $rt",
1678 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1679 def : MipsInstAlias<"negu $rt, $rs",
1680 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1681 def : MipsInstAlias<"slt $rs, $rt, $imm",
1682 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1683 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1684 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1685 def : MipsInstAlias<"xor $rs, $rt, $imm",
1686 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1687 def : MipsInstAlias<"xor $rs, $imm",
1688 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1689 def : MipsInstAlias<"or $rs, $rt, $imm",
1690 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1691 def : MipsInstAlias<"or $rs, $imm",
1692 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1693 let AdditionalPredicates = [NotInMicroMips] in {
1694 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1696 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1697 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1698 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1699 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1700 let AdditionalPredicates = [NotInMicroMips] in {
1701 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1703 def : MipsInstAlias<"bnez $rs,$offset",
1704 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1705 def : MipsInstAlias<"bnezl $rs,$offset",
1706 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1707 def : MipsInstAlias<"beqz $rs,$offset",
1708 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1709 def : MipsInstAlias<"beqzl $rs,$offset",
1710 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1711 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1713 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1714 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1715 let AdditionalPredicates = [NotInMicroMips] in {
1716 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1718 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1719 let AdditionalPredicates = [NotInMicroMips] in {
1720 def : MipsInstAlias<"teq $rs, $rt",
1721 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1722 def : MipsInstAlias<"tge $rs, $rt",
1723 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1724 def : MipsInstAlias<"tgeu $rs, $rt",
1725 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1726 def : MipsInstAlias<"tlt $rs, $rt",
1727 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1728 def : MipsInstAlias<"tltu $rs, $rt",
1729 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1730 def : MipsInstAlias<"tne $rs, $rt",
1731 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1733 def : MipsInstAlias<"sll $rd, $rt, $rs",
1734 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1735 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1736 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1737 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1738 def : MipsInstAlias<"sub $rs, $imm",
1739 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1740 0>, ISA_MIPS1_NOT_32R6_64R6;
1741 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1742 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1743 InvertedImOperand:$imm), 0>;
1744 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1745 InvertedImOperand:$imm), 0>;
1746 def : MipsInstAlias<"sra $rd, $rt, $rs",
1747 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1748 def : MipsInstAlias<"srl $rd, $rt, $rs",
1749 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1750 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1751 def : MipsInstAlias<"sync",
1752 (SYNC 0), 1>, ISA_MIPS2;
1753 //===----------------------------------------------------------------------===//
1754 // Assembler Pseudo Instructions
1755 //===----------------------------------------------------------------------===//
1757 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1758 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1759 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1760 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1762 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1763 RegisterOperand RO> :
1764 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1765 !strconcat(instr_asm, "\t$rt, $addr")> ;
1766 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1768 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1769 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1770 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1771 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1773 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1775 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1778 def NORImm : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm),
1779 "nor\t$rs, $rt, $imm"> ;
1781 let hasDelaySlot = 1 in {
1782 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1783 (ins imm64:$imm64, brtarget:$offset),
1784 "bne\t$rt, $imm64, $offset">;
1785 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1786 (ins imm64:$imm64, brtarget:$offset),
1787 "beq\t$rt, $imm64, $offset">;
1789 class CondBranchPseudo<string instr_asm> :
1790 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1792 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1795 def BLT : CondBranchPseudo<"blt">;
1796 def BLE : CondBranchPseudo<"ble">;
1797 def BGE : CondBranchPseudo<"bge">;
1798 def BGT : CondBranchPseudo<"bgt">;
1799 def BLTU : CondBranchPseudo<"bltu">;
1800 def BLEU : CondBranchPseudo<"bleu">;
1801 def BGEU : CondBranchPseudo<"bgeu">;
1802 def BGTU : CondBranchPseudo<"bgtu">;
1803 def BLTL : CondBranchPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1804 def BLEL : CondBranchPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1805 def BGEL : CondBranchPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1806 def BGTL : CondBranchPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1807 def BLTUL: CondBranchPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1808 def BLEUL: CondBranchPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1809 def BGEUL: CondBranchPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1810 def BGTUL: CondBranchPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1812 class CondBranchImmPseudo<string instr_asm> :
1813 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, imm64:$imm, brtarget:$offset),
1814 !strconcat(instr_asm, "\t$rs, $imm, $offset")>;
1816 def BLTImmMacro : CondBranchImmPseudo<"blt">;
1817 def BLEImmMacro : CondBranchImmPseudo<"ble">;
1818 def BGEImmMacro : CondBranchImmPseudo<"bge">;
1819 def BGTImmMacro : CondBranchImmPseudo<"bgt">;
1820 def BLTUImmMacro : CondBranchImmPseudo<"bltu">;
1821 def BLEUImmMacro : CondBranchImmPseudo<"bleu">;
1822 def BGEUImmMacro : CondBranchImmPseudo<"bgeu">;
1823 def BGTUImmMacro : CondBranchImmPseudo<"bgtu">;
1824 def BLTLImmMacro : CondBranchImmPseudo<"bltl">, ISA_MIPS2_NOT_32R6_64R6;
1825 def BLELImmMacro : CondBranchImmPseudo<"blel">, ISA_MIPS2_NOT_32R6_64R6;
1826 def BGELImmMacro : CondBranchImmPseudo<"bgel">, ISA_MIPS2_NOT_32R6_64R6;
1827 def BGTLImmMacro : CondBranchImmPseudo<"bgtl">, ISA_MIPS2_NOT_32R6_64R6;
1828 def BLTULImmMacro : CondBranchImmPseudo<"bltul">, ISA_MIPS2_NOT_32R6_64R6;
1829 def BLEULImmMacro : CondBranchImmPseudo<"bleul">, ISA_MIPS2_NOT_32R6_64R6;
1830 def BGEULImmMacro : CondBranchImmPseudo<"bgeul">, ISA_MIPS2_NOT_32R6_64R6;
1831 def BGTULImmMacro : CondBranchImmPseudo<"bgtul">, ISA_MIPS2_NOT_32R6_64R6;
1833 // FIXME: Predicates are removed because instructions are matched regardless of
1834 // predicates, because PredicateControl was not in the hierarchy. This was
1835 // done to emit more precise error message from expansion function.
1836 // Once the tablegen-erated errors are made better, this needs to be fixed and
1837 // predicates needs to be restored.
1839 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1840 "div\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1842 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1843 "divu\t$rs, $rt">; //, ISA_MIPS1_NOT_32R6_64R6;
1845 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1846 "ddiv\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1848 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1849 "ddivu\t$rs, $rt">; //, ISA_MIPS64_NOT_64R6;
1851 def Ulh : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1852 "ulh\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1854 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1855 "ulhu\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1857 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1858 "ulw\t$rt, $addr">; //, ISA_MIPS1_NOT_32R6_64R6;
1860 //===----------------------------------------------------------------------===//
1861 // Arbitrary patterns that map to one or more instructions
1862 //===----------------------------------------------------------------------===//
1864 // Load/store pattern templates.
1865 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1866 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1868 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1869 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1872 let AdditionalPredicates = [NotInMicroMips] in {
1873 def : MipsPat<(i32 immSExt16:$in),
1874 (ADDiu ZERO, imm:$in)>;
1875 def : MipsPat<(i32 immZExt16:$in),
1876 (ORi ZERO, imm:$in)>;
1878 def : MipsPat<(i32 immLow16Zero:$in),
1879 (LUi (HI16 imm:$in))>;
1881 // Arbitrary immediates
1882 def : MipsPat<(i32 imm:$imm),
1883 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1885 // Carry MipsPatterns
1886 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1887 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1888 let AdditionalPredicates = [NotDSP] in {
1889 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1890 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1891 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1892 (ADDiu GPR32:$src, imm:$imm)>;
1895 // Support multiplication for pre-Mips32 targets that don't have
1896 // the MUL instruction.
1897 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1898 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1899 ISA_MIPS1_NOT_32R6_64R6;
1902 def : MipsPat<(MipsSync (i32 immz)),
1903 (SYNC 0)>, ISA_MIPS2;
1906 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1907 (JAL tglobaladdr:$dst)>;
1908 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1909 (JAL texternalsym:$dst)>;
1910 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1911 // (JALR GPR32:$dst)>;
1914 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1915 (TAILCALL tglobaladdr:$dst)>;
1916 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1917 (TAILCALL texternalsym:$dst)>;
1919 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1920 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1921 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1922 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1923 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1924 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1926 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1927 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1928 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1929 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1930 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1931 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1933 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1934 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1935 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1936 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1937 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1938 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1939 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1940 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1941 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1942 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1945 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1946 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1947 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1948 (ADDiu GPR32:$gp, tconstpool:$in)>;
1951 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1952 MipsPat<(MipsWrapper RC:$gp, node:$in),
1953 (ADDiuOp RC:$gp, node:$in)>;
1955 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1956 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1957 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1958 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1959 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1960 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1962 let AdditionalPredicates = [NotInMicroMips] in {
1963 // Mips does not have "not", so we expand our way
1964 def : MipsPat<(not GPR32:$in),
1965 (NOR GPR32Opnd:$in, ZERO)>;
1969 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1970 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1971 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1974 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1977 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1978 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1979 Instruction SLTiuOp, Register ZEROReg> {
1980 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1981 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1982 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1983 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1985 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1986 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1987 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1988 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1989 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1990 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1991 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1992 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1993 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1994 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1995 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1996 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1998 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1999 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2000 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
2001 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
2003 def : MipsPat<(brcond RC:$cond, bb:$dst),
2004 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
2007 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
2009 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
2010 (BLEZ i32:$lhs, bb:$dst)>;
2011 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
2012 (BGEZ i32:$lhs, bb:$dst)>;
2015 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
2016 Instruction SLTuOp, Register ZEROReg> {
2017 def : MipsPat<(seteq RC:$lhs, 0),
2018 (SLTiuOp RC:$lhs, 1)>;
2019 def : MipsPat<(setne RC:$lhs, 0),
2020 (SLTuOp ZEROReg, RC:$lhs)>;
2021 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
2022 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
2023 def : MipsPat<(setne RC:$lhs, RC:$rhs),
2024 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
2027 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2028 def : MipsPat<(setle RC:$lhs, RC:$rhs),
2029 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
2030 def : MipsPat<(setule RC:$lhs, RC:$rhs),
2031 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
2034 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2035 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
2036 (SLTOp RC:$rhs, RC:$lhs)>;
2037 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
2038 (SLTuOp RC:$rhs, RC:$lhs)>;
2041 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
2042 def : MipsPat<(setge RC:$lhs, RC:$rhs),
2043 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
2044 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
2045 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
2048 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
2049 Instruction SLTiuOp> {
2050 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
2051 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
2052 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
2053 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
2056 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
2057 defm : SetlePats<GPR32, SLT, SLTu>;
2058 defm : SetgtPats<GPR32, SLT, SLTu>;
2059 defm : SetgePats<GPR32, SLT, SLTu>;
2060 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
2063 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
2065 // Load halfword/word patterns.
2066 let AddedComplexity = 40 in {
2067 def : LoadRegImmPat<LBu, i32, zextloadi8>;
2068 def : LoadRegImmPat<LH, i32, sextloadi16>;
2069 let AdditionalPredicates = [NotInMicroMips] in {
2070 def : LoadRegImmPat<LW, i32, load>;
2074 //===----------------------------------------------------------------------===//
2075 // Floating Point Support
2076 //===----------------------------------------------------------------------===//
2078 include "MipsInstrFPU.td"
2079 include "Mips64InstrInfo.td"
2080 include "MipsCondMov.td"
2082 include "Mips32r6InstrInfo.td"
2083 include "Mips64r6InstrInfo.td"
2088 include "Mips16InstrFormats.td"
2089 include "Mips16InstrInfo.td"
2092 include "MipsDSPInstrFormats.td"
2093 include "MipsDSPInstrInfo.td"
2096 include "MipsMSAInstrFormats.td"
2097 include "MipsMSAInstrInfo.td"
2100 include "MipsEVAInstrFormats.td"
2101 include "MipsEVAInstrInfo.td"
2104 include "MicroMipsInstrFormats.td"
2105 include "MicroMipsInstrInfo.td"
2106 include "MicroMipsInstrFPU.td"
2109 include "MicroMips32r6InstrFormats.td"
2110 include "MicroMips32r6InstrInfo.td"
2113 include "MicroMips64r6InstrFormats.td"
2114 include "MicroMips64r6InstrInfo.td"
2117 include "MicroMipsDSPInstrFormats.td"
2118 include "MicroMipsDSPInstrInfo.td"