1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are created to let easy manipulation of 16-bit when
26 // handling 32-bit immediates. They are used on MipsISelLowering to
27 // lower stuff like GlobalAddress, ExternalSymbol, ...
28 // This two nodes have nothing to do with Mips Registers Hi and Lo.
29 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
30 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
33 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
34 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
37 // These are target-independent nodes, but have target-specific formats.
38 def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
39 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
40 [SDNPHasChain, SDNPOutFlag]>;
41 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
42 [SDNPHasChain, SDNPOutFlag]>;
44 // Instruction operand types
45 def brtarget : Operand<OtherVT>;
46 def calltarget : Operand<i32>;
47 def uimm16 : Operand<i32>;
48 def simm16 : Operand<i32>;
49 def shamt : Operand<i32>;
52 def mem : Operand<i32> {
53 let PrintMethod = "printMemOperand";
54 let MIOperandInfo = (ops simm16, CPURegs);
57 //===----------------------------------------------------------------------===//
58 // Mips Patterns and Transformations
59 //===----------------------------------------------------------------------===//
61 // Transformation Function - get the lower 16 bits.
62 def LO16 : SDNodeXForm<imm, [{
63 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
66 // Transformation Function - get the higher 16 bits.
67 def HI16 : SDNodeXForm<imm, [{
68 return getI32Imm((unsigned)N->getValue() >> 16);
71 // Node immediate fits as 16-bit sign extended on target immediate.
73 def immSExt16 : PatLeaf<(imm), [{
74 if (N->getValueType(0) == MVT::i32)
75 return (int32_t)N->getValue() == (short)N->getValue();
77 return (int64_t)N->getValue() == (short)N->getValue();
80 // Node immediate fits as 16-bit zero extended on target immediate.
81 // The LO16 param means that only the lower 16 bits of the node
82 // immediate are caught.
84 def immZExt16 : PatLeaf<(imm), [{
85 if (N->getValueType(0) == MVT::i32)
86 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
88 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
91 // shamt field must fit in 5 bits.
92 def immZExt5 : PatLeaf<(imm), [{
93 return N->getValue() == ((N->getValue()) & 0x1f) ;
96 // Mips Address Mode! SDNode frameindex could possibily be a match
97 // since load and store instructions from stack used it.
98 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
100 //===----------------------------------------------------------------------===//
101 // Instructions specific format
102 //===----------------------------------------------------------------------===//
104 // Arithmetic 3 register operands
105 let isCommutable = 1 in
106 class ArithR< bits<6> op, bits<6> func, string instr_asm, SDNode OpNode>:
110 (ins CPURegs:$b, CPURegs:$c),
111 !strconcat(instr_asm, " $dst, $b, $c"),
112 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
114 let isCommutable = 1 in
115 class ArithOverflowR< bits<6> op, bits<6> func, string instr_asm>:
119 (ins CPURegs:$b, CPURegs:$c),
120 !strconcat(instr_asm, " $dst, $b, $c"),
123 // Arithmetic 2 register operands
124 let isCommutable = 1 in
125 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
126 Operand Od, PatLeaf imm_type> :
129 (ins CPURegs:$b, Od:$c),
130 !strconcat(instr_asm, " $dst, $b, $c"),
131 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))] >;
133 // Arithmetic Multiply ADD/SUB
135 class MArithR<bits<6> func, string instr_asm> :
140 !strconcat(instr_asm, " $rs, $rt"),
144 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
148 (ins CPURegs:$b, CPURegs:$c),
149 !strconcat(instr_asm, " $dst, $b, $c"),
150 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
152 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
155 (ins CPURegs:$b, uimm16:$c),
156 !strconcat(instr_asm, " $dst, $b, $c"),
157 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))]>;
159 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
163 (ins CPURegs:$b, CPURegs:$c),
164 !strconcat(instr_asm, " $dst, $b, $c"),
165 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))] >;
169 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
173 (ins CPURegs:$b, shamt:$c),
174 !strconcat(instr_asm, " $dst, $b, $c"),
175 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))] >;
177 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
181 (ins CPURegs:$b, CPURegs:$c),
182 !strconcat(instr_asm, " $dst, $b, $c"),
183 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))] >;
185 // Load Upper Imediate
186 class LoadUpper<bits<6> op, string instr_asm>:
190 !strconcat(instr_asm, " $dst, $imm"),
195 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
199 !strconcat(instr_asm, " $dst, $addr"),
200 [(set CPURegs:$dst, (OpNode addr:$addr))]>;
203 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
206 (ins CPURegs:$dst, mem:$addr),
207 !strconcat(instr_asm, " $dst, $addr"),
208 [(OpNode CPURegs:$dst, addr:$addr)]>;
210 // Conditional Branch
211 let isBranch = 1, isTerminator=1 in
212 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
215 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
216 !strconcat(instr_asm, " $a, $b, $offset"),
217 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)]>;
219 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
224 (ins CPURegs:$b, CPURegs:$c),
225 !strconcat(instr_asm, " $dst, $b, $c"),
226 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))]>;
228 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
229 Operand Od, PatLeaf imm_type>:
232 (ins CPURegs:$b, Od:$c),
233 !strconcat(instr_asm, " $dst, $b, $c"),
234 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>;
236 // Unconditional branch
237 let hasCtrlDep=1, isTerminator=1 in
238 class JumpFJ<bits<6> op, string instr_asm>:
241 (ins brtarget:$target),
242 !strconcat(instr_asm, " $target"),
245 let hasCtrlDep=1, isTerminator=1, rd=0 in
246 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
250 (ins CPURegs:$target),
251 !strconcat(instr_asm, " $target"),
254 // Jump and Link (Call)
256 class JumpLink<bits<6> op, string instr_asm>:
259 (ins calltarget:$target),
260 !strconcat(instr_asm, " $target"),
261 [(MipsJmpLink imm:$target)]>;
264 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
268 (ins CPURegs:$rd, CPURegs:$rs),
269 !strconcat(instr_asm, " $rs, $rd"),
273 class MulDiv<bits<6> func, string instr_asm>:
277 (ins CPURegs:$a, CPURegs:$b),
278 !strconcat(instr_asm, " $a, $b"),
282 class MoveFromTo<bits<6> func, string instr_asm>:
287 !strconcat(instr_asm, " $dst"),
290 // Count Leading Ones/Zeros in Word
291 class CountLeading<bits<6> func, string instr_asm>:
296 !strconcat(instr_asm, " $dst, $src"),
300 //===----------------------------------------------------------------------===//
301 // Pseudo instructions
302 //===----------------------------------------------------------------------===//
304 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
305 MipsInst<outs, ins, asmstr, pattern>;
307 // As stack alignment is always done with addiu, we need a 16-bit immediate
308 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt),
309 "!ADJCALLSTACKDOWN $amt",
310 [(callseq_start imm:$amt)]>, Imp<[SP],[SP]>;
311 def ADJCALLSTACKUP : Pseudo<(outs), (ins uimm16:$amt),
312 "!ADJCALLSTACKUP $amt",
313 [(callseq_end imm:$amt)]>, Imp<[SP],[SP]>;
315 def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins),
316 "!IMPLICIT_DEF $dst",
317 [(set CPURegs:$dst, (undef))]>;
319 //===----------------------------------------------------------------------===//
320 // Instruction definition
321 //===----------------------------------------------------------------------===//
323 //===----------------------------------------------------------------------===//
325 //===----------------------------------------------------------------------===//
328 def ADDiu : ArithI<0x09, "addiu", add, uimm16, immSExt16>;
329 def ADDi : ArithI<0x08, "addi", add, simm16, immZExt16>;
330 def MUL : ArithR<0x1c, 0x02, "mul", mul>;
331 def ADDu : ArithR<0x00, 0x21, "addu", add>;
332 def SUBu : ArithR<0x00, 0x23, "subu", sub>;
333 def ADD : ArithOverflowR<0x00, 0x20, "add">;
334 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
335 def MADD : MArithR<0x00, "madd">;
336 def MADDU : MArithR<0x01, "maddu">;
337 def MSUB : MArithR<0x04, "msub">;
338 def MSUBU : MArithR<0x05, "msubu">;
341 def AND : LogicR<0x24, "and", and>;
342 def OR : LogicR<0x25, "or", or>;
343 def XOR : LogicR<0x26, "xor", xor>;
344 def ANDi : LogicI<0x0c, "andi", and>;
345 def ORi : LogicI<0x0d, "ori", or>;
346 def XORi : LogicI<0x0e, "xori", xor>;
347 def NOR : LogicNOR<0x00, 0x27, "nor">;
350 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
351 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
352 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
353 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
354 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
355 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
357 // Load Upper Immediate
358 def LUi : LoadUpper<0x0f, "lui">;
361 def LB : LoadM<0x20, "lb", sextloadi8>;
362 def LBu : LoadM<0x24, "lbu", zextloadi8>;
363 def LH : LoadM<0x21, "lh", sextloadi16>;
364 def LHu : LoadM<0x25, "lhu", zextloadi16>;
365 def LW : LoadM<0x23, "lw", load>;
366 def SB : StoreM<0x28, "sb", truncstorei8>;
367 def SH : StoreM<0x29, "sh", truncstorei16>;
368 def SW : StoreM<0x2b, "sw", store>;
370 // Conditional Branch
371 def BEQ : CBranch<0x04, "beq", seteq>;
372 def BNE : CBranch<0x05, "bne", setne>;
373 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
374 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
375 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
376 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
378 // Unconditional jump
379 def J : JumpFJ<0x02, "j">;
380 def JR : JumpFR<0x00, 0x08, "jr">;
382 // Jump and Link (Call)
383 def JAL : JumpLink<0x03, "jal">;
384 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
386 // MulDiv and Move From Hi/Lo operations, have
387 // their correpondent SDNodes created on ISelDAG.
388 // Special Mul, Div operations
389 def MULT : MulDiv<0x18, "mult">;
390 def MULTu : MulDiv<0x19, "multu">;
391 def DIV : MulDiv<0x1a, "div">;
392 def DIVu : MulDiv<0x1b, "divu">;
395 def MFHI : MoveFromTo<0x10, "mfhi">;
396 def MFLO : MoveFromTo<0x12, "mflo">;
397 def MTHI : MoveFromTo<0x11, "mthi">;
398 def MTLO : MoveFromTo<0x13, "mtlo">;
401 def CLO : CountLeading<0x21, "clo">;
402 def CLZ : CountLeading<0x20, "clz">;
406 def NOOP : FJ<0, (outs), (ins), "nop", []>;
408 // Ret instruction - as mips does not have "ret" a
409 // jr $ra must be generated.
410 let isReturn=1, isTerminator=1, hasDelaySlot=1,
411 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
413 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
414 "jr $target", [(MipsRet CPURegs:$target)]>;
417 //===----------------------------------------------------------------------===//
418 // Arbitrary patterns that map to one or more instructions
419 //===----------------------------------------------------------------------===//
422 def : Pat<(i32 immSExt16:$in),
423 (ADDiu ZERO, imm:$in)>;
424 def : Pat<(i32 immZExt16:$in),
425 (ORi ZERO, imm:$in)>;
427 // Arbitrary immediates
428 def : Pat<(i32 imm:$imm),
429 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
432 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
433 (JAL tglobaladdr:$dst)>;
434 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
435 (JAL texternalsym:$dst)>;
437 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
438 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
439 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
441 // When extracting the address from GlobalAddress we
442 // need something of the form "addiu $reg, %lo(addr)"
443 def : Pat<(add CPURegs:$a, (MipsLo tglobaladdr:$in)),
444 (ADDiu CPURegs:$a, tglobaladdr:$in)>;
446 // Mips does not have not, so we increase the operation
447 def : Pat<(not CPURegs:$in),
448 (NOR CPURegs:$in, CPURegs:$in)>;
450 // extended load and stores
451 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
452 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
453 def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
454 (SB CPURegs:$src, addr:$src)>;
456 def : Pat<(brcond (setne CPURegs:$lhs, (add ZERO, 0)), bb:$dst),
457 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
460 // Conditional branch patterns.
461 // cond branches patterns, 2 register operands signed.
462 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
463 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
464 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
465 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
466 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
467 (BNE (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
468 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
469 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
471 // cond branches patterns, 2 register operands unsigned.
472 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
473 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
474 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
475 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
476 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
477 (BNE (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
478 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
479 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
481 // cond branches patterns, reg/imm operands signed.
482 def : Pat<(brcond (setult CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
483 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
484 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
485 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
487 // cond branches patterns, reg/imm operands unsigned.
488 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
489 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
490 def : Pat<(brcond (setuge CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
491 (BEQ (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;