1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
190 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64> {
266 let DecoderMethod = "DecodeSimm16";
270 def uimm5 : Operand<i32> {
271 let PrintMethod = "printUnsignedImm";
274 def uimm6 : Operand<i32> {
275 let PrintMethod = "printUnsignedImm";
278 def uimm16 : Operand<i32> {
279 let PrintMethod = "printUnsignedImm";
282 def pcrel16 : Operand<i32> {
285 def MipsMemAsmOperand : AsmOperandClass {
287 let ParserMethod = "parseMemOperand";
290 def MipsInvertedImmoperand : AsmOperandClass {
292 let RenderMethod = "addImmOperands";
293 let ParserMethod = "parseInvNum";
296 def PtrRegAsmOperand : AsmOperandClass {
298 let ParserMethod = "parsePtrReg";
302 def InvertedImOperand : Operand<i32> {
303 let ParserMatchClass = MipsInvertedImmoperand;
306 class mem_generic : Operand<iPTR> {
307 let PrintMethod = "printMemOperand";
308 let MIOperandInfo = (ops ptr_rc, simm16);
309 let EncoderMethod = "getMemEncoding";
310 let ParserMatchClass = MipsMemAsmOperand;
311 let OperandType = "OPERAND_MEMORY";
315 def mem : mem_generic;
317 // MSA specific address operand
318 def mem_msa : mem_generic {
319 let EncoderMethod = "getMSAMemEncoding";
322 def mem_ea : Operand<iPTR> {
323 let PrintMethod = "printMemOperandEA";
324 let MIOperandInfo = (ops ptr_rc, simm16);
325 let EncoderMethod = "getMemEncoding";
326 let OperandType = "OPERAND_MEMORY";
329 def PtrRC : Operand<iPTR> {
330 let MIOperandInfo = (ops ptr_rc);
331 let DecoderMethod = "DecodePtrRegisterClass";
332 let ParserMatchClass = PtrRegAsmOperand;
335 // size operand of ext instruction
336 def size_ext : Operand<i32> {
337 let EncoderMethod = "getSizeExtEncoding";
338 let DecoderMethod = "DecodeExtSize";
341 // size operand of ins instruction
342 def size_ins : Operand<i32> {
343 let EncoderMethod = "getSizeInsEncoding";
344 let DecoderMethod = "DecodeInsSize";
347 // Transformation Function - get the lower 16 bits.
348 def LO16 : SDNodeXForm<imm, [{
349 return getImm(N, N->getZExtValue() & 0xFFFF);
352 // Transformation Function - get the higher 16 bits.
353 def HI16 : SDNodeXForm<imm, [{
354 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
358 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
360 // Node immediate fits as 16-bit sign extended on target immediate.
362 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
364 // Node immediate fits as 16-bit sign extended on target immediate.
366 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
368 // Node immediate fits as 15-bit sign extended on target immediate.
370 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
372 // Node immediate fits as 16-bit zero extended on target immediate.
373 // The LO16 param means that only the lower 16 bits of the node
374 // immediate are caught.
376 def immZExt16 : PatLeaf<(imm), [{
377 if (N->getValueType(0) == MVT::i32)
378 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
380 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
383 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
384 def immLow16Zero : PatLeaf<(imm), [{
385 int64_t Val = N->getSExtValue();
386 return isInt<32>(Val) && !(Val & 0xffff);
389 // shamt field must fit in 5 bits.
390 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
392 // True if (N + 1) fits in 16-bit field.
393 def immSExt16Plus1 : PatLeaf<(imm), [{
394 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
397 // Mips Address Mode! SDNode frameindex could possibily be a match
398 // since load and store instructions from stack used it.
400 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
403 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
406 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
409 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
411 //===----------------------------------------------------------------------===//
412 // Instructions specific format
413 //===----------------------------------------------------------------------===//
415 // Arithmetic and logical instructions with 3 register operands.
416 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
417 InstrItinClass Itin = NoItinerary,
418 SDPatternOperator OpNode = null_frag>:
419 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
420 !strconcat(opstr, "\t$rd, $rs, $rt"),
421 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
422 let isCommutable = isComm;
423 let isReMaterializable = 1;
426 // Arithmetic and logical instructions with 2 register operands.
427 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
428 InstrItinClass Itin = NoItinerary,
429 SDPatternOperator imm_type = null_frag,
430 SDPatternOperator OpNode = null_frag> :
431 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
432 !strconcat(opstr, "\t$rt, $rs, $imm16"),
433 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
435 let isReMaterializable = 1;
436 let TwoOperandAliasConstraint = "$rs = $rt";
439 // Arithmetic Multiply ADD/SUB
440 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
441 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
442 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
443 let Defs = [HI0, LO0];
444 let Uses = [HI0, LO0];
445 let isCommutable = isComm;
449 class LogicNOR<string opstr, RegisterOperand RO>:
450 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
451 !strconcat(opstr, "\t$rd, $rs, $rt"),
452 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
453 let isCommutable = 1;
457 class shift_rotate_imm<string opstr, Operand ImmOpnd,
458 RegisterOperand RO, InstrItinClass itin,
459 SDPatternOperator OpNode = null_frag,
460 SDPatternOperator PF = null_frag> :
461 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
462 !strconcat(opstr, "\t$rd, $rt, $shamt"),
463 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
465 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
466 SDPatternOperator OpNode = null_frag>:
467 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
468 !strconcat(opstr, "\t$rd, $rt, $rs"),
469 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
472 // Load Upper Imediate
473 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
474 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
475 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
476 let neverHasSideEffects = 1;
477 let isReMaterializable = 1;
481 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
482 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
483 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
484 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
485 let DecoderMethod = "DecodeMem";
486 let canFoldAsLoad = 1;
490 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
491 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
492 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
493 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
494 let DecoderMethod = "DecodeMem";
498 // Load/Store Left/Right
499 let canFoldAsLoad = 1 in
500 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
501 InstrItinClass Itin> :
502 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
503 !strconcat(opstr, "\t$rt, $addr"),
504 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
505 let DecoderMethod = "DecodeMem";
506 string Constraints = "$src = $rt";
509 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
510 InstrItinClass Itin> :
511 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
512 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
513 let DecoderMethod = "DecodeMem";
516 // Conditional Branch
517 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
518 RegisterOperand RO> :
519 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
520 !strconcat(opstr, "\t$rs, $rt, $offset"),
521 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
524 let isTerminator = 1;
525 let hasDelaySlot = 1;
529 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
530 RegisterOperand RO> :
531 InstSE<(outs), (ins RO:$rs, opnd:$offset),
532 !strconcat(opstr, "\t$rs, $offset"),
533 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
536 let isTerminator = 1;
537 let hasDelaySlot = 1;
542 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
543 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
544 !strconcat(opstr, "\t$rd, $rs, $rt"),
545 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
546 II_SLT_SLTU, FrmR, opstr>;
548 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
550 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
551 !strconcat(opstr, "\t$rt, $rs, $imm16"),
552 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
553 II_SLTI_SLTIU, FrmI, opstr>;
556 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
557 SDPatternOperator targetoperator, string bopstr> :
558 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
559 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
562 let hasDelaySlot = 1;
563 let DecoderMethod = "DecodeJumpTarget";
567 // Unconditional branch
568 class UncondBranch<Instruction BEQInst> :
569 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
570 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
572 let isTerminator = 1;
574 let hasDelaySlot = 1;
575 let Predicates = [RelocPIC, HasStdEnc];
579 // Base class for indirect branch and return instruction classes.
580 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
581 class JumpFR<string opstr, RegisterOperand RO,
582 SDPatternOperator operator = null_frag>:
583 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
587 class IndirectBranch<string opstr, RegisterOperand RO> :
588 JumpFR<opstr, RO, brind> {
590 let isIndirectBranch = 1;
593 // Return instruction
594 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
596 let isCodeGenOnly = 1;
598 let hasExtraSrcRegAllocReq = 1;
601 // Jump and Link (Call)
602 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
603 class JumpLink<string opstr, DAGOperand opnd> :
604 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
605 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
606 let DecoderMethod = "DecodeJumpTarget";
609 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
610 Register RetReg, RegisterOperand ResRO = RO>:
611 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
612 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
614 class JumpLinkReg<string opstr, RegisterOperand RO>:
615 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
616 [], IIBranch, FrmR, opstr>;
618 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
619 InstSE<(outs), (ins RO:$rs, opnd:$offset),
620 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
624 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
625 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
626 class TailCall<Instruction JumpInst> :
627 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
628 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
630 class TailCallReg<RegisterOperand RO, Instruction JRInst,
631 RegisterOperand ResRO = RO> :
632 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
633 PseudoInstExpansion<(JRInst ResRO:$rs)>;
636 class BAL_BR_Pseudo<Instruction RealInst> :
637 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
638 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
640 let isTerminator = 1;
642 let hasDelaySlot = 1;
647 class SYS_FT<string opstr> :
648 InstSE<(outs), (ins uimm20:$code_),
649 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
651 class BRK_FT<string opstr> :
652 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
653 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
657 class ER_FT<string opstr> :
658 InstSE<(outs), (ins),
659 opstr, [], NoItinerary, FrmOther, opstr>;
662 class DEI_FT<string opstr, RegisterOperand RO> :
663 InstSE<(outs RO:$rt), (ins),
664 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
667 class WAIT_FT<string opstr> :
668 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
671 let hasSideEffects = 1 in
672 class SYNC_FT<string opstr> :
673 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
674 NoItinerary, FrmOther, opstr>;
676 let hasSideEffects = 1 in
677 class TEQ_FT<string opstr, RegisterOperand RO> :
678 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
679 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
682 class TEQI_FT<string opstr, RegisterOperand RO> :
683 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
684 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
686 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
687 list<Register> DefRegs> :
688 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
690 let isCommutable = 1;
692 let neverHasSideEffects = 1;
695 // Pseudo multiply/divide instruction with explicit accumulator register
697 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
698 SDPatternOperator OpNode, InstrItinClass Itin,
699 bit IsComm = 1, bit HasSideEffects = 0,
700 bit UsesCustomInserter = 0> :
701 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
702 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
703 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
704 let isCommutable = IsComm;
705 let hasSideEffects = HasSideEffects;
706 let usesCustomInserter = UsesCustomInserter;
709 // Pseudo multiply add/sub instruction with explicit accumulator register
711 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
713 : PseudoSE<(outs ACC64:$ac),
714 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
716 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
718 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
719 string Constraints = "$acin = $ac";
722 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
723 list<Register> DefRegs> :
724 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
725 [], itin, FrmR, opstr> {
730 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
731 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
732 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
734 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
735 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
738 let neverHasSideEffects = 1;
741 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
742 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
743 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
746 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
747 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
750 let neverHasSideEffects = 1;
753 class EffectiveAddress<string opstr, RegisterOperand RO> :
754 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
755 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
756 !strconcat(opstr, "_lea")> {
757 let isCodeGenOnly = 1;
758 let DecoderMethod = "DecodeMem";
761 // Count Leading Ones/Zeros in Word
762 class CountLeading0<string opstr, RegisterOperand RO>:
763 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
764 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
765 Requires<[HasBitCount, HasStdEnc]>;
767 class CountLeading1<string opstr, RegisterOperand RO>:
768 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
769 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
770 Requires<[HasBitCount, HasStdEnc]>;
773 // Sign Extend in Register.
774 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
775 InstrItinClass itin> :
776 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
777 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
778 let Predicates = [HasSEInReg, HasStdEnc];
782 class SubwordSwap<string opstr, RegisterOperand RO>:
783 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
784 NoItinerary, FrmR, opstr> {
785 let Predicates = [HasSwap, HasStdEnc];
786 let neverHasSideEffects = 1;
790 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
791 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
795 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
796 SDPatternOperator Op = null_frag>:
797 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
798 !strconcat(opstr, " $rt, $rs, $pos, $size"),
799 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
801 let Predicates = [HasMips32r2, HasStdEnc];
804 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
805 SDPatternOperator Op = null_frag>:
806 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
807 !strconcat(opstr, " $rt, $rs, $pos, $size"),
808 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
809 NoItinerary, FrmR, opstr> {
810 let Predicates = [HasMips32r2, HasStdEnc];
811 let Constraints = "$src = $rt";
814 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
815 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
816 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
817 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
819 // Atomic Compare & Swap.
820 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
821 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
822 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
824 class LLBase<string opstr, RegisterOperand RO> :
825 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
826 [], NoItinerary, FrmI> {
827 let DecoderMethod = "DecodeMem";
831 class SCBase<string opstr, RegisterOperand RO> :
832 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
833 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
834 let DecoderMethod = "DecodeMem";
836 let Constraints = "$rt = $dst";
839 class MFC3OP<string asmstr, RegisterOperand RO> :
840 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
841 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
843 class TrapBase<Instruction RealInst>
844 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
845 PseudoInstExpansion<(RealInst 0, 0)> {
847 let isTerminator = 1;
848 let isCodeGenOnly = 1;
851 //===----------------------------------------------------------------------===//
852 // Pseudo instructions
853 //===----------------------------------------------------------------------===//
856 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
857 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
859 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
860 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
861 [(callseq_start timm:$amt)]>;
862 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
863 [(callseq_end timm:$amt1, timm:$amt2)]>;
866 let usesCustomInserter = 1 in {
867 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
868 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
869 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
870 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
871 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
872 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
873 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
874 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
875 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
876 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
877 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
878 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
879 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
880 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
881 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
882 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
883 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
884 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
886 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
887 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
888 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
890 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
891 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
892 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
895 /// Pseudo instructions for loading and storing accumulator registers.
896 let isPseudo = 1, isCodeGenOnly = 1 in {
897 def LOAD_ACC64 : Load<"", ACC64>;
898 def STORE_ACC64 : Store<"", ACC64>;
901 //===----------------------------------------------------------------------===//
902 // Instruction definition
903 //===----------------------------------------------------------------------===//
904 //===----------------------------------------------------------------------===//
905 // MipsI Instructions
906 //===----------------------------------------------------------------------===//
908 /// Arithmetic Instructions (ALU Immediate)
909 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
911 ADDI_FM<0x9>, IsAsCheapAsAMove;
912 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
913 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
915 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
917 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
920 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
923 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
926 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
928 /// Arithmetic Instructions (3-Operand, R-Type)
929 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
931 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
933 let Defs = [HI0, LO0] in
934 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
936 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
937 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
938 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
939 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
940 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
942 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
944 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
946 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
948 /// Shift Instructions
949 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
950 immZExt5>, SRA_FM<0, 0>;
951 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
952 immZExt5>, SRA_FM<2, 0>;
953 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
954 immZExt5>, SRA_FM<3, 0>;
955 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
957 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
959 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
962 // Rotate Instructions
963 let Predicates = [HasMips32r2, HasStdEnc] in {
964 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
965 immZExt5>, SRA_FM<2, 1>;
966 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
970 /// Load and Store Instructions
972 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
973 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
975 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
977 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
978 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
980 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
981 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
982 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
984 /// load/store left/right
985 let Predicates = [NotInMicroMips] in {
986 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
987 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
988 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
989 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
992 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
993 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
994 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
995 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
996 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
997 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
998 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1000 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1001 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1002 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1003 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1004 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1005 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1007 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1008 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1009 def TRAP : TrapBase<BREAK>;
1011 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1012 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1014 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1015 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1017 def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM;
1019 /// Load-linked, Store-conditional
1020 let Predicates = [NotInMicroMips] in {
1021 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1022 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1025 /// Jump and Branch Instructions
1026 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1027 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1028 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1029 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1030 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1031 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1033 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1035 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1037 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1039 def B : UncondBranch<BEQ>;
1041 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1042 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1043 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1044 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1045 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1046 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1047 def TAILCALL : TailCall<J>;
1048 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1050 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1052 // Exception handling related node and instructions.
1053 // The conversion sequence is:
1054 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1055 // MIPSeh_return -> (stack change + indirect branch)
1057 // MIPSeh_return takes the place of regular return instruction
1058 // but takes two arguments (V1, V0) which are used for storing
1059 // the offset and return address respectively.
1060 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1062 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1063 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1065 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1066 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1067 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1068 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1070 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1073 /// Multiply and Divide Instructions.
1074 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1076 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1078 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1080 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1083 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1084 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1085 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1086 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1088 /// Sign Ext In Register Instructions.
1089 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1090 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1093 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1094 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1096 /// Word Swap Bytes Within Halfwords
1097 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1100 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1102 // FrameIndexes are legalized when they are operands from load/store
1103 // instructions. The same not happens for stack address copies, so an
1104 // add op with mem ComplexPattern is used and the stack address copy
1105 // can be matched. It's similar to Sparc LEA_ADDRi
1106 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1109 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1110 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1111 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1112 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1114 let Predicates = [HasStdEnc, NotDSP] in {
1115 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1116 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1117 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1118 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1119 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1120 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1121 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1122 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1123 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1126 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1128 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1131 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1133 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1134 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1136 /// Move Control Registers From/To CPU Registers
1137 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1138 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1139 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1140 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1142 //===----------------------------------------------------------------------===//
1143 // Instruction aliases
1144 //===----------------------------------------------------------------------===//
1145 def : InstAlias<"move $dst, $src",
1146 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1147 Requires<[NotMips64]>;
1148 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1149 def : InstAlias<"addu $rs, $rt, $imm",
1150 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1151 def : InstAlias<"add $rs, $rt, $imm",
1152 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1153 def : InstAlias<"and $rs, $rt, $imm",
1154 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1155 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1156 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1157 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1158 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1159 def : InstAlias<"not $rt, $rs",
1160 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1161 def : InstAlias<"neg $rt, $rs",
1162 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1163 def : InstAlias<"negu $rt, $rs",
1164 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1165 def : InstAlias<"slt $rs, $rt, $imm",
1166 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1167 def : InstAlias<"xor $rs, $rt, $imm",
1168 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1169 def : InstAlias<"or $rs, $rt, $imm",
1170 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1171 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1172 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1173 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1174 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1175 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1176 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1177 def : InstAlias<"bnez $rs,$offset",
1178 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1179 def : InstAlias<"beqz $rs,$offset",
1180 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1181 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1183 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1184 def : InstAlias<"break", (BREAK 0, 0), 1>;
1185 def : InstAlias<"ei", (EI ZERO), 1>;
1186 def : InstAlias<"di", (DI ZERO), 1>;
1188 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1189 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1190 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1191 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1192 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1193 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1194 def : InstAlias<"sub, $rd, $rs, $imm",
1195 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1196 def : InstAlias<"subu, $rd, $rs, $imm",
1197 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1199 //===----------------------------------------------------------------------===//
1200 // Assembler Pseudo Instructions
1201 //===----------------------------------------------------------------------===//
1203 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1204 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1205 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1206 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1208 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1209 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1210 !strconcat(instr_asm, "\t$rt, $addr")> ;
1211 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1213 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1214 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1215 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1216 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1218 //===----------------------------------------------------------------------===//
1219 // Arbitrary patterns that map to one or more instructions
1220 //===----------------------------------------------------------------------===//
1222 // Load/store pattern templates.
1223 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1224 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1226 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1227 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1230 def : MipsPat<(i32 immSExt16:$in),
1231 (ADDiu ZERO, imm:$in)>;
1232 def : MipsPat<(i32 immZExt16:$in),
1233 (ORi ZERO, imm:$in)>;
1234 def : MipsPat<(i32 immLow16Zero:$in),
1235 (LUi (HI16 imm:$in))>;
1237 // Arbitrary immediates
1238 def : MipsPat<(i32 imm:$imm),
1239 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1241 // Carry MipsPatterns
1242 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1243 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1244 let Predicates = [HasStdEnc, NotDSP] in {
1245 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1246 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1247 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1248 (ADDiu GPR32:$src, imm:$imm)>;
1252 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1253 (JAL tglobaladdr:$dst)>;
1254 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1255 (JAL texternalsym:$dst)>;
1256 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1257 // (JALR GPR32:$dst)>;
1260 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1261 (TAILCALL tglobaladdr:$dst)>;
1262 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1263 (TAILCALL texternalsym:$dst)>;
1265 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1266 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1267 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1268 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1269 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1270 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1272 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1273 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1274 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1275 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1276 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1277 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1279 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1280 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1281 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1282 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1283 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1284 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1285 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1286 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1287 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1288 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1291 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1292 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1293 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1294 (ADDiu GPR32:$gp, tconstpool:$in)>;
1297 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1298 MipsPat<(MipsWrapper RC:$gp, node:$in),
1299 (ADDiuOp RC:$gp, node:$in)>;
1301 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1302 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1303 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1304 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1305 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1306 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1308 // Mips does not have "not", so we expand our way
1309 def : MipsPat<(not GPR32:$in),
1310 (NOR GPR32Opnd:$in, ZERO)>;
1313 let Predicates = [HasStdEnc] in {
1314 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1315 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1316 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1320 let Predicates = [HasStdEnc] in
1321 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1324 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1325 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1326 Instruction SLTiuOp, Register ZEROReg> {
1327 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1328 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1329 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1330 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1332 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1333 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1334 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1335 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1336 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1337 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1338 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1339 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1340 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1341 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1342 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1343 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1345 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1346 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1347 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1348 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1350 def : MipsPat<(brcond RC:$cond, bb:$dst),
1351 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1354 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1356 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1357 (BLEZ i32:$lhs, bb:$dst)>;
1358 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1359 (BGEZ i32:$lhs, bb:$dst)>;
1362 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1363 Instruction SLTuOp, Register ZEROReg> {
1364 def : MipsPat<(seteq RC:$lhs, 0),
1365 (SLTiuOp RC:$lhs, 1)>;
1366 def : MipsPat<(setne RC:$lhs, 0),
1367 (SLTuOp ZEROReg, RC:$lhs)>;
1368 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1369 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1370 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1371 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1374 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1375 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1376 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1377 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1378 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1381 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1382 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1383 (SLTOp RC:$rhs, RC:$lhs)>;
1384 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1385 (SLTuOp RC:$rhs, RC:$lhs)>;
1388 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1389 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1390 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1391 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1392 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1395 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1396 Instruction SLTiuOp> {
1397 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1398 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1399 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1400 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1403 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1404 defm : SetlePats<GPR32, SLT, SLTu>;
1405 defm : SetgtPats<GPR32, SLT, SLTu>;
1406 defm : SetgePats<GPR32, SLT, SLTu>;
1407 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1410 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1412 // Load halfword/word patterns.
1413 let AddedComplexity = 40 in {
1414 let Predicates = [HasStdEnc] in {
1415 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1416 def : LoadRegImmPat<LH, i32, sextloadi16>;
1417 def : LoadRegImmPat<LW, i32, load>;
1421 //===----------------------------------------------------------------------===//
1422 // Floating Point Support
1423 //===----------------------------------------------------------------------===//
1425 include "MipsInstrFPU.td"
1426 include "Mips64InstrInfo.td"
1427 include "MipsCondMov.td"
1432 include "Mips16InstrFormats.td"
1433 include "Mips16InstrInfo.td"
1436 include "MipsDSPInstrFormats.td"
1437 include "MipsDSPInstrInfo.td"
1440 include "MipsMSAInstrFormats.td"
1441 include "MipsMSAInstrInfo.td"
1444 include "MicroMipsInstrFormats.td"
1445 include "MicroMipsInstrInfo.td"
1446 include "MicroMipsInstrFPU.td"