1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
189 def IsLE : Predicate<"Subtarget.isLittle()">;
190 def IsBE : Predicate<"!Subtarget.isLittle()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
251 def calltarget64: Operand<i64>;
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64>;
266 def shamt : Operand<i32>;
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm16 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def MipsMemAsmOperand : AsmOperandClass {
279 let ParserMethod = "parseMemOperand";
282 def PtrRegAsmOperand : AsmOperandClass {
284 let ParserMethod = "parsePtrReg";
288 def mem : Operand<iPTR> {
289 let PrintMethod = "printMemOperand";
290 let MIOperandInfo = (ops ptr_rc, simm16);
291 let EncoderMethod = "getMemEncoding";
292 let ParserMatchClass = MipsMemAsmOperand;
293 let OperandType = "OPERAND_MEMORY";
296 def mem_ea : Operand<iPTR> {
297 let PrintMethod = "printMemOperandEA";
298 let MIOperandInfo = (ops ptr_rc, simm16);
299 let EncoderMethod = "getMemEncoding";
300 let OperandType = "OPERAND_MEMORY";
303 def PtrRC : Operand<iPTR> {
304 let MIOperandInfo = (ops ptr_rc);
305 let DecoderMethod = "DecodePtrRegisterClass";
306 let ParserMatchClass = PtrRegAsmOperand;
309 // size operand of ext instruction
310 def size_ext : Operand<i32> {
311 let EncoderMethod = "getSizeExtEncoding";
312 let DecoderMethod = "DecodeExtSize";
315 // size operand of ins instruction
316 def size_ins : Operand<i32> {
317 let EncoderMethod = "getSizeInsEncoding";
318 let DecoderMethod = "DecodeInsSize";
321 // Transformation Function - get the lower 16 bits.
322 def LO16 : SDNodeXForm<imm, [{
323 return getImm(N, N->getZExtValue() & 0xFFFF);
326 // Transformation Function - get the higher 16 bits.
327 def HI16 : SDNodeXForm<imm, [{
328 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
332 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
334 // Node immediate fits as 16-bit sign extended on target immediate.
336 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
338 // Node immediate fits as 16-bit sign extended on target immediate.
340 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
342 // Node immediate fits as 15-bit sign extended on target immediate.
344 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
346 // Node immediate fits as 16-bit zero extended on target immediate.
347 // The LO16 param means that only the lower 16 bits of the node
348 // immediate are caught.
350 def immZExt16 : PatLeaf<(imm), [{
351 if (N->getValueType(0) == MVT::i32)
352 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
354 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
357 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
358 def immLow16Zero : PatLeaf<(imm), [{
359 int64_t Val = N->getSExtValue();
360 return isInt<32>(Val) && !(Val & 0xffff);
363 // shamt field must fit in 5 bits.
364 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
366 // True if (N + 1) fits in 16-bit field.
367 def immSExt16Plus1 : PatLeaf<(imm), [{
368 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
371 // Mips Address Mode! SDNode frameindex could possibily be a match
372 // since load and store instructions from stack used it.
374 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
377 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
380 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
383 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
385 //===----------------------------------------------------------------------===//
386 // Instructions specific format
387 //===----------------------------------------------------------------------===//
389 // Arithmetic and logical instructions with 3 register operands.
390 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
391 InstrItinClass Itin = NoItinerary,
392 SDPatternOperator OpNode = null_frag>:
393 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
394 !strconcat(opstr, "\t$rd, $rs, $rt"),
395 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
396 let isCommutable = isComm;
397 let isReMaterializable = 1;
400 // Arithmetic and logical instructions with 2 register operands.
401 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
402 InstrItinClass Itin = NoItinerary,
403 SDPatternOperator imm_type = null_frag,
404 SDPatternOperator OpNode = null_frag> :
405 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
406 !strconcat(opstr, "\t$rt, $rs, $imm16"),
407 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
409 let isReMaterializable = 1;
410 let TwoOperandAliasConstraint = "$rs = $rt";
413 // Arithmetic Multiply ADD/SUB
414 class MArithR<string opstr, bit isComm = 0> :
415 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
416 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR> {
417 let Defs = [HI0, LO0];
418 let Uses = [HI0, LO0];
419 let isCommutable = isComm;
423 class LogicNOR<string opstr, RegisterOperand RO>:
424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
425 !strconcat(opstr, "\t$rd, $rs, $rt"),
426 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
427 let isCommutable = 1;
431 class shift_rotate_imm<string opstr, Operand ImmOpnd,
432 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
433 SDPatternOperator PF = null_frag> :
434 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
435 !strconcat(opstr, "\t$rd, $rt, $shamt"),
436 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
438 class shift_rotate_reg<string opstr, RegisterOperand RO,
439 SDPatternOperator OpNode = null_frag>:
440 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
441 !strconcat(opstr, "\t$rd, $rt, $rs"),
442 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
444 // Load Upper Imediate
445 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
446 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
447 [], IIArith, FrmI>, IsAsCheapAsAMove {
448 let neverHasSideEffects = 1;
449 let isReMaterializable = 1;
452 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
453 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
455 let Inst{25-21} = addr{20-16};
456 let Inst{15-0} = addr{15-0};
457 let DecoderMethod = "DecodeMem";
461 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
462 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
463 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
464 [(set RO:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI, opstr> {
465 let DecoderMethod = "DecodeMem";
466 let canFoldAsLoad = 1;
470 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
471 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
472 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
473 [(OpNode RO:$rt, Addr:$addr)], NoItinerary, FrmI, opstr> {
474 let DecoderMethod = "DecodeMem";
478 // Load/Store Left/Right
479 let canFoldAsLoad = 1 in
480 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
481 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
482 !strconcat(opstr, "\t$rt, $addr"),
483 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], NoItinerary, FrmI> {
484 let DecoderMethod = "DecodeMem";
485 string Constraints = "$src = $rt";
488 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO> :
489 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
490 [(OpNode RO:$rt, addr:$addr)], NoItinerary, FrmI> {
491 let DecoderMethod = "DecodeMem";
494 // Conditional Branch
495 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
496 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
497 !strconcat(opstr, "\t$rs, $rt, $offset"),
498 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
501 let isTerminator = 1;
502 let hasDelaySlot = 1;
506 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
507 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
508 !strconcat(opstr, "\t$rs, $offset"),
509 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
511 let isTerminator = 1;
512 let hasDelaySlot = 1;
517 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
518 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
519 !strconcat(opstr, "\t$rd, $rs, $rt"),
520 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
523 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
525 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
526 !strconcat(opstr, "\t$rt, $rs, $imm16"),
527 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
531 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
532 SDPatternOperator targetoperator> :
533 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
534 [(operator targetoperator:$target)], IIBranch, FrmJ> {
537 let hasDelaySlot = 1;
538 let DecoderMethod = "DecodeJumpTarget";
542 // Unconditional branch
543 class UncondBranch<string opstr> :
544 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
545 [(br bb:$offset)], IIBranch, FrmI> {
547 let isTerminator = 1;
549 let hasDelaySlot = 1;
550 let Predicates = [RelocPIC, HasStdEnc];
554 // Base class for indirect branch and return instruction classes.
555 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
556 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
557 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
560 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
562 let isIndirectBranch = 1;
565 // Return instruction
566 class RetBase<RegisterOperand RO>: JumpFR<RO> {
568 let isCodeGenOnly = 1;
570 let hasExtraSrcRegAllocReq = 1;
573 // Jump and Link (Call)
574 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
575 class JumpLink<string opstr> :
576 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
577 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
578 let DecoderMethod = "DecodeJumpTarget";
581 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
582 Register RetReg, RegisterOperand ResRO = RO>:
583 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
584 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
586 class JumpLinkReg<string opstr, RegisterOperand RO>:
587 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
590 class BGEZAL_FT<string opstr, RegisterOperand RO> :
591 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
592 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
596 class BAL_BR_Pseudo<Instruction RealInst> :
597 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
598 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
600 let isTerminator = 1;
602 let hasDelaySlot = 1;
607 class SYS_FT<string opstr> :
608 InstSE<(outs), (ins uimm20:$code_),
609 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
611 class BRK_FT<string opstr> :
612 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
613 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
616 class ER_FT<string opstr> :
617 InstSE<(outs), (ins),
618 opstr, [], NoItinerary, FrmOther>;
621 class DEI_FT<string opstr, RegisterOperand RO> :
622 InstSE<(outs RO:$rt), (ins),
623 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
626 class WAIT_FT<string opstr> :
627 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
628 let Inst{31-26} = 0x10;
631 let Inst{5-0} = 0x20;
635 let hasSideEffects = 1 in
637 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
638 NoItinerary, FrmOther>;
640 let hasSideEffects = 1 in
641 class TEQ_FT<string opstr, RegisterOperand RO> :
642 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
643 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
645 class TEQI_FT<string opstr, RegisterOperand RO> :
646 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
647 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
649 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
650 list<Register> DefRegs> :
651 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
653 let isCommutable = 1;
655 let neverHasSideEffects = 1;
658 // Pseudo multiply/divide instruction with explicit accumulator register
660 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
661 SDPatternOperator OpNode, InstrItinClass Itin,
662 bit IsComm = 1, bit HasSideEffects = 0,
663 bit UsesCustomInserter = 0> :
664 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
665 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
666 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
667 let isCommutable = IsComm;
668 let hasSideEffects = HasSideEffects;
669 let usesCustomInserter = UsesCustomInserter;
672 // Pseudo multiply add/sub instruction with explicit accumulator register
674 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
675 : PseudoSE<(outs ACC64:$ac),
676 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
678 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
680 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
681 string Constraints = "$acin = $ac";
684 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
685 list<Register> DefRegs> :
686 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
692 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
693 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
695 let neverHasSideEffects = 1;
698 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
699 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
701 let neverHasSideEffects = 1;
704 class EffectiveAddress<string opstr, RegisterOperand RO> :
705 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
706 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
707 let isCodeGenOnly = 1;
708 let DecoderMethod = "DecodeMem";
711 // Count Leading Ones/Zeros in Word
712 class CountLeading0<string opstr, RegisterOperand RO>:
713 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
714 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR>,
715 Requires<[HasBitCount, HasStdEnc]>;
717 class CountLeading1<string opstr, RegisterOperand RO>:
718 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
719 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR>,
720 Requires<[HasBitCount, HasStdEnc]>;
723 // Sign Extend in Register.
724 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
725 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
726 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR> {
727 let Predicates = [HasSEInReg, HasStdEnc];
731 class SubwordSwap<string opstr, RegisterOperand RO>:
732 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
734 let Predicates = [HasSwap, HasStdEnc];
735 let neverHasSideEffects = 1;
739 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
740 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
744 class ExtBase<string opstr, RegisterOperand RO>:
745 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
746 !strconcat(opstr, " $rt, $rs, $pos, $size"),
747 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
749 let Predicates = [HasMips32r2, HasStdEnc];
752 class InsBase<string opstr, RegisterOperand RO>:
753 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
754 !strconcat(opstr, " $rt, $rs, $pos, $size"),
755 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
757 let Predicates = [HasMips32r2, HasStdEnc];
758 let Constraints = "$src = $rt";
761 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
762 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
763 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
764 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
766 // Atomic Compare & Swap.
767 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
768 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
769 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
771 class LLBase<string opstr, RegisterOperand RO> :
772 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
773 [], NoItinerary, FrmI> {
774 let DecoderMethod = "DecodeMem";
778 class SCBase<string opstr, RegisterOperand RO> :
779 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
780 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
781 let DecoderMethod = "DecodeMem";
783 let Constraints = "$rt = $dst";
786 class MFC3OP<string asmstr, RegisterOperand RO> :
787 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
788 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
790 let isBarrier = 1, isTerminator = 1, isCodeGenOnly = 1 in
791 def TRAP : InstSE<(outs), (ins), "break", [(trap)], NoItinerary, FrmOther> {
792 let Inst = 0x0000000d;
795 //===----------------------------------------------------------------------===//
796 // Pseudo instructions
797 //===----------------------------------------------------------------------===//
800 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
801 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
803 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
804 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
805 [(callseq_start timm:$amt)]>;
806 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
807 [(callseq_end timm:$amt1, timm:$amt2)]>;
810 let usesCustomInserter = 1 in {
811 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
812 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
813 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
814 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
815 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
816 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
817 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
818 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
819 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
820 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
821 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
822 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
823 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
824 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
825 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
826 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
827 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
828 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
830 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
831 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
832 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
834 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
835 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
836 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
839 /// Pseudo instructions for loading and storing accumulator registers.
840 let isPseudo = 1, isCodeGenOnly = 1 in {
841 def LOAD_ACC64 : Load<"", ACC64>;
842 def STORE_ACC64 : Store<"", ACC64>;
845 //===----------------------------------------------------------------------===//
846 // Instruction definition
847 //===----------------------------------------------------------------------===//
848 //===----------------------------------------------------------------------===//
849 // MipsI Instructions
850 //===----------------------------------------------------------------------===//
852 /// Arithmetic Instructions (ALU Immediate)
853 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
855 ADDI_FM<0x9>, IsAsCheapAsAMove;
856 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
857 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
859 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
861 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
864 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
867 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
870 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
872 /// Arithmetic Instructions (3-Operand, R-Type)
873 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
875 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
877 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
879 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
880 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
881 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
882 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
883 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
885 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
887 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
889 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
891 /// Shift Instructions
892 def SLL : MMRel, shift_rotate_imm<"sll", shamt, GPR32Opnd, shl, immZExt5>,
894 def SRL : MMRel, shift_rotate_imm<"srl", shamt, GPR32Opnd, srl, immZExt5>,
896 def SRA : MMRel, shift_rotate_imm<"sra", shamt, GPR32Opnd, sra, immZExt5>,
898 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
899 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
900 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
902 // Rotate Instructions
903 let Predicates = [HasMips32r2, HasStdEnc] in {
904 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, GPR32Opnd, rotr,
907 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
911 /// Load and Store Instructions
913 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
914 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
916 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
918 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
919 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
921 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
922 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
923 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
925 /// load/store left/right
926 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd>, LW_FM<0x22>;
927 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd>, LW_FM<0x26>;
928 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd>, LW_FM<0x2a>;
929 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd>, LW_FM<0x2e>;
931 def SYNC : SYNC_FT, SYNC_FM;
932 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
933 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
934 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
935 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
936 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
937 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
939 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
940 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
941 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
942 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
943 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
944 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
946 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
947 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
949 def ERET : ER_FT<"eret">, ER_FM<0x18>;
950 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
952 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
953 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
955 def WAIT : WAIT_FT<"wait">;
957 /// Load-linked, Store-conditional
958 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
959 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
961 /// Jump and Branch Instructions
962 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
963 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
964 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
965 def B : UncondBranch<"b">, B_FM;
966 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
967 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
968 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
969 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
970 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
971 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
973 def JAL : JumpLink<"jal">, FJ<3>;
974 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
975 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
976 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
977 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
978 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
979 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
980 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
982 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
984 // Exception handling related node and instructions.
985 // The conversion sequence is:
986 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
987 // MIPSeh_return -> (stack change + indirect branch)
989 // MIPSeh_return takes the place of regular return instruction
990 // but takes two arguments (V1, V0) which are used for storing
991 // the offset and return address respectively.
992 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
994 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
995 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
997 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
998 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
999 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1000 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1002 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1005 /// Multiply and Divide Instructions.
1006 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1008 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1010 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1011 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1012 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1013 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1014 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1016 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1019 def MTHI : MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1020 def MTLO : MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1021 def MFHI : MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
1022 def MFLO : MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
1024 /// Sign Ext In Register Instructions.
1025 def SEB : SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1026 def SEH : SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1029 def CLZ : CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1030 def CLO : CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1032 /// Word Swap Bytes Within Halfwords
1033 def WSBH : SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1036 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1038 // FrameIndexes are legalized when they are operands from load/store
1039 // instructions. The same not happens for stack address copies, so an
1040 // add op with mem ComplexPattern is used and the stack address copy
1041 // can be matched. It's similar to Sparc LEA_ADDRi
1042 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1045 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1046 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1047 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1048 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1049 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1050 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1051 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1052 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1054 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1056 def EXT : ExtBase<"ext", GPR32Opnd>, EXT_FM<0>;
1057 def INS : InsBase<"ins", GPR32Opnd>, EXT_FM<4>;
1059 /// Move Control Registers From/To CPU Registers
1060 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1061 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1062 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1063 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1065 //===----------------------------------------------------------------------===//
1066 // Instruction aliases
1067 //===----------------------------------------------------------------------===//
1068 def : InstAlias<"move $dst, $src",
1069 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1070 Requires<[NotMips64]>;
1071 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1072 def : InstAlias<"addu $rs, $rt, $imm",
1073 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1074 def : InstAlias<"add $rs, $rt, $imm",
1075 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1076 def : InstAlias<"and $rs, $rt, $imm",
1077 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1078 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1079 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1080 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1081 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1082 def : InstAlias<"not $rt, $rs",
1083 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1084 def : InstAlias<"neg $rt, $rs",
1085 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1086 def : InstAlias<"negu $rt, $rs",
1087 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1088 def : InstAlias<"slt $rs, $rt, $imm",
1089 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1090 def : InstAlias<"xor $rs, $rt, $imm",
1091 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1092 def : InstAlias<"or $rs, $rt, $imm",
1093 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1094 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1095 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1096 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1097 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1098 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1099 def : InstAlias<"bnez $rs,$offset",
1100 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1101 def : InstAlias<"beqz $rs,$offset",
1102 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1103 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1105 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1106 def : InstAlias<"break", (BREAK 0, 0), 1>;
1107 def : InstAlias<"ei", (EI ZERO), 1>;
1108 def : InstAlias<"di", (DI ZERO), 1>;
1110 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1111 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1112 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1113 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1114 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1115 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1116 //===----------------------------------------------------------------------===//
1117 // Assembler Pseudo Instructions
1118 //===----------------------------------------------------------------------===//
1120 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1121 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1122 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1123 def LoadImm32Reg : LoadImm32<"li", shamt,GPR32Opnd>;
1125 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1126 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1127 !strconcat(instr_asm, "\t$rt, $addr")> ;
1128 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1130 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1131 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1132 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1133 def LoadAddr32Imm : LoadAddressImm<"la", shamt,GPR32Opnd>;
1137 //===----------------------------------------------------------------------===//
1138 // Arbitrary patterns that map to one or more instructions
1139 //===----------------------------------------------------------------------===//
1141 // Load/store pattern templates.
1142 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1143 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1145 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1146 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1149 def : MipsPat<(i32 immSExt16:$in),
1150 (ADDiu ZERO, imm:$in)>;
1151 def : MipsPat<(i32 immZExt16:$in),
1152 (ORi ZERO, imm:$in)>;
1153 def : MipsPat<(i32 immLow16Zero:$in),
1154 (LUi (HI16 imm:$in))>;
1156 // Arbitrary immediates
1157 def : MipsPat<(i32 imm:$imm),
1158 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1160 // Carry MipsPatterns
1161 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1162 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1163 let Predicates = [HasStdEnc, NotDSP] in {
1164 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1165 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1166 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1167 (ADDiu GPR32:$src, imm:$imm)>;
1171 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1172 (JAL tglobaladdr:$dst)>;
1173 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1174 (JAL texternalsym:$dst)>;
1175 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1176 // (JALR GPR32:$dst)>;
1179 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1180 (TAILCALL tglobaladdr:$dst)>;
1181 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1182 (TAILCALL texternalsym:$dst)>;
1184 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1185 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1186 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1187 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1188 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1189 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1191 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1192 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1193 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1194 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1195 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1196 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1198 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1199 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1200 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1201 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1202 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1203 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1204 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1205 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1206 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1207 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1210 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1211 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1212 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1213 (ADDiu GPR32:$gp, tconstpool:$in)>;
1216 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1217 MipsPat<(MipsWrapper RC:$gp, node:$in),
1218 (ADDiuOp RC:$gp, node:$in)>;
1220 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1221 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1222 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1223 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1224 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1225 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1227 // Mips does not have "not", so we expand our way
1228 def : MipsPat<(not GPR32:$in),
1229 (NOR GPR32Opnd:$in, ZERO)>;
1232 let Predicates = [HasStdEnc] in {
1233 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1234 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1235 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1239 let Predicates = [HasStdEnc] in
1240 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1243 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1244 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1245 Instruction SLTiuOp, Register ZEROReg> {
1246 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1247 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1248 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1249 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1251 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1252 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1253 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1254 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1255 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1256 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1257 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1258 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1259 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1260 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1261 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1262 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1264 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1265 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1266 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1267 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1269 def : MipsPat<(brcond RC:$cond, bb:$dst),
1270 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1273 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1275 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1276 (BLEZ i32:$lhs, bb:$dst)>;
1277 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1278 (BGEZ i32:$lhs, bb:$dst)>;
1281 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1282 Instruction SLTuOp, Register ZEROReg> {
1283 def : MipsPat<(seteq RC:$lhs, 0),
1284 (SLTiuOp RC:$lhs, 1)>;
1285 def : MipsPat<(setne RC:$lhs, 0),
1286 (SLTuOp ZEROReg, RC:$lhs)>;
1287 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1288 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1289 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1290 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1293 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1294 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1295 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1296 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1297 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1300 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1301 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1302 (SLTOp RC:$rhs, RC:$lhs)>;
1303 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1304 (SLTuOp RC:$rhs, RC:$lhs)>;
1307 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1308 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1309 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1310 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1311 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1314 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1315 Instruction SLTiuOp> {
1316 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1317 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1318 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1319 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1322 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1323 defm : SetlePats<GPR32, SLT, SLTu>;
1324 defm : SetgtPats<GPR32, SLT, SLTu>;
1325 defm : SetgePats<GPR32, SLT, SLTu>;
1326 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1329 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1331 // mflo/hi patterns.
1332 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1333 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1335 // Load halfword/word patterns.
1336 let AddedComplexity = 40 in {
1337 let Predicates = [HasStdEnc] in {
1338 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1339 def : LoadRegImmPat<LH, i32, sextloadi16>;
1340 def : LoadRegImmPat<LW, i32, load>;
1344 //===----------------------------------------------------------------------===//
1345 // Floating Point Support
1346 //===----------------------------------------------------------------------===//
1348 include "MipsInstrFPU.td"
1349 include "Mips64InstrInfo.td"
1350 include "MipsCondMov.td"
1355 include "Mips16InstrFormats.td"
1356 include "Mips16InstrInfo.td"
1359 include "MipsDSPInstrFormats.td"
1360 include "MipsDSPInstrInfo.td"
1363 include "MipsMSAInstrFormats.td"
1364 include "MipsMSAInstrInfo.td"
1367 include "MicroMipsInstrFormats.td"
1368 include "MicroMipsInstrInfo.td"