1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
253 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS4_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
271 //===----------------------------------------------------------------------===//
273 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
274 let EncodingPredicates = [HasStdEnc];
277 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
278 InstAlias<Asm, Result, Emit>, PredicateControl;
281 bit isCommutable = 1;
298 bit isTerminator = 1;
301 bit hasExtraSrcRegAllocReq = 1;
302 bit isCodeGenOnly = 1;
305 class IsAsCheapAsAMove {
306 bit isAsCheapAsAMove = 1;
309 class NeverHasSideEffects {
310 bit neverHasSideEffects = 1;
313 //===----------------------------------------------------------------------===//
314 // Instruction format superclass
315 //===----------------------------------------------------------------------===//
317 include "MipsInstrFormats.td"
319 //===----------------------------------------------------------------------===//
320 // Mips Operand, Complex Patterns and Transformations Definitions.
321 //===----------------------------------------------------------------------===//
323 def MipsJumpTargetAsmOperand : AsmOperandClass {
324 let Name = "JumpTarget";
325 let ParserMethod = "ParseJumpTarget";
326 let PredicateMethod = "isImm";
327 let RenderMethod = "addImmOperands";
330 // Instruction operand types
331 def jmptarget : Operand<OtherVT> {
332 let EncoderMethod = "getJumpTargetOpValue";
333 let ParserMatchClass = MipsJumpTargetAsmOperand;
335 def brtarget : Operand<OtherVT> {
336 let EncoderMethod = "getBranchTargetOpValue";
337 let OperandType = "OPERAND_PCREL";
338 let DecoderMethod = "DecodeBranchTarget";
339 let ParserMatchClass = MipsJumpTargetAsmOperand;
341 def calltarget : Operand<iPTR> {
342 let EncoderMethod = "getJumpTargetOpValue";
343 let ParserMatchClass = MipsJumpTargetAsmOperand;
346 def simm10 : Operand<i32>;
348 def simm16 : Operand<i32> {
349 let DecoderMethod= "DecodeSimm16";
352 def simm19_lsl2 : Operand<i32> {
353 let EncoderMethod = "getSimm19Lsl2Encoding";
354 let DecoderMethod = "DecodeSimm19Lsl2";
355 let ParserMatchClass = MipsJumpTargetAsmOperand;
358 def simm18_lsl3 : Operand<i32> {
359 let EncoderMethod = "getSimm18Lsl3Encoding";
360 let DecoderMethod = "DecodeSimm18Lsl3";
363 def simm20 : Operand<i32> {
366 def uimm20 : Operand<i32> {
369 def uimm10 : Operand<i32> {
372 def simm16_64 : Operand<i64> {
373 let DecoderMethod = "DecodeSimm16";
377 def uimmz : Operand<i32> {
378 let PrintMethod = "printUnsignedImm";
382 def uimm2 : Operand<i32> {
383 let PrintMethod = "printUnsignedImm";
386 def uimm3 : Operand<i32> {
387 let PrintMethod = "printUnsignedImm";
390 def uimm5 : Operand<i32> {
391 let PrintMethod = "printUnsignedImm";
394 def uimm6 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm16 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def pcrel16 : Operand<i32> {
405 def MipsMemAsmOperand : AsmOperandClass {
407 let ParserMethod = "parseMemOperand";
410 def MipsInvertedImmoperand : AsmOperandClass {
412 let RenderMethod = "addImmOperands";
413 let ParserMethod = "parseInvNum";
416 def InvertedImOperand : Operand<i32> {
417 let ParserMatchClass = MipsInvertedImmoperand;
420 def InvertedImOperand64 : Operand<i64> {
421 let ParserMatchClass = MipsInvertedImmoperand;
424 class mem_generic : Operand<iPTR> {
425 let PrintMethod = "printMemOperand";
426 let MIOperandInfo = (ops ptr_rc, simm16);
427 let EncoderMethod = "getMemEncoding";
428 let ParserMatchClass = MipsMemAsmOperand;
429 let OperandType = "OPERAND_MEMORY";
433 def mem : mem_generic;
435 // MSA specific address operand
436 def mem_msa : mem_generic {
437 let MIOperandInfo = (ops ptr_rc, simm10);
438 let EncoderMethod = "getMSAMemEncoding";
441 def mem_ea : Operand<iPTR> {
442 let PrintMethod = "printMemOperandEA";
443 let MIOperandInfo = (ops ptr_rc, simm16);
444 let EncoderMethod = "getMemEncoding";
445 let OperandType = "OPERAND_MEMORY";
448 def PtrRC : Operand<iPTR> {
449 let MIOperandInfo = (ops ptr_rc);
450 let DecoderMethod = "DecodePtrRegisterClass";
451 let ParserMatchClass = GPR32AsmOperand;
454 // size operand of ext instruction
455 def size_ext : Operand<i32> {
456 let EncoderMethod = "getSizeExtEncoding";
457 let DecoderMethod = "DecodeExtSize";
460 // size operand of ins instruction
461 def size_ins : Operand<i32> {
462 let EncoderMethod = "getSizeInsEncoding";
463 let DecoderMethod = "DecodeInsSize";
466 // Transformation Function - get the lower 16 bits.
467 def LO16 : SDNodeXForm<imm, [{
468 return getImm(N, N->getZExtValue() & 0xFFFF);
471 // Transformation Function - get the higher 16 bits.
472 def HI16 : SDNodeXForm<imm, [{
473 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
477 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
479 // Node immediate is zero (e.g. insve.d)
480 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
482 // Node immediate fits as 16-bit sign extended on target immediate.
484 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
486 // Node immediate fits as 16-bit sign extended on target immediate.
488 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
490 // Node immediate fits as 15-bit sign extended on target immediate.
492 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
494 // Node immediate fits as 16-bit zero extended on target immediate.
495 // The LO16 param means that only the lower 16 bits of the node
496 // immediate are caught.
498 def immZExt16 : PatLeaf<(imm), [{
499 if (N->getValueType(0) == MVT::i32)
500 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
502 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
505 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
506 def immLow16Zero : PatLeaf<(imm), [{
507 int64_t Val = N->getSExtValue();
508 return isInt<32>(Val) && !(Val & 0xffff);
511 // shamt field must fit in 5 bits.
512 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
514 // True if (N + 1) fits in 16-bit field.
515 def immSExt16Plus1 : PatLeaf<(imm), [{
516 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
519 // Mips Address Mode! SDNode frameindex could possibily be a match
520 // since load and store instructions from stack used it.
522 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
525 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
528 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
531 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
533 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
535 //===----------------------------------------------------------------------===//
536 // Instructions specific format
537 //===----------------------------------------------------------------------===//
539 // Arithmetic and logical instructions with 3 register operands.
540 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
541 InstrItinClass Itin = NoItinerary,
542 SDPatternOperator OpNode = null_frag>:
543 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
544 !strconcat(opstr, "\t$rd, $rs, $rt"),
545 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
546 let isCommutable = isComm;
547 let isReMaterializable = 1;
548 let TwoOperandAliasConstraint = "$rd = $rs";
551 // Arithmetic and logical instructions with 2 register operands.
552 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
553 InstrItinClass Itin = NoItinerary,
554 SDPatternOperator imm_type = null_frag,
555 SDPatternOperator OpNode = null_frag> :
556 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
557 !strconcat(opstr, "\t$rt, $rs, $imm16"),
558 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
560 let isReMaterializable = 1;
561 let TwoOperandAliasConstraint = "$rs = $rt";
564 // Arithmetic Multiply ADD/SUB
565 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
566 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
567 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
568 let Defs = [HI0, LO0];
569 let Uses = [HI0, LO0];
570 let isCommutable = isComm;
574 class LogicNOR<string opstr, RegisterOperand RO>:
575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
576 !strconcat(opstr, "\t$rd, $rs, $rt"),
577 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
578 let isCommutable = 1;
582 class shift_rotate_imm<string opstr, Operand ImmOpnd,
583 RegisterOperand RO, InstrItinClass itin,
584 SDPatternOperator OpNode = null_frag,
585 SDPatternOperator PF = null_frag> :
586 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
587 !strconcat(opstr, "\t$rd, $rt, $shamt"),
588 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
589 let TwoOperandAliasConstraint = "$rt = $rd";
592 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
593 SDPatternOperator OpNode = null_frag>:
594 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
595 !strconcat(opstr, "\t$rd, $rt, $rs"),
596 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
599 // Load Upper Imediate
600 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
601 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
602 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
603 let neverHasSideEffects = 1;
604 let isReMaterializable = 1;
608 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
609 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
610 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
611 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
612 let DecoderMethod = "DecodeMem";
613 let canFoldAsLoad = 1;
617 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
618 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
619 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
620 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
621 let DecoderMethod = "DecodeMem";
625 // Load/Store Left/Right
626 let canFoldAsLoad = 1 in
627 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
628 InstrItinClass Itin> :
629 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
630 !strconcat(opstr, "\t$rt, $addr"),
631 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
632 let DecoderMethod = "DecodeMem";
633 string Constraints = "$src = $rt";
636 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
637 InstrItinClass Itin> :
638 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
639 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
640 let DecoderMethod = "DecodeMem";
643 // Conditional Branch
644 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
645 RegisterOperand RO> :
646 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
647 !strconcat(opstr, "\t$rs, $rt, $offset"),
648 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
651 let isTerminator = 1;
652 let hasDelaySlot = 1;
656 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
657 RegisterOperand RO> :
658 InstSE<(outs), (ins RO:$rs, opnd:$offset),
659 !strconcat(opstr, "\t$rs, $offset"),
660 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
663 let isTerminator = 1;
664 let hasDelaySlot = 1;
669 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
670 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
671 !strconcat(opstr, "\t$rd, $rs, $rt"),
672 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
673 II_SLT_SLTU, FrmR, opstr>;
675 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
677 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
678 !strconcat(opstr, "\t$rt, $rs, $imm16"),
679 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
680 II_SLTI_SLTIU, FrmI, opstr>;
683 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
684 SDPatternOperator targetoperator, string bopstr> :
685 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
686 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
689 let hasDelaySlot = 1;
690 let DecoderMethod = "DecodeJumpTarget";
694 // Unconditional branch
695 class UncondBranch<Instruction BEQInst> :
696 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
697 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
699 let isTerminator = 1;
701 let hasDelaySlot = 1;
702 let AdditionalPredicates = [RelocPIC];
706 // Base class for indirect branch and return instruction classes.
707 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
708 class JumpFR<string opstr, RegisterOperand RO,
709 SDPatternOperator operator = null_frag>:
710 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
714 class IndirectBranch<string opstr, RegisterOperand RO> :
715 JumpFR<opstr, RO, brind> {
717 let isIndirectBranch = 1;
720 // Return instruction
721 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
723 let isCodeGenOnly = 1;
725 let hasExtraSrcRegAllocReq = 1;
728 // Jump and Link (Call)
729 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
730 class JumpLink<string opstr, DAGOperand opnd> :
731 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
732 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
733 let DecoderMethod = "DecodeJumpTarget";
736 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
737 Register RetReg, RegisterOperand ResRO = RO>:
738 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
739 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
741 class JumpLinkReg<string opstr, RegisterOperand RO>:
742 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
745 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
746 InstSE<(outs), (ins RO:$rs, opnd:$offset),
747 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
751 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
752 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
753 class TailCall<Instruction JumpInst> :
754 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
755 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
757 class TailCallReg<RegisterOperand RO, Instruction JRInst,
758 RegisterOperand ResRO = RO> :
759 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
760 PseudoInstExpansion<(JRInst ResRO:$rs)>;
763 class BAL_BR_Pseudo<Instruction RealInst> :
764 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
765 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
767 let isTerminator = 1;
769 let hasDelaySlot = 1;
774 class SYS_FT<string opstr> :
775 InstSE<(outs), (ins uimm20:$code_),
776 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
778 class BRK_FT<string opstr> :
779 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
780 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
784 class ER_FT<string opstr> :
785 InstSE<(outs), (ins),
786 opstr, [], NoItinerary, FrmOther, opstr>;
789 class DEI_FT<string opstr, RegisterOperand RO> :
790 InstSE<(outs RO:$rt), (ins),
791 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
794 class WAIT_FT<string opstr> :
795 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
798 let hasSideEffects = 1 in
799 class SYNC_FT<string opstr> :
800 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
801 NoItinerary, FrmOther, opstr>;
803 let hasSideEffects = 1 in
804 class TEQ_FT<string opstr, RegisterOperand RO> :
805 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
806 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
809 class TEQI_FT<string opstr, RegisterOperand RO> :
810 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
811 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
813 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
814 list<Register> DefRegs> :
815 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
817 let isCommutable = 1;
819 let neverHasSideEffects = 1;
822 // Pseudo multiply/divide instruction with explicit accumulator register
824 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
825 SDPatternOperator OpNode, InstrItinClass Itin,
826 bit IsComm = 1, bit HasSideEffects = 0,
827 bit UsesCustomInserter = 0> :
828 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
829 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
830 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
831 let isCommutable = IsComm;
832 let hasSideEffects = HasSideEffects;
833 let usesCustomInserter = UsesCustomInserter;
836 // Pseudo multiply add/sub instruction with explicit accumulator register
838 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
840 : PseudoSE<(outs ACC64:$ac),
841 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
843 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
845 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
846 string Constraints = "$acin = $ac";
849 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
850 list<Register> DefRegs> :
851 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
852 [], itin, FrmR, opstr> {
857 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
858 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
859 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
861 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
862 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
865 let neverHasSideEffects = 1;
868 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
869 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
870 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
873 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
874 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
877 let neverHasSideEffects = 1;
880 class EffectiveAddress<string opstr, RegisterOperand RO> :
881 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
882 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
883 !strconcat(opstr, "_lea")> {
884 let isCodeGenOnly = 1;
885 let DecoderMethod = "DecodeMem";
888 // Count Leading Ones/Zeros in Word
889 class CountLeading0<string opstr, RegisterOperand RO>:
890 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
891 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
893 class CountLeading1<string opstr, RegisterOperand RO>:
894 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
895 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
897 // Sign Extend in Register.
898 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
899 InstrItinClass itin> :
900 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
901 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
904 class SubwordSwap<string opstr, RegisterOperand RO>:
905 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
906 NoItinerary, FrmR, opstr> {
907 let neverHasSideEffects = 1;
911 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
912 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
916 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
917 SDPatternOperator Op = null_frag>:
918 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
919 !strconcat(opstr, " $rt, $rs, $pos, $size"),
920 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
921 FrmR, opstr>, ISA_MIPS32R2;
923 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
924 SDPatternOperator Op = null_frag>:
925 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
926 !strconcat(opstr, " $rt, $rs, $pos, $size"),
927 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
928 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
929 let Constraints = "$src = $rt";
932 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
933 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
934 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
935 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
937 // Atomic Compare & Swap.
938 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
939 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
940 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
942 class LLBase<string opstr, RegisterOperand RO> :
943 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
944 [], NoItinerary, FrmI> {
945 let DecoderMethod = "DecodeMem";
949 class SCBase<string opstr, RegisterOperand RO> :
950 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
951 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
952 let DecoderMethod = "DecodeMem";
954 let Constraints = "$rt = $dst";
957 class MFC3OP<string asmstr, RegisterOperand RO> :
958 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
959 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
961 class TrapBase<Instruction RealInst>
962 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
963 PseudoInstExpansion<(RealInst 0, 0)> {
965 let isTerminator = 1;
966 let isCodeGenOnly = 1;
969 //===----------------------------------------------------------------------===//
970 // Pseudo instructions
971 //===----------------------------------------------------------------------===//
974 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
975 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
977 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
978 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
979 [(callseq_start timm:$amt)]>;
980 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
981 [(callseq_end timm:$amt1, timm:$amt2)]>;
984 let usesCustomInserter = 1 in {
985 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
986 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
987 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
988 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
989 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
990 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
991 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
992 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
993 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
994 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
995 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
996 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
997 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
998 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
999 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1000 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1001 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1002 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1004 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1005 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1006 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1008 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1009 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1010 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1013 /// Pseudo instructions for loading and storing accumulator registers.
1014 let isPseudo = 1, isCodeGenOnly = 1 in {
1015 def LOAD_ACC64 : Load<"", ACC64>;
1016 def STORE_ACC64 : Store<"", ACC64>;
1019 // We need these two pseudo instructions to avoid offset calculation for long
1020 // branches. See the comment in file MipsLongBranch.cpp for detailed
1023 // Expands to: lui $dst, %hi($tgt - $baltgt)
1024 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1025 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1027 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1028 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1029 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1031 //===----------------------------------------------------------------------===//
1032 // Instruction definition
1033 //===----------------------------------------------------------------------===//
1034 //===----------------------------------------------------------------------===//
1035 // MipsI Instructions
1036 //===----------------------------------------------------------------------===//
1038 /// Arithmetic Instructions (ALU Immediate)
1039 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1041 ADDI_FM<0x9>, IsAsCheapAsAMove;
1042 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1043 ISA_MIPS1_NOT_32R6_64R6;
1044 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1046 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1048 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1051 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1054 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1057 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1059 /// Arithmetic Instructions (3-Operand, R-Type)
1060 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1062 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1064 let Defs = [HI0, LO0] in
1065 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1066 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1067 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1068 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1069 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1070 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1071 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1073 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1075 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1077 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1079 /// Shift Instructions
1080 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1081 immZExt5>, SRA_FM<0, 0>;
1082 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1083 immZExt5>, SRA_FM<2, 0>;
1084 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1085 immZExt5>, SRA_FM<3, 0>;
1086 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1088 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1090 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1093 // Rotate Instructions
1094 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1096 SRA_FM<2, 1>, ISA_MIPS32R2;
1097 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1098 SRLV_FM<6, 1>, ISA_MIPS32R2;
1100 /// Load and Store Instructions
1102 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1103 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1105 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1107 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1108 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1110 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1111 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1112 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1114 /// load/store left/right
1115 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1116 AdditionalPredicates = [NotInMicroMips] in {
1117 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1118 ISA_MIPS1_NOT_32R6_64R6;
1119 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1120 ISA_MIPS1_NOT_32R6_64R6;
1121 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1122 ISA_MIPS1_NOT_32R6_64R6;
1123 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1124 ISA_MIPS1_NOT_32R6_64R6;
1127 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1128 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1129 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1130 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1131 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1132 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1133 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1135 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1136 ISA_MIPS2_NOT_32R6_64R6;
1137 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1138 ISA_MIPS2_NOT_32R6_64R6;
1139 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1140 ISA_MIPS2_NOT_32R6_64R6;
1141 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1142 ISA_MIPS2_NOT_32R6_64R6;
1143 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1144 ISA_MIPS2_NOT_32R6_64R6;
1145 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1146 ISA_MIPS2_NOT_32R6_64R6;
1148 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1149 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1150 def TRAP : TrapBase<BREAK>;
1152 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1153 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1155 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1156 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1158 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1159 AdditionalPredicates = [NotInMicroMips] in {
1160 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1162 /// Load-linked, Store-conditional
1163 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1164 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1167 /// Jump and Branch Instructions
1168 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1169 AdditionalRequires<[RelocStatic]>, IsBranch;
1170 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1171 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1172 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1173 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1175 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1177 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1179 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1181 def B : UncondBranch<BEQ>;
1183 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1184 let AdditionalPredicates = [NotInMicroMips] in {
1185 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1186 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1189 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1190 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1191 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1192 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1193 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1194 def TAILCALL : TailCall<J>;
1195 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1197 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1199 // Exception handling related node and instructions.
1200 // The conversion sequence is:
1201 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1202 // MIPSeh_return -> (stack change + indirect branch)
1204 // MIPSeh_return takes the place of regular return instruction
1205 // but takes two arguments (V1, V0) which are used for storing
1206 // the offset and return address respectively.
1207 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1209 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1210 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1212 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1213 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1214 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1215 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1217 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1220 /// Multiply and Divide Instructions.
1221 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1222 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1223 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1224 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1225 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1226 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1227 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1228 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1230 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1231 ISA_MIPS1_NOT_32R6_64R6;
1232 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1233 ISA_MIPS1_NOT_32R6_64R6;
1234 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1235 AdditionalPredicates = [NotInMicroMips] in {
1236 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1237 ISA_MIPS1_NOT_32R6_64R6;
1238 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1239 ISA_MIPS1_NOT_32R6_64R6;
1242 /// Sign Ext In Register Instructions.
1243 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1244 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1245 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1246 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1249 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1250 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1252 /// Word Swap Bytes Within Halfwords
1253 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1256 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1258 // FrameIndexes are legalized when they are operands from load/store
1259 // instructions. The same not happens for stack address copies, so an
1260 // add op with mem ComplexPattern is used and the stack address copy
1261 // can be matched. It's similar to Sparc LEA_ADDRi
1262 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1265 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1266 ISA_MIPS32_NOT_32R6_64R6;
1267 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1268 ISA_MIPS32_NOT_32R6_64R6;
1269 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1270 ISA_MIPS32_NOT_32R6_64R6;
1271 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1272 ISA_MIPS32_NOT_32R6_64R6;
1274 let AdditionalPredicates = [NotDSP] in {
1275 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1276 ISA_MIPS1_NOT_32R6_64R6;
1277 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1278 ISA_MIPS1_NOT_32R6_64R6;
1279 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1280 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1281 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1282 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1283 ISA_MIPS32_NOT_32R6_64R6;
1284 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1285 ISA_MIPS32_NOT_32R6_64R6;
1286 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1287 ISA_MIPS32_NOT_32R6_64R6;
1288 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1289 ISA_MIPS32_NOT_32R6_64R6;
1292 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1293 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1294 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1295 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1297 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1299 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1300 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1302 /// Move Control Registers From/To CPU Registers
1303 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1304 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1305 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1306 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1308 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1310 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1311 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1312 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1314 // JR_HB and JALR_HB are defined here using the new style naming
1315 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1316 // and because of that it doesn't follow the naming convention of the
1317 // rest of the file. To avoid a mixture of old vs new style, the new
1318 // style was chosen.
1319 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1320 dag OutOperandList = (outs);
1321 dag InOperandList = (ins GPROpnd:$rs);
1322 string AsmString = !strconcat(instr_asm, "\t$rs");
1323 list<dag> Pattern = [];
1326 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1327 dag OutOperandList = (outs GPROpnd:$rd);
1328 dag InOperandList = (ins GPROpnd:$rs);
1329 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1330 list<dag> Pattern = [];
1333 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1334 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1336 let isIndirectBranch=1;
1342 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1343 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1344 let isIndirectBranch=1;
1348 class JR_HB_ENC : JR_HB_FM<8>;
1349 class JALR_HB_ENC : JALR_HB_FM<9>;
1351 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1352 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1354 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1356 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1357 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1358 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1359 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1361 //===----------------------------------------------------------------------===//
1362 // Instruction aliases
1363 //===----------------------------------------------------------------------===//
1364 def : MipsInstAlias<"move $dst, $src",
1365 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1367 let AdditionalPredicates = [NotInMicroMips];
1369 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1370 def : MipsInstAlias<"addu $rs, $rt, $imm",
1371 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1372 def : MipsInstAlias<"add $rs, $rt, $imm",
1373 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1374 def : MipsInstAlias<"and $rs, $rt, $imm",
1375 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1376 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1377 let Predicates = [NotInMicroMips] in {
1378 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1380 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1381 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1382 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1383 def : MipsInstAlias<"not $rt, $rs",
1384 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1385 def : MipsInstAlias<"neg $rt, $rs",
1386 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1387 def : MipsInstAlias<"negu $rt",
1388 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1389 def : MipsInstAlias<"negu $rt, $rs",
1390 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1391 def : MipsInstAlias<"slt $rs, $rt, $imm",
1392 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1393 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1394 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1395 def : MipsInstAlias<"xor $rs, $rt, $imm",
1396 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1397 def : MipsInstAlias<"or $rs, $rt, $imm",
1398 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1399 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1400 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1401 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1402 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1403 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1404 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1405 def : MipsInstAlias<"bnez $rs,$offset",
1406 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1407 def : MipsInstAlias<"beqz $rs,$offset",
1408 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1409 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1411 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1412 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1413 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1414 def : MipsInstAlias<"di", (DI ZERO), 1>;
1416 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1417 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1418 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1420 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1421 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1423 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1424 def : MipsInstAlias<"sll $rd, $rt, $rs",
1425 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1426 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1427 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1428 InvertedImOperand:$imm), 0>;
1429 def : MipsInstAlias<"sub $rs, $imm",
1430 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1432 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1433 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1434 InvertedImOperand:$imm), 0>;
1435 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1436 InvertedImOperand:$imm), 0>;
1437 def : MipsInstAlias<"sra $rd, $rt, $rs",
1438 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1439 def : MipsInstAlias<"srl $rd, $rt, $rs",
1440 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1441 //===----------------------------------------------------------------------===//
1442 // Assembler Pseudo Instructions
1443 //===----------------------------------------------------------------------===//
1445 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1446 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1447 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1448 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1450 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1451 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1452 !strconcat(instr_asm, "\t$rt, $addr")> ;
1453 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1455 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1456 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1457 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1458 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1460 //===----------------------------------------------------------------------===//
1461 // Arbitrary patterns that map to one or more instructions
1462 //===----------------------------------------------------------------------===//
1464 // Load/store pattern templates.
1465 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1466 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1468 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1469 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1472 def : MipsPat<(i32 immSExt16:$in),
1473 (ADDiu ZERO, imm:$in)>;
1474 def : MipsPat<(i32 immZExt16:$in),
1475 (ORi ZERO, imm:$in)>;
1476 def : MipsPat<(i32 immLow16Zero:$in),
1477 (LUi (HI16 imm:$in))>;
1479 // Arbitrary immediates
1480 def : MipsPat<(i32 imm:$imm),
1481 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1483 // Carry MipsPatterns
1484 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1485 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1486 let AdditionalPredicates = [NotDSP] in {
1487 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1488 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1489 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1490 (ADDiu GPR32:$src, imm:$imm)>;
1494 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1495 (JAL tglobaladdr:$dst)>;
1496 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1497 (JAL texternalsym:$dst)>;
1498 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1499 // (JALR GPR32:$dst)>;
1502 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1503 (TAILCALL tglobaladdr:$dst)>;
1504 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1505 (TAILCALL texternalsym:$dst)>;
1507 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1508 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1509 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1510 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1511 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1512 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1514 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1515 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1516 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1517 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1518 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1519 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1521 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1522 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1523 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1524 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1525 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1526 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1527 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1528 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1529 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1530 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1533 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1534 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1535 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1536 (ADDiu GPR32:$gp, tconstpool:$in)>;
1539 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1540 MipsPat<(MipsWrapper RC:$gp, node:$in),
1541 (ADDiuOp RC:$gp, node:$in)>;
1543 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1544 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1545 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1546 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1547 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1548 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1550 // Mips does not have "not", so we expand our way
1551 def : MipsPat<(not GPR32:$in),
1552 (NOR GPR32Opnd:$in, ZERO)>;
1555 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1556 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1557 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1560 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1563 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1564 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1565 Instruction SLTiuOp, Register ZEROReg> {
1566 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1567 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1568 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1569 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1571 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1572 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1573 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1574 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1575 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1576 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1577 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1578 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1579 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1580 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1581 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1582 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1584 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1585 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1586 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1587 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1589 def : MipsPat<(brcond RC:$cond, bb:$dst),
1590 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1593 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1595 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1596 (BLEZ i32:$lhs, bb:$dst)>;
1597 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1598 (BGEZ i32:$lhs, bb:$dst)>;
1601 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1602 Instruction SLTuOp, Register ZEROReg> {
1603 def : MipsPat<(seteq RC:$lhs, 0),
1604 (SLTiuOp RC:$lhs, 1)>;
1605 def : MipsPat<(setne RC:$lhs, 0),
1606 (SLTuOp ZEROReg, RC:$lhs)>;
1607 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1608 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1609 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1610 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1613 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1614 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1615 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1616 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1617 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1620 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1621 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1622 (SLTOp RC:$rhs, RC:$lhs)>;
1623 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1624 (SLTuOp RC:$rhs, RC:$lhs)>;
1627 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1628 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1629 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1630 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1631 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1634 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1635 Instruction SLTiuOp> {
1636 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1637 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1638 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1639 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1642 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1643 defm : SetlePats<GPR32, SLT, SLTu>;
1644 defm : SetgtPats<GPR32, SLT, SLTu>;
1645 defm : SetgePats<GPR32, SLT, SLTu>;
1646 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1649 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1651 // Load halfword/word patterns.
1652 let AddedComplexity = 40 in {
1653 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1654 def : LoadRegImmPat<LH, i32, sextloadi16>;
1655 def : LoadRegImmPat<LW, i32, load>;
1658 //===----------------------------------------------------------------------===//
1659 // Floating Point Support
1660 //===----------------------------------------------------------------------===//
1662 include "MipsInstrFPU.td"
1663 include "Mips64InstrInfo.td"
1664 include "MipsCondMov.td"
1666 include "Mips32r6InstrInfo.td"
1667 include "Mips64r6InstrInfo.td"
1672 include "Mips16InstrFormats.td"
1673 include "Mips16InstrInfo.td"
1676 include "MipsDSPInstrFormats.td"
1677 include "MipsDSPInstrInfo.td"
1680 include "MipsMSAInstrFormats.td"
1681 include "MipsMSAInstrInfo.td"
1684 include "MicroMipsInstrFormats.td"
1685 include "MicroMipsInstrInfo.td"
1686 include "MicroMipsInstrFPU.td"