1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
20 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
21 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
26 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
27 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
28 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
31 def SDT_MipsDivRem : SDTypeProfile<0, 2,
35 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
37 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
39 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
41 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
43 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
47 def SDTMipsLoadLR : SDTypeProfile<1, 2,
48 [SDTCisInt<0>, SDTCisPtrTy<1>,
52 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 // Hi and Lo nodes are used to handle global addresses. Used on
57 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
58 // static model. (nothing to do with Mips Registers Hi and Lo)
59 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
60 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
61 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
63 // TlsGd node is used to handle General Dynamic TLS
64 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
66 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
67 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
68 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
71 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
74 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
85 [SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
88 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
89 [SDNPOptInGlue, SDNPOutGlue]>;
90 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
91 [SDNPOptInGlue, SDNPOutGlue]>;
94 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
96 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
99 // Target constant nodes that are not part of any isel patterns and remain
100 // unchanged can cause instructions with illegal operands to be emitted.
101 // Wrapper node patterns give the instruction selector a chance to replace
102 // target constant nodes that would otherwise remain unchanged with ADDiu
103 // nodes. Without these wrapper node patterns, the following conditional move
104 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
106 // movn %got(d)($gp), %got(c)($gp), $4
107 // This instruction is illegal since movn can take only register operands.
109 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
111 // Pointer to dynamically allocated stack area.
112 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
113 [SDNPHasChain, SDNPInGlue]>;
115 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
117 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
118 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
120 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
123 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
124 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
126 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
127 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
128 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 //===----------------------------------------------------------------------===//
138 // Mips Instruction Predicate Definitions.
139 //===----------------------------------------------------------------------===//
140 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
141 AssemblerPredicate<"FeatureSEInReg">;
142 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
143 AssemblerPredicate<"FeatureBitCount">;
144 def HasSwap : Predicate<"Subtarget.hasSwap()">,
145 AssemblerPredicate<"FeatureSwap">;
146 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
147 AssemblerPredicate<"FeatureCondMov">;
148 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
149 AssemblerPredicate<"FeatureMips32">;
150 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
151 AssemblerPredicate<"FeatureMips32r2">;
152 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
153 AssemblerPredicate<"FeatureMips64">;
154 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
155 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
156 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
157 AssemblerPredicate<"!FeatureMips64">;
158 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
159 AssemblerPredicate<"FeatureMips64r2">;
160 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
161 AssemblerPredicate<"FeatureN64">;
162 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
163 AssemblerPredicate<"!FeatureN64">;
164 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
165 AssemblerPredicate<"FeatureMips16">;
166 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
167 AssemblerPredicate<"FeatureMips32">;
168 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
169 AssemblerPredicate<"FeatureMips32">;
170 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
171 AssemblerPredicate<"FeatureMips32">;
172 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
173 AssemblerPredicate<"!FeatureMips16">;
175 //===----------------------------------------------------------------------===//
176 // Instruction format superclass
177 //===----------------------------------------------------------------------===//
179 include "MipsInstrFormats.td"
181 //===----------------------------------------------------------------------===//
182 // Mips Operand, Complex Patterns and Transformations Definitions.
183 //===----------------------------------------------------------------------===//
185 // Instruction operand types
186 def jmptarget : Operand<OtherVT> {
187 let EncoderMethod = "getJumpTargetOpValue";
189 def brtarget : Operand<OtherVT> {
190 let EncoderMethod = "getBranchTargetOpValue";
191 let OperandType = "OPERAND_PCREL";
192 let DecoderMethod = "DecodeBranchTarget";
194 def calltarget : Operand<iPTR> {
195 let EncoderMethod = "getJumpTargetOpValue";
197 def calltarget64: Operand<i64>;
198 def simm16 : Operand<i32> {
199 let DecoderMethod= "DecodeSimm16";
201 def simm16_64 : Operand<i64>;
202 def shamt : Operand<i32>;
205 def uimm16 : Operand<i32> {
206 let PrintMethod = "printUnsignedImm";
210 def mem : Operand<i32> {
211 let PrintMethod = "printMemOperand";
212 let MIOperandInfo = (ops CPURegs, simm16);
213 let EncoderMethod = "getMemEncoding";
216 def mem64 : Operand<i64> {
217 let PrintMethod = "printMemOperand";
218 let MIOperandInfo = (ops CPU64Regs, simm16_64);
221 def mem_ea : Operand<i32> {
222 let PrintMethod = "printMemOperandEA";
223 let MIOperandInfo = (ops CPURegs, simm16);
224 let EncoderMethod = "getMemEncoding";
227 def mem_ea_64 : Operand<i64> {
228 let PrintMethod = "printMemOperandEA";
229 let MIOperandInfo = (ops CPU64Regs, simm16_64);
230 let EncoderMethod = "getMemEncoding";
233 // size operand of ext instruction
234 def size_ext : Operand<i32> {
235 let EncoderMethod = "getSizeExtEncoding";
236 let DecoderMethod = "DecodeExtSize";
239 // size operand of ins instruction
240 def size_ins : Operand<i32> {
241 let EncoderMethod = "getSizeInsEncoding";
242 let DecoderMethod = "DecodeInsSize";
245 // Transformation Function - get the lower 16 bits.
246 def LO16 : SDNodeXForm<imm, [{
247 return getImm(N, N->getZExtValue() & 0xFFFF);
250 // Transformation Function - get the higher 16 bits.
251 def HI16 : SDNodeXForm<imm, [{
252 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
255 // Node immediate fits as 16-bit sign extended on target immediate.
257 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
259 // Node immediate fits as 16-bit zero extended on target immediate.
260 // The LO16 param means that only the lower 16 bits of the node
261 // immediate are caught.
263 def immZExt16 : PatLeaf<(imm), [{
264 if (N->getValueType(0) == MVT::i32)
265 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
267 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
270 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
271 def immLow16Zero : PatLeaf<(imm), [{
272 int64_t Val = N->getSExtValue();
273 return isInt<32>(Val) && !(Val & 0xffff);
276 // shamt field must fit in 5 bits.
277 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
279 // Mips Address Mode! SDNode frameindex could possibily be a match
280 // since load and store instructions from stack used it.
282 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
284 //===----------------------------------------------------------------------===//
285 // Pattern fragment for load/store
286 //===----------------------------------------------------------------------===//
287 class UnalignedLoad<PatFrag Node> :
288 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
289 LoadSDNode *LD = cast<LoadSDNode>(N);
290 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
293 class AlignedLoad<PatFrag Node> :
294 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
295 LoadSDNode *LD = cast<LoadSDNode>(N);
296 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
299 class UnalignedStore<PatFrag Node> :
300 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
301 StoreSDNode *SD = cast<StoreSDNode>(N);
302 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
305 class AlignedStore<PatFrag Node> :
306 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
307 StoreSDNode *SD = cast<StoreSDNode>(N);
308 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
311 // Load/Store PatFrags.
312 def sextloadi16_a : AlignedLoad<sextloadi16>;
313 def zextloadi16_a : AlignedLoad<zextloadi16>;
314 def extloadi16_a : AlignedLoad<extloadi16>;
315 def load_a : AlignedLoad<load>;
316 def sextloadi32_a : AlignedLoad<sextloadi32>;
317 def zextloadi32_a : AlignedLoad<zextloadi32>;
318 def extloadi32_a : AlignedLoad<extloadi32>;
319 def truncstorei16_a : AlignedStore<truncstorei16>;
320 def store_a : AlignedStore<store>;
321 def truncstorei32_a : AlignedStore<truncstorei32>;
322 def sextloadi16_u : UnalignedLoad<sextloadi16>;
323 def zextloadi16_u : UnalignedLoad<zextloadi16>;
324 def extloadi16_u : UnalignedLoad<extloadi16>;
325 def load_u : UnalignedLoad<load>;
326 def sextloadi32_u : UnalignedLoad<sextloadi32>;
327 def zextloadi32_u : UnalignedLoad<zextloadi32>;
328 def extloadi32_u : UnalignedLoad<extloadi32>;
329 def truncstorei16_u : UnalignedStore<truncstorei16>;
330 def store_u : UnalignedStore<store>;
331 def truncstorei32_u : UnalignedStore<truncstorei32>;
333 //===----------------------------------------------------------------------===//
334 // Instructions specific format
335 //===----------------------------------------------------------------------===//
337 // Arithmetic and logical instructions with 3 register operands.
338 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
339 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
340 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
341 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
342 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
344 let isCommutable = isComm;
345 let isReMaterializable = 1;
348 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
349 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
350 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
351 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
353 let isCommutable = isComm;
356 // Arithmetic and logical instructions with 2 register operands.
357 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
358 Operand Od, PatLeaf imm_type, RegisterClass RC> :
359 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
360 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
361 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
362 let isReMaterializable = 1;
365 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
366 Operand Od, PatLeaf imm_type, RegisterClass RC> :
367 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
368 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
370 // Arithmetic Multiply ADD/SUB
371 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
372 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
373 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
374 !strconcat(instr_asm, "\t$rs, $rt"),
375 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
378 let isCommutable = isComm;
382 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
383 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
384 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
385 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
387 let isCommutable = 1;
391 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
392 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
394 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
395 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
396 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
400 // 32-bit shift instructions.
401 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
403 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
405 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
406 SDNode OpNode, RegisterClass RC>:
407 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
408 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
409 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
410 let shamt = isRotate;
413 // Load Upper Imediate
414 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
415 FI<op, (outs RC:$rt), (ins Imm:$imm16),
416 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
418 let neverHasSideEffects = 1;
419 let isReMaterializable = 1;
422 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
423 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
425 let Inst{25-21} = addr{20-16};
426 let Inst{15-0} = addr{15-0};
427 let DecoderMethod = "DecodeMem";
431 let canFoldAsLoad = 1 in
432 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
433 Operand MemOpnd, bit Pseudo>:
434 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
435 !strconcat(instr_asm, "\t$rt, $addr"),
436 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
437 let isPseudo = Pseudo;
440 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
441 Operand MemOpnd, bit Pseudo>:
442 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
443 !strconcat(instr_asm, "\t$rt, $addr"),
444 [(OpNode RC:$rt, addr:$addr)], IIStore> {
445 let isPseudo = Pseudo;
449 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
451 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
452 Requires<[NotN64, HasStandardEncoding]>;
453 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
454 Requires<[IsN64, HasStandardEncoding]> {
455 let DecoderNamespace = "Mips64";
456 let isCodeGenOnly = 1;
461 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
463 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
464 Requires<[NotN64, HasStandardEncoding]>;
465 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
466 Requires<[IsN64, HasStandardEncoding]> {
467 let DecoderNamespace = "Mips64";
468 let isCodeGenOnly = 1;
473 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
475 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
476 Requires<[NotN64, HasStandardEncoding]>;
477 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
478 Requires<[IsN64, HasStandardEncoding]> {
479 let DecoderNamespace = "Mips64";
480 let isCodeGenOnly = 1;
485 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
487 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
488 Requires<[NotN64, HasStandardEncoding]>;
489 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
490 Requires<[IsN64, HasStandardEncoding]> {
491 let DecoderNamespace = "Mips64";
492 let isCodeGenOnly = 1;
496 // Load/Store Left/Right
497 let canFoldAsLoad = 1 in
498 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
499 RegisterClass RC, Operand MemOpnd> :
500 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
501 !strconcat(instr_asm, "\t$rt, $addr"),
502 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
503 string Constraints = "$src = $rt";
506 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
507 RegisterClass RC, Operand MemOpnd>:
508 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
509 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
512 // 32-bit load left/right.
513 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
514 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
515 Requires<[NotN64, HasStandardEncoding]>;
516 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
517 Requires<[IsN64, HasStandardEncoding]> {
518 let DecoderNamespace = "Mips64";
519 let isCodeGenOnly = 1;
523 // 64-bit load left/right.
524 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
525 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
526 Requires<[NotN64, HasStandardEncoding]>;
527 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
528 Requires<[IsN64, HasStandardEncoding]> {
529 let DecoderNamespace = "Mips64";
530 let isCodeGenOnly = 1;
534 // 32-bit store left/right.
535 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
536 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
537 Requires<[NotN64, HasStandardEncoding]>;
538 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
539 Requires<[IsN64, HasStandardEncoding]> {
540 let DecoderNamespace = "Mips64";
541 let isCodeGenOnly = 1;
545 // 64-bit store left/right.
546 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
547 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
548 Requires<[NotN64, HasStandardEncoding]>;
549 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
550 Requires<[IsN64, HasStandardEncoding]> {
551 let DecoderNamespace = "Mips64";
552 let isCodeGenOnly = 1;
556 // Conditional Branch
557 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
558 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
559 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
560 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
562 let isTerminator = 1;
563 let hasDelaySlot = 1;
566 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
568 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
569 !strconcat(instr_asm, "\t$rs, $imm16"),
570 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
573 let isTerminator = 1;
574 let hasDelaySlot = 1;
578 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
580 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
581 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
582 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
587 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
588 PatLeaf imm_type, RegisterClass RC>:
589 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
590 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
591 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
595 class JumpFJ<bits<6> op, string instr_asm>:
596 FJ<op, (outs), (ins jmptarget:$target),
597 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
601 let hasDelaySlot = 1;
602 let Predicates = [RelocStatic, HasStandardEncoding];
603 let DecoderMethod = "DecodeJumpTarget";
606 // Unconditional branch
607 class UncondBranch<bits<6> op, string instr_asm>:
608 BranchBase<op, (outs), (ins brtarget:$imm16),
609 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
613 let isTerminator = 1;
615 let hasDelaySlot = 1;
616 let Predicates = [RelocPIC, HasStandardEncoding];
619 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
620 isIndirectBranch = 1 in
621 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
622 FR<op, func, (outs), (ins RC:$rs),
623 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
629 // Jump and Link (Call)
630 let isCall=1, hasDelaySlot=1 in {
631 class JumpLink<bits<6> op, string instr_asm>:
632 FJ<op, (outs), (ins calltarget:$target, variable_ops),
633 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
635 let DecoderMethod = "DecodeJumpTarget";
638 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
640 FR<op, func, (outs), (ins RC:$rs, variable_ops),
641 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
647 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
648 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
649 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
655 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
656 RegisterClass RC, list<Register> DefRegs>:
657 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
658 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
661 let isCommutable = 1;
663 let neverHasSideEffects = 1;
666 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
667 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
669 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
670 RegisterClass RC, list<Register> DefRegs>:
671 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
672 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
673 [(op RC:$rs, RC:$rt)], itin> {
679 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
680 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
683 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
684 list<Register> UseRegs>:
685 FR<0x00, func, (outs RC:$rd), (ins),
686 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
691 let neverHasSideEffects = 1;
694 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
695 list<Register> DefRegs>:
696 FR<0x00, func, (outs), (ins RC:$rs),
697 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
702 let neverHasSideEffects = 1;
705 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
706 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
707 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
709 // Count Leading Ones/Zeros in Word
710 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
711 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
712 !strconcat(instr_asm, "\t$rd, $rs"),
713 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
714 Requires<[HasBitCount, HasStandardEncoding]> {
719 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
720 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
721 !strconcat(instr_asm, "\t$rd, $rs"),
722 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
723 Requires<[HasBitCount, HasStandardEncoding]> {
728 // Sign Extend in Register.
729 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
731 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
732 !strconcat(instr_asm, "\t$rd, $rt"),
733 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
736 let Predicates = [HasSEInReg, HasStandardEncoding];
740 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
741 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
742 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
745 let Predicates = [HasSwap, HasStandardEncoding];
746 let neverHasSideEffects = 1;
750 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
751 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
752 "rdhwr\t$rt, $rd", [], IIAlu> {
758 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
759 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
760 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
761 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
766 let Predicates = [HasMips32r2, HasStandardEncoding];
769 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
770 FR<0x1f, _funct, (outs RC:$rt),
771 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
772 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
773 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
779 let Predicates = [HasMips32r2, HasStandardEncoding];
780 let Constraints = "$src = $rt";
783 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
784 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
786 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
787 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
788 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
790 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
791 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
792 Requires<[NotN64, HasStandardEncoding]>;
793 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
794 Requires<[IsN64, HasStandardEncoding]> {
795 let DecoderNamespace = "Mips64";
799 // Atomic Compare & Swap.
800 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
802 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
803 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
804 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
806 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
807 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
808 Requires<[NotN64, HasStandardEncoding]>;
809 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
810 Requires<[IsN64, HasStandardEncoding]> {
811 let DecoderNamespace = "Mips64";
815 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
816 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
817 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
821 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
822 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
823 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
825 let Constraints = "$rt = $dst";
828 //===----------------------------------------------------------------------===//
829 // Pseudo instructions
830 //===----------------------------------------------------------------------===//
832 // As stack alignment is always done with addiu, we need a 16-bit immediate
833 let Defs = [SP], Uses = [SP] in {
834 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
835 "!ADJCALLSTACKDOWN $amt",
836 [(callseq_start timm:$amt)]>;
837 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
838 "!ADJCALLSTACKUP $amt1",
839 [(callseq_end timm:$amt1, timm:$amt2)]>;
842 // When handling PIC code the assembler needs .cpload and .cprestore
843 // directives. If the real instructions corresponding these directives
844 // are used, we have the same behavior, but get also a bunch of warnings
845 // from the assembler.
846 let neverHasSideEffects = 1 in
847 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
848 ".cprestore\t$loc", []>;
850 let usesCustomInserter = 1 in {
851 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
852 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
853 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
854 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
855 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
856 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
857 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
858 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
859 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
860 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
861 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
862 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
863 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
864 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
865 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
866 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
867 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
868 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
870 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
871 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
872 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
874 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
875 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
876 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
879 //===----------------------------------------------------------------------===//
880 // Instruction definition
881 //===----------------------------------------------------------------------===//
883 //===----------------------------------------------------------------------===//
884 // MipsI Instructions
885 //===----------------------------------------------------------------------===//
887 /// Arithmetic Instructions (ALU Immediate)
888 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
889 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
890 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
891 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
892 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
893 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
894 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
895 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
897 /// Arithmetic Instructions (3-Operand, R-Type)
898 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
899 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
900 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
901 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
902 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
903 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
904 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
905 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
906 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
907 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
909 /// Shift Instructions
910 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
911 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
912 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
913 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
914 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
915 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
917 // Rotate Instructions
918 let Predicates = [HasMips32r2, HasStandardEncoding] in {
919 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
920 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
923 /// Load and Store Instructions
925 defm LB : LoadM32<0x20, "lb", sextloadi8>;
926 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
927 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
928 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
929 defm LW : LoadM32<0x23, "lw", load_a>;
930 defm SB : StoreM32<0x28, "sb", truncstorei8>;
931 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
932 defm SW : StoreM32<0x2b, "sw", store_a>;
935 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
936 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
937 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
938 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
939 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
941 /// load/store left/right
942 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
943 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
944 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
945 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
947 let hasSideEffects = 1 in
948 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
949 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
954 let Inst{10-6} = stype;
958 /// Load-linked, Store-conditional
959 def LL : LLBase<0x30, "ll", CPURegs, mem>,
960 Requires<[NotN64, HasStandardEncoding]>;
961 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
962 Requires<[IsN64, HasStandardEncoding]> {
963 let DecoderNamespace = "Mips64";
966 def SC : SCBase<0x38, "sc", CPURegs, mem>,
967 Requires<[NotN64, HasStandardEncoding]>;
968 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
969 Requires<[IsN64, HasStandardEncoding]> {
970 let DecoderNamespace = "Mips64";
973 /// Jump and Branch Instructions
974 def J : JumpFJ<0x02, "j">;
975 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
976 def B : UncondBranch<0x04, "b">;
977 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
978 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
979 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
980 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
981 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
982 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
984 def JAL : JumpLink<0x03, "jal">;
985 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
986 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
987 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
989 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
990 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
991 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
992 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
994 /// Multiply and Divide Instructions.
995 def MULT : Mult32<0x18, "mult", IIImul>;
996 def MULTu : Mult32<0x19, "multu", IIImul>;
997 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
998 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1000 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1001 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1002 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1003 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1005 /// Sign Ext In Register Instructions.
1006 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1007 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1010 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1011 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1013 /// Word Swap Bytes Within Halfwords
1014 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1018 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1020 // FrameIndexes are legalized when they are operands from load/store
1021 // instructions. The same not happens for stack address copies, so an
1022 // add op with mem ComplexPattern is used and the stack address copy
1023 // can be matched. It's similar to Sparc LEA_ADDRi
1024 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1025 let isCodeGenOnly = 1;
1028 // DynAlloc node points to dynamically allocated stack space.
1029 // $sp is added to the list of implicitly used registers to prevent dead code
1030 // elimination from removing instructions that modify $sp.
1032 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1033 let isCodeGenOnly = 1;
1037 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1038 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1039 def MSUB : MArithR<4, "msub", MipsMSub>;
1040 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1042 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1043 // it is a real instruction.
1044 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
1045 Requires<[HasMips32, HasStandardEncoding]>;
1047 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1049 def EXT : ExtBase<0, "ext", CPURegs>;
1050 def INS : InsBase<4, "ins", CPURegs>;
1052 //===----------------------------------------------------------------------===//
1053 // Arbitrary patterns that map to one or more instructions
1054 //===----------------------------------------------------------------------===//
1057 def : Pat<(i32 immSExt16:$in),
1058 (ADDiu ZERO, imm:$in)>;
1059 def : Pat<(i32 immZExt16:$in),
1060 (ORi ZERO, imm:$in)>;
1061 def : Pat<(i32 immLow16Zero:$in),
1062 (LUi (HI16 imm:$in))>;
1064 // Arbitrary immediates
1065 def : Pat<(i32 imm:$imm),
1066 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1069 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
1070 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1071 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
1072 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1073 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
1074 (ADDiu CPURegs:$src, imm:$imm)>;
1077 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1078 (JAL tglobaladdr:$dst)>;
1079 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1080 (JAL texternalsym:$dst)>;
1081 //def : Pat<(MipsJmpLink CPURegs:$dst),
1082 // (JALR CPURegs:$dst)>;
1085 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1086 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1087 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1088 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1089 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1091 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1092 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1093 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1094 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1095 def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1097 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1098 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1099 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1100 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1101 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1102 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1103 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1104 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1105 def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1106 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1109 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1110 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1111 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1112 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1115 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1116 Pat<(MipsWrapper RC:$gp, node:$in),
1117 (ADDiuOp RC:$gp, node:$in)>;
1119 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1120 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1121 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1122 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1123 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1124 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1126 // Mips does not have "not", so we expand our way
1127 def : Pat<(not CPURegs:$in),
1128 (NOR CPURegs:$in, ZERO)>;
1131 let Predicates = [NotN64, HasStandardEncoding] in {
1132 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1133 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1134 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1135 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1137 let Predicates = [IsN64, HasStandardEncoding] in {
1138 def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1139 def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1140 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1141 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1145 let Predicates = [NotN64, HasStandardEncoding] in {
1146 def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1147 def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1149 let Predicates = [IsN64, HasStandardEncoding] in {
1150 def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1151 def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1155 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1156 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1157 Instruction SLTiuOp, Register ZEROReg> {
1158 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1159 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1160 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1161 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1163 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1164 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1165 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1166 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1167 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1168 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1169 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1170 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1172 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1173 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1174 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1175 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1177 def : Pat<(brcond RC:$cond, bb:$dst),
1178 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1181 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1184 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1185 Instruction SLTuOp, Register ZEROReg> {
1186 def : Pat<(seteq RC:$lhs, RC:$rhs),
1187 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1188 def : Pat<(setne RC:$lhs, RC:$rhs),
1189 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1192 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1193 def : Pat<(setle RC:$lhs, RC:$rhs),
1194 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1195 def : Pat<(setule RC:$lhs, RC:$rhs),
1196 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1199 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1200 def : Pat<(setgt RC:$lhs, RC:$rhs),
1201 (SLTOp RC:$rhs, RC:$lhs)>;
1202 def : Pat<(setugt RC:$lhs, RC:$rhs),
1203 (SLTuOp RC:$rhs, RC:$lhs)>;
1206 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1207 def : Pat<(setge RC:$lhs, RC:$rhs),
1208 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1209 def : Pat<(setuge RC:$lhs, RC:$rhs),
1210 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1213 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1214 Instruction SLTiuOp> {
1215 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1216 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1217 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1218 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1221 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1222 defm : SetlePats<CPURegs, SLT, SLTu>;
1223 defm : SetgtPats<CPURegs, SLT, SLTu>;
1224 defm : SetgePats<CPURegs, SLT, SLTu>;
1225 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1227 // select MipsDynAlloc
1228 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1231 def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1233 //===----------------------------------------------------------------------===//
1234 // Floating Point Support
1235 //===----------------------------------------------------------------------===//
1237 include "MipsInstrFPU.td"
1238 include "Mips64InstrInfo.td"
1239 include "MipsCondMov.td"
1244 include "Mips16InstrFormats.td"
1245 include "Mips16InstrInfo.td"