1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget->isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64_NOT_64R6 {
244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
246 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
247 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
248 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
253 // The portions of MIPS-III that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS3_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-III that were also added to MIPS32
260 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
262 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
263 // MIPS32r6 and MIPS64r6.
264 class INSN_MIPS4_32_NOT_32R6_64R6 {
265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
268 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
280 //===----------------------------------------------------------------------===//
282 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
283 let EncodingPredicates = [HasStdEnc];
286 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
287 InstAlias<Asm, Result, Emit>, PredicateControl;
290 bit isCommutable = 1;
307 bit isTerminator = 1;
310 bit hasExtraSrcRegAllocReq = 1;
311 bit isCodeGenOnly = 1;
314 class IsAsCheapAsAMove {
315 bit isAsCheapAsAMove = 1;
318 class NeverHasSideEffects {
319 bit hasSideEffects = 0;
322 //===----------------------------------------------------------------------===//
323 // Instruction format superclass
324 //===----------------------------------------------------------------------===//
326 include "MipsInstrFormats.td"
328 //===----------------------------------------------------------------------===//
329 // Mips Operand, Complex Patterns and Transformations Definitions.
330 //===----------------------------------------------------------------------===//
332 def MipsJumpTargetAsmOperand : AsmOperandClass {
333 let Name = "JumpTarget";
334 let ParserMethod = "parseJumpTarget";
335 let PredicateMethod = "isImm";
336 let RenderMethod = "addImmOperands";
339 // Instruction operand types
340 def jmptarget : Operand<OtherVT> {
341 let EncoderMethod = "getJumpTargetOpValue";
342 let ParserMatchClass = MipsJumpTargetAsmOperand;
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBranchTarget";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def calltarget : Operand<iPTR> {
351 let EncoderMethod = "getJumpTargetOpValue";
352 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def simm9 : Operand<i32>;
356 def simm10 : Operand<i32>;
357 def simm11 : Operand<i32>;
359 def simm16 : Operand<i32> {
360 let DecoderMethod= "DecodeSimm16";
363 def simm19_lsl2 : Operand<i32> {
364 let EncoderMethod = "getSimm19Lsl2Encoding";
365 let DecoderMethod = "DecodeSimm19Lsl2";
366 let ParserMatchClass = MipsJumpTargetAsmOperand;
369 def simm18_lsl3 : Operand<i32> {
370 let EncoderMethod = "getSimm18Lsl3Encoding";
371 let DecoderMethod = "DecodeSimm18Lsl3";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm20 : Operand<i32> {
378 def uimm20 : Operand<i32> {
381 def uimm10 : Operand<i32> {
384 def simm16_64 : Operand<i64> {
385 let DecoderMethod = "DecodeSimm16";
389 def uimmz : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
394 def uimm2 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm3 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm5 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm6 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def uimm16 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def pcrel16 : Operand<i32> {
417 def MipsMemAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseMemOperand";
422 def MipsMemSimm11AsmOperand : AsmOperandClass {
423 let Name = "MemOffsetSimm11";
424 let SuperClasses = [MipsMemAsmOperand];
425 let RenderMethod = "addMemOperands";
426 let ParserMethod = "parseMemOperand";
427 let PredicateMethod = "isMemWithSimmOffset<11>";
430 def MipsMemSimm16AsmOperand : AsmOperandClass {
431 let Name = "MemOffsetSimm16";
432 let SuperClasses = [MipsMemAsmOperand];
433 let RenderMethod = "addMemOperands";
434 let ParserMethod = "parseMemOperand";
435 let PredicateMethod = "isMemWithSimmOffset<16>";
438 def MipsInvertedImmoperand : AsmOperandClass {
440 let RenderMethod = "addImmOperands";
441 let ParserMethod = "parseInvNum";
444 def InvertedImOperand : Operand<i32> {
445 let ParserMatchClass = MipsInvertedImmoperand;
448 def InvertedImOperand64 : Operand<i64> {
449 let ParserMatchClass = MipsInvertedImmoperand;
452 class mem_generic : Operand<iPTR> {
453 let PrintMethod = "printMemOperand";
454 let MIOperandInfo = (ops ptr_rc, simm16);
455 let EncoderMethod = "getMemEncoding";
456 let ParserMatchClass = MipsMemAsmOperand;
457 let OperandType = "OPERAND_MEMORY";
461 def mem : mem_generic;
463 // MSA specific address operand
464 def mem_msa : mem_generic {
465 let MIOperandInfo = (ops ptr_rc, simm10);
466 let EncoderMethod = "getMSAMemEncoding";
469 def mem_simm9 : mem_generic {
470 let MIOperandInfo = (ops ptr_rc, simm9);
471 let EncoderMethod = "getMemEncoding";
474 def mem_simm11 : mem_generic {
475 let MIOperandInfo = (ops ptr_rc, simm11);
476 let EncoderMethod = "getMemEncoding";
477 let ParserMatchClass = MipsMemSimm11AsmOperand;
480 def mem_simm16 : mem_generic {
481 let MIOperandInfo = (ops ptr_rc, simm16);
482 let EncoderMethod = "getMemEncoding";
483 let ParserMatchClass = MipsMemSimm16AsmOperand;
486 def mem_ea : Operand<iPTR> {
487 let PrintMethod = "printMemOperandEA";
488 let MIOperandInfo = (ops ptr_rc, simm16);
489 let EncoderMethod = "getMemEncoding";
490 let OperandType = "OPERAND_MEMORY";
493 def PtrRC : Operand<iPTR> {
494 let MIOperandInfo = (ops ptr_rc);
495 let DecoderMethod = "DecodePtrRegisterClass";
496 let ParserMatchClass = GPR32AsmOperand;
499 // size operand of ext instruction
500 def size_ext : Operand<i32> {
501 let EncoderMethod = "getSizeExtEncoding";
502 let DecoderMethod = "DecodeExtSize";
505 // size operand of ins instruction
506 def size_ins : Operand<i32> {
507 let EncoderMethod = "getSizeInsEncoding";
508 let DecoderMethod = "DecodeInsSize";
511 // Transformation Function - get the lower 16 bits.
512 def LO16 : SDNodeXForm<imm, [{
513 return getImm(N, N->getZExtValue() & 0xFFFF);
516 // Transformation Function - get the higher 16 bits.
517 def HI16 : SDNodeXForm<imm, [{
518 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
522 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
524 // Node immediate is zero (e.g. insve.d)
525 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
527 // Node immediate fits as 16-bit sign extended on target immediate.
529 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
531 // Node immediate fits as 16-bit sign extended on target immediate.
533 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
535 // Node immediate fits as 15-bit sign extended on target immediate.
537 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
539 // Node immediate fits as 16-bit zero extended on target immediate.
540 // The LO16 param means that only the lower 16 bits of the node
541 // immediate are caught.
543 def immZExt16 : PatLeaf<(imm), [{
544 if (N->getValueType(0) == MVT::i32)
545 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
547 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
550 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
551 def immLow16Zero : PatLeaf<(imm), [{
552 int64_t Val = N->getSExtValue();
553 return isInt<32>(Val) && !(Val & 0xffff);
556 // shamt field must fit in 5 bits.
557 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
559 // True if (N + 1) fits in 16-bit field.
560 def immSExt16Plus1 : PatLeaf<(imm), [{
561 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
564 // Mips Address Mode! SDNode frameindex could possibily be a match
565 // since load and store instructions from stack used it.
567 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
570 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
573 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
576 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
578 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
580 //===----------------------------------------------------------------------===//
581 // Instructions specific format
582 //===----------------------------------------------------------------------===//
584 // Arithmetic and logical instructions with 3 register operands.
585 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
586 InstrItinClass Itin = NoItinerary,
587 SDPatternOperator OpNode = null_frag>:
588 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
589 !strconcat(opstr, "\t$rd, $rs, $rt"),
590 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
591 let isCommutable = isComm;
592 let isReMaterializable = 1;
593 let TwoOperandAliasConstraint = "$rd = $rs";
596 // Arithmetic and logical instructions with 2 register operands.
597 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
598 InstrItinClass Itin = NoItinerary,
599 SDPatternOperator imm_type = null_frag,
600 SDPatternOperator OpNode = null_frag> :
601 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
602 !strconcat(opstr, "\t$rt, $rs, $imm16"),
603 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
605 let isReMaterializable = 1;
606 let TwoOperandAliasConstraint = "$rs = $rt";
609 // Arithmetic Multiply ADD/SUB
610 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
611 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
612 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
613 let Defs = [HI0, LO0];
614 let Uses = [HI0, LO0];
615 let isCommutable = isComm;
619 class LogicNOR<string opstr, RegisterOperand RO>:
620 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
621 !strconcat(opstr, "\t$rd, $rs, $rt"),
622 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
623 let isCommutable = 1;
627 class shift_rotate_imm<string opstr, Operand ImmOpnd,
628 RegisterOperand RO, InstrItinClass itin,
629 SDPatternOperator OpNode = null_frag,
630 SDPatternOperator PF = null_frag> :
631 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
632 !strconcat(opstr, "\t$rd, $rt, $shamt"),
633 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
634 let TwoOperandAliasConstraint = "$rt = $rd";
637 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
638 SDPatternOperator OpNode = null_frag>:
639 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
640 !strconcat(opstr, "\t$rd, $rt, $rs"),
641 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
644 // Load Upper Imediate
645 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
646 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
647 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
648 let hasSideEffects = 0;
649 let isReMaterializable = 1;
653 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
654 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
655 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
656 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
657 let DecoderMethod = "DecodeMem";
658 let canFoldAsLoad = 1;
662 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
663 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
664 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
665 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
666 let DecoderMethod = "DecodeMem";
670 // Load/Store Left/Right
671 let canFoldAsLoad = 1 in
672 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
673 InstrItinClass Itin> :
674 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
675 !strconcat(opstr, "\t$rt, $addr"),
676 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
677 let DecoderMethod = "DecodeMem";
678 string Constraints = "$src = $rt";
681 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
682 InstrItinClass Itin> :
683 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
684 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
685 let DecoderMethod = "DecodeMem";
689 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
690 SDPatternOperator OpNode= null_frag> :
691 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
692 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
693 let DecoderMethod = "DecodeFMem2";
697 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
698 SDPatternOperator OpNode= null_frag> :
699 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
700 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
701 let DecoderMethod = "DecodeFMem2";
706 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
707 SDPatternOperator OpNode= null_frag> :
708 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
709 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
710 let DecoderMethod = "DecodeFMem3";
714 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
715 SDPatternOperator OpNode= null_frag> :
716 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
717 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
718 let DecoderMethod = "DecodeFMem3";
722 // Conditional Branch
723 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
724 RegisterOperand RO, bit DelaySlot = 1> :
725 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
726 !strconcat(opstr, "\t$rs, $rt, $offset"),
727 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
730 let isTerminator = 1;
731 let hasDelaySlot = DelaySlot;
735 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
736 RegisterOperand RO, bit DelaySlot = 1> :
737 InstSE<(outs), (ins RO:$rs, opnd:$offset),
738 !strconcat(opstr, "\t$rs, $offset"),
739 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
742 let isTerminator = 1;
743 let hasDelaySlot = DelaySlot;
748 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
749 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
750 !strconcat(opstr, "\t$rd, $rs, $rt"),
751 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
752 II_SLT_SLTU, FrmR, opstr>;
754 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
756 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
757 !strconcat(opstr, "\t$rt, $rs, $imm16"),
758 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
759 II_SLTI_SLTIU, FrmI, opstr>;
762 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
763 SDPatternOperator targetoperator, string bopstr> :
764 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
765 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
768 let hasDelaySlot = 1;
769 let DecoderMethod = "DecodeJumpTarget";
773 // Unconditional branch
774 class UncondBranch<Instruction BEQInst> :
775 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
776 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
778 let isTerminator = 1;
780 let hasDelaySlot = 1;
781 let AdditionalPredicates = [RelocPIC];
785 // Base class for indirect branch and return instruction classes.
786 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
787 class JumpFR<string opstr, RegisterOperand RO,
788 SDPatternOperator operator = null_frag>:
789 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
793 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
795 let isIndirectBranch = 1;
798 // Jump and Link (Call)
799 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
800 class JumpLink<string opstr, DAGOperand opnd> :
801 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
802 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
803 let DecoderMethod = "DecodeJumpTarget";
806 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
807 Register RetReg, RegisterOperand ResRO = RO>:
808 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
809 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
811 class JumpLinkReg<string opstr, RegisterOperand RO>:
812 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
815 class BGEZAL_FT<string opstr, DAGOperand opnd,
816 RegisterOperand RO, bit DelaySlot = 1> :
817 InstSE<(outs), (ins RO:$rs, opnd:$offset),
818 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
819 let hasDelaySlot = DelaySlot;
824 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
825 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
826 class TailCall<Instruction JumpInst> :
827 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
828 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
830 class TailCallReg<RegisterOperand RO, Instruction JRInst,
831 RegisterOperand ResRO = RO> :
832 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
833 PseudoInstExpansion<(JRInst ResRO:$rs)>;
836 class BAL_BR_Pseudo<Instruction RealInst> :
837 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
838 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
840 let isTerminator = 1;
842 let hasDelaySlot = 1;
847 class SYS_FT<string opstr> :
848 InstSE<(outs), (ins uimm20:$code_),
849 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
851 class BRK_FT<string opstr> :
852 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
853 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
857 class ER_FT<string opstr> :
858 InstSE<(outs), (ins),
859 opstr, [], NoItinerary, FrmOther, opstr>;
862 class DEI_FT<string opstr, RegisterOperand RO> :
863 InstSE<(outs RO:$rt), (ins),
864 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
867 class WAIT_FT<string opstr> :
868 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
871 let hasSideEffects = 1 in
872 class SYNC_FT<string opstr> :
873 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
874 NoItinerary, FrmOther, opstr>;
876 class SYNCI_FT<string opstr> :
877 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
878 NoItinerary, FrmOther, opstr> {
879 let hasSideEffects = 1;
880 let DecoderMethod = "DecodeSyncI";
883 let hasSideEffects = 1 in
884 class TEQ_FT<string opstr, RegisterOperand RO> :
885 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
886 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
889 class TEQI_FT<string opstr, RegisterOperand RO> :
890 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
891 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
893 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
894 list<Register> DefRegs> :
895 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
897 let isCommutable = 1;
899 let hasSideEffects = 0;
902 // Pseudo multiply/divide instruction with explicit accumulator register
904 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
905 SDPatternOperator OpNode, InstrItinClass Itin,
906 bit IsComm = 1, bit HasSideEffects = 0,
907 bit UsesCustomInserter = 0> :
908 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
909 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
910 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
911 let isCommutable = IsComm;
912 let hasSideEffects = HasSideEffects;
913 let usesCustomInserter = UsesCustomInserter;
916 // Pseudo multiply add/sub instruction with explicit accumulator register
918 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
920 : PseudoSE<(outs ACC64:$ac),
921 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
923 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
925 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
926 string Constraints = "$acin = $ac";
929 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
930 list<Register> DefRegs> :
931 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
932 [], itin, FrmR, opstr> {
937 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
938 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
939 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
941 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
942 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
945 let hasSideEffects = 0;
948 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
949 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
950 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
953 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
954 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
957 let hasSideEffects = 0;
960 class EffectiveAddress<string opstr, RegisterOperand RO> :
961 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
962 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
963 !strconcat(opstr, "_lea")> {
964 let isCodeGenOnly = 1;
965 let DecoderMethod = "DecodeMem";
968 // Count Leading Ones/Zeros in Word
969 class CountLeading0<string opstr, RegisterOperand RO>:
970 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
971 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
973 class CountLeading1<string opstr, RegisterOperand RO>:
974 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
975 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
977 // Sign Extend in Register.
978 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
979 InstrItinClass itin> :
980 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
981 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
984 class SubwordSwap<string opstr, RegisterOperand RO>:
985 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
986 NoItinerary, FrmR, opstr> {
987 let hasSideEffects = 0;
991 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
992 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
993 II_RDHWR, FrmR, "rdhwr">;
996 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
997 SDPatternOperator Op = null_frag>:
998 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
999 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1000 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
1001 FrmR, opstr>, ISA_MIPS32R2;
1003 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1004 SDPatternOperator Op = null_frag>:
1005 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1006 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1007 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1008 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
1009 let Constraints = "$src = $rt";
1012 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1013 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1014 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1015 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1017 // Atomic Compare & Swap.
1018 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1019 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1020 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1022 class LLBase<string opstr, RegisterOperand RO> :
1023 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1024 [], NoItinerary, FrmI> {
1025 let DecoderMethod = "DecodeMem";
1029 class SCBase<string opstr, RegisterOperand RO> :
1030 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1031 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1032 let DecoderMethod = "DecodeMem";
1034 let Constraints = "$rt = $dst";
1037 class MFC3OP<string asmstr, RegisterOperand RO> :
1038 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1039 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1041 class TrapBase<Instruction RealInst>
1042 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1043 PseudoInstExpansion<(RealInst 0, 0)> {
1045 let isTerminator = 1;
1046 let isCodeGenOnly = 1;
1049 //===----------------------------------------------------------------------===//
1050 // Pseudo instructions
1051 //===----------------------------------------------------------------------===//
1054 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1055 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1057 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1058 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1059 [(callseq_start timm:$amt)]>;
1060 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1061 [(callseq_end timm:$amt1, timm:$amt2)]>;
1064 let usesCustomInserter = 1 in {
1065 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1066 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1067 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1068 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1069 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1070 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1071 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1072 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1073 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1074 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1075 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1076 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1077 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1078 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1079 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1080 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1081 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1082 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1084 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1085 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1086 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1088 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1089 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1090 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1093 /// Pseudo instructions for loading and storing accumulator registers.
1094 let isPseudo = 1, isCodeGenOnly = 1 in {
1095 def LOAD_ACC64 : Load<"", ACC64>;
1096 def STORE_ACC64 : Store<"", ACC64>;
1099 // We need these two pseudo instructions to avoid offset calculation for long
1100 // branches. See the comment in file MipsLongBranch.cpp for detailed
1103 // Expands to: lui $dst, %hi($tgt - $baltgt)
1104 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1105 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1107 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1108 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1109 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1111 //===----------------------------------------------------------------------===//
1112 // Instruction definition
1113 //===----------------------------------------------------------------------===//
1114 //===----------------------------------------------------------------------===//
1115 // MipsI Instructions
1116 //===----------------------------------------------------------------------===//
1118 /// Arithmetic Instructions (ALU Immediate)
1119 let AdditionalPredicates = [NotInMicroMips] in {
1120 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1121 add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
1123 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1124 ISA_MIPS1_NOT_32R6_64R6;
1125 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1127 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1129 let AdditionalPredicates = [NotInMicroMips] in {
1130 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1133 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1136 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1139 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1141 /// Arithmetic Instructions (3-Operand, R-Type)
1142 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1144 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1146 let Defs = [HI0, LO0] in
1147 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1148 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1149 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1150 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1151 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1152 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1153 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1155 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1157 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1159 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1161 /// Shift Instructions
1162 let AdditionalPredicates = [NotInMicroMips] in {
1163 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1164 immZExt5>, SRA_FM<0, 0>;
1165 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1166 immZExt5>, SRA_FM<2, 0>;
1168 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1169 immZExt5>, SRA_FM<3, 0>;
1170 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1172 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1174 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1177 // Rotate Instructions
1178 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1180 SRA_FM<2, 1>, ISA_MIPS32R2;
1181 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1182 SRLV_FM<6, 1>, ISA_MIPS32R2;
1184 /// Load and Store Instructions
1186 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1187 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1189 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1191 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1192 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1194 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1195 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1196 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1198 /// load/store left/right
1199 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1200 AdditionalPredicates = [NotInMicroMips] in {
1201 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1202 ISA_MIPS1_NOT_32R6_64R6;
1203 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1204 ISA_MIPS1_NOT_32R6_64R6;
1205 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1206 ISA_MIPS1_NOT_32R6_64R6;
1207 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1208 ISA_MIPS1_NOT_32R6_64R6;
1211 // COP2 Memory Instructions
1212 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1213 ISA_MIPS1_NOT_32R6_64R6;
1214 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1215 ISA_MIPS1_NOT_32R6_64R6;
1216 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1217 ISA_MIPS2_NOT_32R6_64R6;
1218 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1219 ISA_MIPS2_NOT_32R6_64R6;
1221 // COP3 Memory Instructions
1222 let DecoderNamespace = "COP3_" in {
1223 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1224 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1225 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1227 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1231 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1232 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1234 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1235 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1236 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1237 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1238 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1239 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1241 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1242 ISA_MIPS2_NOT_32R6_64R6;
1243 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1244 ISA_MIPS2_NOT_32R6_64R6;
1245 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1246 ISA_MIPS2_NOT_32R6_64R6;
1247 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1248 ISA_MIPS2_NOT_32R6_64R6;
1249 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1250 ISA_MIPS2_NOT_32R6_64R6;
1251 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1252 ISA_MIPS2_NOT_32R6_64R6;
1254 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1255 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1256 def TRAP : TrapBase<BREAK>;
1257 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1259 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1260 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1262 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1263 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1265 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1266 AdditionalPredicates = [NotInMicroMips] in {
1267 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1269 /// Load-linked, Store-conditional
1270 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1271 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1274 /// Jump and Branch Instructions
1275 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1276 AdditionalRequires<[RelocStatic]>, IsBranch;
1277 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1278 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1279 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1280 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1281 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1282 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1283 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1284 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1286 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1287 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1288 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1290 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1291 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1292 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1294 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1295 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1296 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1298 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1299 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1300 def B : UncondBranch<BEQ>;
1302 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1303 let AdditionalPredicates = [NotInMicroMips] in {
1304 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1305 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1308 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1309 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1310 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1311 ISA_MIPS1_NOT_32R6_64R6;
1312 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1313 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1314 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1315 ISA_MIPS1_NOT_32R6_64R6;
1316 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1317 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1318 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1319 def TAILCALL : TailCall<J>;
1320 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1322 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1323 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1324 class PseudoIndirectBranchBase<RegisterOperand RO> :
1325 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1328 let hasDelaySlot = 1;
1330 let isIndirectBranch = 1;
1333 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1335 // Return instructions are matched as a RetRA instruction, then ar expanded
1336 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1337 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1339 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1341 let isTerminator = 1;
1343 let hasDelaySlot = 1;
1345 let isCodeGenOnly = 1;
1347 let hasExtraSrcRegAllocReq = 1;
1350 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1352 // Exception handling related node and instructions.
1353 // The conversion sequence is:
1354 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1355 // MIPSeh_return -> (stack change + indirect branch)
1357 // MIPSeh_return takes the place of regular return instruction
1358 // but takes two arguments (V1, V0) which are used for storing
1359 // the offset and return address respectively.
1360 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1362 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1363 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1365 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1366 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1367 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1368 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1370 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1373 /// Multiply and Divide Instructions.
1374 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1375 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1376 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1377 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1378 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1379 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1380 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1381 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1383 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1384 ISA_MIPS1_NOT_32R6_64R6;
1385 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1386 ISA_MIPS1_NOT_32R6_64R6;
1387 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1388 AdditionalPredicates = [NotInMicroMips] in {
1389 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1390 ISA_MIPS1_NOT_32R6_64R6;
1391 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1392 ISA_MIPS1_NOT_32R6_64R6;
1395 /// Sign Ext In Register Instructions.
1396 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1397 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1398 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1399 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1402 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1403 ISA_MIPS32_NOT_32R6_64R6;
1404 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1405 ISA_MIPS32_NOT_32R6_64R6;
1407 /// Word Swap Bytes Within Halfwords
1408 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1411 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1413 // FrameIndexes are legalized when they are operands from load/store
1414 // instructions. The same not happens for stack address copies, so an
1415 // add op with mem ComplexPattern is used and the stack address copy
1416 // can be matched. It's similar to Sparc LEA_ADDRi
1417 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1420 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1421 ISA_MIPS32_NOT_32R6_64R6;
1422 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1423 ISA_MIPS32_NOT_32R6_64R6;
1424 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1425 ISA_MIPS32_NOT_32R6_64R6;
1426 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1427 ISA_MIPS32_NOT_32R6_64R6;
1429 let AdditionalPredicates = [NotDSP] in {
1430 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1431 ISA_MIPS1_NOT_32R6_64R6;
1432 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1433 ISA_MIPS1_NOT_32R6_64R6;
1434 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1435 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1436 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1437 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1438 ISA_MIPS32_NOT_32R6_64R6;
1439 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1440 ISA_MIPS32_NOT_32R6_64R6;
1441 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1442 ISA_MIPS32_NOT_32R6_64R6;
1443 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1444 ISA_MIPS32_NOT_32R6_64R6;
1447 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1448 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1449 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1450 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1452 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1454 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1455 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1457 /// Move Control Registers From/To CPU Registers
1458 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1459 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1460 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1461 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1463 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1465 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1466 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1467 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1469 // JR_HB and JALR_HB are defined here using the new style naming
1470 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1471 // and because of that it doesn't follow the naming convention of the
1472 // rest of the file. To avoid a mixture of old vs new style, the new
1473 // style was chosen.
1474 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1475 dag OutOperandList = (outs);
1476 dag InOperandList = (ins GPROpnd:$rs);
1477 string AsmString = !strconcat(instr_asm, "\t$rs");
1478 list<dag> Pattern = [];
1481 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1482 dag OutOperandList = (outs GPROpnd:$rd);
1483 dag InOperandList = (ins GPROpnd:$rs);
1484 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1485 list<dag> Pattern = [];
1488 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1489 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1491 let isIndirectBranch=1;
1497 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1498 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1499 let isIndirectBranch=1;
1503 class JR_HB_ENC : JR_HB_FM<8>;
1504 class JALR_HB_ENC : JALR_HB_FM<9>;
1506 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1507 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1509 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1511 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1512 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1513 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1514 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1516 class CacheOp<string instr_asm, Operand MemOpnd> :
1517 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1518 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> {
1519 let DecoderMethod = "DecodeCacheOp";
1522 def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1523 INSN_MIPS3_32_NOT_32R6_64R6;
1524 def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1525 INSN_MIPS3_32_NOT_32R6_64R6;
1527 //===----------------------------------------------------------------------===//
1528 // Instruction aliases
1529 //===----------------------------------------------------------------------===//
1530 def : MipsInstAlias<"move $dst, $src",
1531 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1533 let AdditionalPredicates = [NotInMicroMips];
1535 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1536 ISA_MIPS1_NOT_32R6_64R6;
1537 def : MipsInstAlias<"addu $rs, $rt, $imm",
1538 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1539 def : MipsInstAlias<"addu $rs, $imm",
1540 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1541 def : MipsInstAlias<"add $rs, $rt, $imm",
1542 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1543 ISA_MIPS1_NOT_32R6_64R6;
1544 def : MipsInstAlias<"add $rs, $imm",
1545 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1546 ISA_MIPS1_NOT_32R6_64R6;
1547 def : MipsInstAlias<"and $rs, $rt, $imm",
1548 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1549 def : MipsInstAlias<"and $rs, $imm",
1550 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1551 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1552 let Predicates = [NotInMicroMips] in {
1553 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1555 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1556 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1557 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1558 def : MipsInstAlias<"not $rt, $rs",
1559 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1560 def : MipsInstAlias<"neg $rt, $rs",
1561 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1562 def : MipsInstAlias<"negu $rt",
1563 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1564 def : MipsInstAlias<"negu $rt, $rs",
1565 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1566 def : MipsInstAlias<"slt $rs, $rt, $imm",
1567 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1568 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1569 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1570 def : MipsInstAlias<"xor $rs, $rt, $imm",
1571 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1572 def : MipsInstAlias<"or $rs, $rt, $imm",
1573 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1574 def : MipsInstAlias<"or $rs, $imm",
1575 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1576 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1577 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1578 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1579 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1580 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1581 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1582 def : MipsInstAlias<"bnez $rs,$offset",
1583 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1584 def : MipsInstAlias<"beqz $rs,$offset",
1585 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1586 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1588 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1589 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1590 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1591 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1593 def : MipsInstAlias<"teq $rs, $rt",
1594 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1595 def : MipsInstAlias<"tge $rs, $rt",
1596 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1597 def : MipsInstAlias<"tgeu $rs, $rt",
1598 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1599 def : MipsInstAlias<"tlt $rs, $rt",
1600 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1601 def : MipsInstAlias<"tltu $rs, $rt",
1602 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1603 def : MipsInstAlias<"tne $rs, $rt",
1604 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1606 def : MipsInstAlias<"sll $rd, $rt, $rs",
1607 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1608 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1609 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1610 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1611 def : MipsInstAlias<"sub $rs, $imm",
1612 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1613 0>, ISA_MIPS1_NOT_32R6_64R6;
1614 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1615 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1616 InvertedImOperand:$imm), 0>;
1617 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1618 InvertedImOperand:$imm), 0>;
1619 def : MipsInstAlias<"sra $rd, $rt, $rs",
1620 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1621 def : MipsInstAlias<"srl $rd, $rt, $rs",
1622 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1623 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1624 def : MipsInstAlias<"sync",
1625 (SYNC 0), 1>, ISA_MIPS2;
1626 //===----------------------------------------------------------------------===//
1627 // Assembler Pseudo Instructions
1628 //===----------------------------------------------------------------------===//
1630 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1631 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1632 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1633 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1635 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1636 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1637 !strconcat(instr_asm, "\t$rt, $addr")> ;
1638 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1640 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1641 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1642 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1643 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1645 //===----------------------------------------------------------------------===//
1646 // Arbitrary patterns that map to one or more instructions
1647 //===----------------------------------------------------------------------===//
1649 // Load/store pattern templates.
1650 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1651 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1653 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1654 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1657 def : MipsPat<(i32 immSExt16:$in),
1658 (ADDiu ZERO, imm:$in)>;
1659 def : MipsPat<(i32 immZExt16:$in),
1660 (ORi ZERO, imm:$in)>;
1661 def : MipsPat<(i32 immLow16Zero:$in),
1662 (LUi (HI16 imm:$in))>;
1664 // Arbitrary immediates
1665 def : MipsPat<(i32 imm:$imm),
1666 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1668 // Carry MipsPatterns
1669 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1670 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1671 let AdditionalPredicates = [NotDSP] in {
1672 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1673 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1674 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1675 (ADDiu GPR32:$src, imm:$imm)>;
1678 // Support multiplication for pre-Mips32 targets that don't have
1679 // the MUL instruction.
1680 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1681 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1682 ISA_MIPS1_NOT_32R6_64R6;
1685 def : MipsPat<(MipsSync (i32 immz)),
1686 (SYNC 0)>, ISA_MIPS2;
1689 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1690 (JAL tglobaladdr:$dst)>;
1691 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1692 (JAL texternalsym:$dst)>;
1693 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1694 // (JALR GPR32:$dst)>;
1697 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1698 (TAILCALL tglobaladdr:$dst)>;
1699 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1700 (TAILCALL texternalsym:$dst)>;
1702 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1703 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1704 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1705 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1706 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1707 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1709 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1710 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1711 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1712 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1713 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1714 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1716 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1717 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1718 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1719 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1720 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1721 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1722 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1723 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1724 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1725 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1728 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1729 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1730 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1731 (ADDiu GPR32:$gp, tconstpool:$in)>;
1734 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1735 MipsPat<(MipsWrapper RC:$gp, node:$in),
1736 (ADDiuOp RC:$gp, node:$in)>;
1738 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1739 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1740 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1741 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1742 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1743 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1745 // Mips does not have "not", so we expand our way
1746 def : MipsPat<(not GPR32:$in),
1747 (NOR GPR32Opnd:$in, ZERO)>;
1750 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1751 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1752 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1755 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1758 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1759 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1760 Instruction SLTiuOp, Register ZEROReg> {
1761 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1762 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1763 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1764 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1766 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1767 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1768 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1769 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1770 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1771 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1772 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1773 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1774 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1775 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1776 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1777 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1779 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1780 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1781 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1782 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1784 def : MipsPat<(brcond RC:$cond, bb:$dst),
1785 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1788 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1790 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1791 (BLEZ i32:$lhs, bb:$dst)>;
1792 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1793 (BGEZ i32:$lhs, bb:$dst)>;
1796 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1797 Instruction SLTuOp, Register ZEROReg> {
1798 def : MipsPat<(seteq RC:$lhs, 0),
1799 (SLTiuOp RC:$lhs, 1)>;
1800 def : MipsPat<(setne RC:$lhs, 0),
1801 (SLTuOp ZEROReg, RC:$lhs)>;
1802 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1803 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1804 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1805 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1808 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1809 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1810 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1811 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1812 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1815 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1816 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1817 (SLTOp RC:$rhs, RC:$lhs)>;
1818 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1819 (SLTuOp RC:$rhs, RC:$lhs)>;
1822 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1823 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1824 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1825 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1826 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1829 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1830 Instruction SLTiuOp> {
1831 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1832 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1833 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1834 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1837 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1838 defm : SetlePats<GPR32, SLT, SLTu>;
1839 defm : SetgtPats<GPR32, SLT, SLTu>;
1840 defm : SetgePats<GPR32, SLT, SLTu>;
1841 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1844 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1846 // Load halfword/word patterns.
1847 let AddedComplexity = 40 in {
1848 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1849 def : LoadRegImmPat<LH, i32, sextloadi16>;
1850 def : LoadRegImmPat<LW, i32, load>;
1853 //===----------------------------------------------------------------------===//
1854 // Floating Point Support
1855 //===----------------------------------------------------------------------===//
1857 include "MipsInstrFPU.td"
1858 include "Mips64InstrInfo.td"
1859 include "MipsCondMov.td"
1861 include "Mips32r6InstrInfo.td"
1862 include "Mips64r6InstrInfo.td"
1867 include "Mips16InstrFormats.td"
1868 include "Mips16InstrInfo.td"
1871 include "MipsDSPInstrFormats.td"
1872 include "MipsDSPInstrInfo.td"
1875 include "MipsMSAInstrFormats.td"
1876 include "MipsMSAInstrInfo.td"
1879 include "MicroMipsInstrFormats.td"
1880 include "MicroMipsInstrInfo.td"
1881 include "MicroMipsInstrFPU.td"