1 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
29 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
30 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
37 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
40 // Hi and Lo nodes are used to handle global addresses. Used on
41 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
42 // static model. (nothing to do with Mips Registers Hi and Lo)
43 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
44 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
45 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
48 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
51 // These are target-independent nodes, but have target-specific formats.
52 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
53 [SDNPHasChain, SDNPOutGlue]>;
54 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
55 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
57 // Select Condition Code
58 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
61 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
62 [SDNPOptInGlue, SDNPOutGlue]>;
63 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
64 [SDNPOptInGlue, SDNPOutGlue]>;
65 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
66 [SDNPOptInGlue, SDNPOutGlue]>;
67 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
68 [SDNPOptInGlue, SDNPOutGlue]>;
70 //===----------------------------------------------------------------------===//
71 // Mips Instruction Predicate Definitions.
72 //===----------------------------------------------------------------------===//
73 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
74 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
75 def HasSwap : Predicate<"Subtarget.hasSwap()">;
76 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
77 def IsMips32 : Predicate<"Subtarget.isMips32()">;
78 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
80 //===----------------------------------------------------------------------===//
81 // Mips Operand, Complex Patterns and Transformations Definitions.
82 //===----------------------------------------------------------------------===//
84 // Instruction operand types
85 def brtarget : Operand<OtherVT>;
86 def calltarget : Operand<i32>;
87 def simm16 : Operand<i32>;
88 def shamt : Operand<i32>;
91 def uimm16 : Operand<i32> {
92 let PrintMethod = "printUnsignedImm";
96 def mem : Operand<i32> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops simm16, CPURegs);
101 // Transformation Function - get the lower 16 bits.
102 def LO16 : SDNodeXForm<imm, [{
103 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
106 // Transformation Function - get the higher 16 bits.
107 def HI16 : SDNodeXForm<imm, [{
108 return getI32Imm((unsigned)N->getZExtValue() >> 16);
111 // Node immediate fits as 16-bit sign extended on target immediate.
113 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
115 // Node immediate fits as 16-bit zero extended on target immediate.
116 // The LO16 param means that only the lower 16 bits of the node
117 // immediate are caught.
119 def immZExt16 : PatLeaf<(imm), [{
120 if (N->getValueType(0) == MVT::i32)
121 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
123 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
126 // shamt field must fit in 5 bits.
127 def immZExt5 : PatLeaf<(imm), [{
128 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
131 // Mips Address Mode! SDNode frameindex could possibily be a match
132 // since load and store instructions from stack used it.
133 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
135 //===----------------------------------------------------------------------===//
136 // Instructions specific format
137 //===----------------------------------------------------------------------===//
139 // Arithmetic 3 register operands
140 let isCommutable = 1 in
141 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
142 InstrItinClass itin>:
143 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
144 !strconcat(instr_asm, "\t$dst, $b, $c"),
145 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
147 let isCommutable = 1 in
148 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
149 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
150 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
152 // Arithmetic 2 register operands
153 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
154 Operand Od, PatLeaf imm_type> :
155 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
156 !strconcat(instr_asm, "\t$dst, $b, $c"),
157 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
159 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
160 Operand Od, PatLeaf imm_type> :
161 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
162 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
164 // Arithmetic Multiply ADD/SUB
165 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
166 class MArithR<bits<6> func, string instr_asm, SDNode op> :
167 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
168 !strconcat(instr_asm, "\t$rs, $rt"),
169 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul>;
172 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
173 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
174 !strconcat(instr_asm, "\t$dst, $b, $c"),
175 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
177 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
178 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
179 !strconcat(instr_asm, "\t$dst, $b, $c"),
180 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
182 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
183 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
184 !strconcat(instr_asm, "\t$dst, $b, $c"),
185 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
188 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
190 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
191 !strconcat(instr_asm, "\t$dst, $b, $c"),
192 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
196 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
198 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
199 !strconcat(instr_asm, "\t$dst, $b, $c"),
200 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
204 // Load Upper Imediate
205 class LoadUpper<bits<6> op, string instr_asm>:
209 !strconcat(instr_asm, "\t$dst, $imm"),
213 let canFoldAsLoad = 1, hasDelaySlot = 1 in
214 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
215 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
216 !strconcat(instr_asm, "\t$dst, $addr"),
217 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
219 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
220 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
221 !strconcat(instr_asm, "\t$dst, $addr"),
222 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
224 // Conditional Branch
225 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
226 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
227 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
228 !strconcat(instr_asm, "\t$a, $b, $offset"),
229 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
232 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
233 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
234 !strconcat(instr_asm, "\t$src, $offset"),
235 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
240 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
242 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
243 !strconcat(instr_asm, "\t$dst, $b, $c"),
244 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
247 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
248 Operand Od, PatLeaf imm_type>:
249 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
250 !strconcat(instr_asm, "\t$dst, $b, $c"),
251 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
254 // Unconditional branch
255 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
256 class JumpFJ<bits<6> op, string instr_asm>:
257 FJ<op, (outs), (ins brtarget:$target),
258 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
260 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
261 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
262 FR<op, func, (outs), (ins CPURegs:$target),
263 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
265 // Jump and Link (Call)
266 let isCall=1, hasDelaySlot=1,
267 // All calls clobber the non-callee saved registers...
268 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
269 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
270 class JumpLink<bits<6> op, string instr_asm>:
271 FJ<op, (outs), (ins calltarget:$target, variable_ops),
272 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
276 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
277 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
278 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
280 class BranchLink<string instr_asm>:
281 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
282 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
286 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
287 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
288 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
291 class MoveFromLOHI<bits<6> func, string instr_asm>:
292 FR<0x00, func, (outs CPURegs:$dst), (ins),
293 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
295 class MoveToLOHI<bits<6> func, string instr_asm>:
296 FR<0x00, func, (outs), (ins CPURegs:$src),
297 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
299 class EffectiveAddress<string instr_asm> :
300 FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
301 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
303 // Count Leading Ones/Zeros in Word
304 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
305 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
306 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
307 Requires<[HasBitCount]> {
312 // Sign Extend in Register.
313 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
314 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
315 !strconcat(instr_asm, "\t$dst, $src"),
316 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
319 class ByteSwap<bits<6> func, string instr_asm>:
320 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
321 !strconcat(instr_asm, "\t$dst, $src"),
322 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
325 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
326 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
327 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
330 //===----------------------------------------------------------------------===//
331 // Pseudo instructions
332 //===----------------------------------------------------------------------===//
334 // As stack alignment is always done with addiu, we need a 16-bit immediate
335 let Defs = [SP], Uses = [SP] in {
336 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
337 "!ADJCALLSTACKDOWN $amt",
338 [(callseq_start timm:$amt)]>;
339 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
340 "!ADJCALLSTACKUP $amt1",
341 [(callseq_end timm:$amt1, timm:$amt2)]>;
344 // Some assembly macros need to avoid pseudoinstructions and assembler
345 // automatic reodering, we should reorder ourselves.
346 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
347 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
348 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
349 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
351 // When handling PIC code the assembler needs .cpload and .cprestore
352 // directives. If the real instructions corresponding these directives
353 // are used, we have the same behavior, but get also a bunch of warnings
354 // from the assembler.
355 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
356 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
358 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
359 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
360 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
361 // replace it for real supported nodes into EmitInstrWithCustomInserter
362 let usesCustomInserter = 1 in {
363 class PseudoSelCC<RegisterClass RC, string asmstr>:
364 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
365 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
368 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
370 //===----------------------------------------------------------------------===//
371 // Instruction definition
372 //===----------------------------------------------------------------------===//
374 //===----------------------------------------------------------------------===//
375 // MipsI Instructions
376 //===----------------------------------------------------------------------===//
378 /// Arithmetic Instructions (ALU Immediate)
379 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
380 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
381 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
382 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
383 def ANDi : LogicI<0x0c, "andi", and>;
384 def ORi : LogicI<0x0d, "ori", or>;
385 def XORi : LogicI<0x0e, "xori", xor>;
386 def LUi : LoadUpper<0x0f, "lui">;
388 /// Arithmetic Instructions (3-Operand, R-Type)
389 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
390 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
391 def ADD : ArithOverflowR<0x00, 0x20, "add">;
392 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
393 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
394 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
395 def AND : LogicR<0x24, "and", and>;
396 def OR : LogicR<0x25, "or", or>;
397 def XOR : LogicR<0x26, "xor", xor>;
398 def NOR : LogicNOR<0x00, 0x27, "nor">;
400 /// Shift Instructions
401 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
402 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
403 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
404 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
405 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
406 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
408 // Rotate Instructions
409 let Predicates = [IsMips32r2] in {
410 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
411 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
414 /// Load and Store Instructions
415 def LB : LoadM<0x20, "lb", sextloadi8>;
416 def LBu : LoadM<0x24, "lbu", zextloadi8>;
417 def LH : LoadM<0x21, "lh", sextloadi16>;
418 def LHu : LoadM<0x25, "lhu", zextloadi16>;
419 def LW : LoadM<0x23, "lw", load>;
420 def SB : StoreM<0x28, "sb", truncstorei8>;
421 def SH : StoreM<0x29, "sh", truncstorei16>;
422 def SW : StoreM<0x2b, "sw", store>;
424 /// Jump and Branch Instructions
425 def J : JumpFJ<0x02, "j">;
426 def JR : JumpFR<0x00, 0x08, "jr">;
427 def JAL : JumpLink<0x03, "jal">;
428 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
429 def BEQ : CBranch<0x04, "beq", seteq>;
430 def BNE : CBranch<0x05, "bne", setne>;
433 def BGEZ : CBranchZero<0x01, "bgez", setge>;
436 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
437 def BLEZ : CBranchZero<0x07, "blez", setle>;
438 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
441 def BGEZAL : BranchLink<"bgezal">;
442 def BLTZAL : BranchLink<"bltzal">;
444 let isReturn=1, isTerminator=1, hasDelaySlot=1,
445 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
446 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
447 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
449 /// Multiply and Divide Instructions.
450 let Defs = [HI, LO] in {
451 def MULT : MulDiv<0x18, "mult", IIImul>;
452 def MULTu : MulDiv<0x19, "multu", IIImul>;
453 def DIV : MulDiv<0x1a, "div", IIIdiv>;
454 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
458 def MTHI : MoveToLOHI<0x11, "mthi">;
460 def MTLO : MoveToLOHI<0x13, "mtlo">;
463 def MFHI : MoveFromLOHI<0x10, "mfhi">;
465 def MFLO : MoveFromLOHI<0x12, "mflo">;
467 /// Sign Ext In Register Instructions.
468 let Predicates = [HasSEInReg] in {
469 let shamt = 0x10, rs = 0 in
470 def SEB : SignExtInReg<0x21, "seb", i8>;
472 let shamt = 0x18, rs = 0 in
473 def SEH : SignExtInReg<0x20, "seh", i16>;
477 def CLZ : CountLeading<0b100000, "clz",
478 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
479 def CLO : CountLeading<0b100001, "clo",
480 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
483 let Predicates = [HasSwap] in {
484 let shamt = 0x3, rs = 0 in
485 def WSBW : ByteSwap<0x20, "wsbw">;
489 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
490 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
492 let Predicates = [HasCondMov], Constraints = "$F = $dst" in {
493 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
494 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
499 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
501 // FrameIndexes are legalized when they are operands from load/store
502 // instructions. The same not happens for stack address copies, so an
503 // add op with mem ComplexPattern is used and the stack address copy
504 // can be matched. It's similar to Sparc LEA_ADDRi
505 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
508 def MADD : MArithR<0, "madd", MipsMAdd>;
509 def MADDU : MArithR<1, "maddu", MipsMAddu>;
510 def MSUB : MArithR<4, "msub", MipsMSub>;
511 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
513 // MUL is a assembly macro in the current used ISAs. In recent ISA's
514 // it is a real instruction.
515 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
517 //===----------------------------------------------------------------------===//
518 // Arbitrary patterns that map to one or more instructions
519 //===----------------------------------------------------------------------===//
522 def : Pat<(i32 immSExt16:$in),
523 (ADDiu ZERO, imm:$in)>;
524 def : Pat<(i32 immZExt16:$in),
525 (ORi ZERO, imm:$in)>;
527 // Arbitrary immediates
528 def : Pat<(i32 imm:$imm),
529 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
532 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
533 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
534 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
535 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
536 def : Pat<(addc CPURegs:$src, imm:$imm),
537 (ADDiu CPURegs:$src, imm:$imm)>;
540 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
541 (JAL tglobaladdr:$dst)>;
542 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
543 (JAL texternalsym:$dst)>;
544 //def : Pat<(MipsJmpLink CPURegs:$dst),
545 // (JALR CPURegs:$dst)>;
548 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
549 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
550 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
552 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
553 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
554 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
556 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
557 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
558 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
561 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
562 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
563 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
564 (ADDiu CPURegs:$gp, tconstpool:$in)>;
566 // Mips does not have "not", so we expand our way
567 def : Pat<(not CPURegs:$in),
568 (NOR CPURegs:$in, ZERO)>;
570 // extended load and stores
571 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
572 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
573 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
576 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
579 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
580 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
581 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
582 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
584 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
585 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
586 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
587 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
588 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
589 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
590 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
591 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
593 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
594 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
595 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
596 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
598 def : Pat<(brcond CPURegs:$cond, bb:$dst),
599 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
602 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
603 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
604 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
605 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
606 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
607 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
608 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
609 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
611 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
612 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
613 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
614 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
616 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
617 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
618 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
619 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
621 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
622 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
624 // select patterns with got access
625 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs),
626 (i32 tglobaladdr:$T), CPURegs:$F),
627 (MOVN CPURegs:$F, (ADDiu GP, tglobaladdr:$T),
628 (XOR CPURegs:$lhs, CPURegs:$rhs))>;
631 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
632 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
633 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
634 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
636 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
637 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
638 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
639 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
641 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
642 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
643 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
644 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
646 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
647 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
648 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
649 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
651 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
652 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
653 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
654 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
656 //===----------------------------------------------------------------------===//
657 // Floating Point Support
658 //===----------------------------------------------------------------------===//
660 include "MipsInstrFPU.td"