1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
31 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
32 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
34 // Hi and Lo nodes are used to handle global addresses. Used on
35 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
36 // static model. (nothing to do with Mips Registers Hi and Lo)
37 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
38 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
39 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
42 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
45 // These are target-independent nodes, but have target-specific formats.
46 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
47 [SDNPHasChain, SDNPOutFlag]>;
48 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
49 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
51 // Select Condition Code
52 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
55 def MipsCMov : SDNode<"MipsISD::CMov", SDT_MipsCMov>;
57 //===----------------------------------------------------------------------===//
58 // Mips Instruction Predicate Definitions.
59 //===----------------------------------------------------------------------===//
60 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
61 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
62 def HasSwap : Predicate<"Subtarget.hasSwap()">;
63 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
65 //===----------------------------------------------------------------------===//
66 // Mips Operand, Complex Patterns and Transformations Definitions.
67 //===----------------------------------------------------------------------===//
69 // Instruction operand types
70 def brtarget : Operand<OtherVT>;
71 def calltarget : Operand<i32>;
72 def simm16 : Operand<i32>;
73 def shamt : Operand<i32>;
76 def uimm16 : Operand<i32> {
77 let PrintMethod = "printUnsignedImm";
81 def mem : Operand<i32> {
82 let PrintMethod = "printMemOperand";
83 let MIOperandInfo = (ops simm16, CPURegs);
86 // Transformation Function - get the lower 16 bits.
87 def LO16 : SDNodeXForm<imm, [{
88 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
91 // Transformation Function - get the higher 16 bits.
92 def HI16 : SDNodeXForm<imm, [{
93 return getI32Imm((unsigned)N->getZExtValue() >> 16);
96 // Node immediate fits as 16-bit sign extended on target immediate.
98 def immSExt16 : PatLeaf<(imm), [{
99 if (N->getValueType(0) == MVT::i32)
100 return (int32_t)N->getZExtValue() == (short)N->getZExtValue();
102 return (int64_t)N->getZExtValue() == (short)N->getZExtValue();
105 // Node immediate fits as 16-bit zero extended on target immediate.
106 // The LO16 param means that only the lower 16 bits of the node
107 // immediate are caught.
109 def immZExt16 : PatLeaf<(imm), [{
110 if (N->getValueType(0) == MVT::i32)
111 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
113 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
116 // shamt field must fit in 5 bits.
117 def immZExt5 : PatLeaf<(imm), [{
118 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
121 // Mips Address Mode! SDNode frameindex could possibily be a match
122 // since load and store instructions from stack used it.
123 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
125 //===----------------------------------------------------------------------===//
126 // Instructions specific format
127 //===----------------------------------------------------------------------===//
129 // Arithmetic 3 register operands
130 let isCommutable = 1 in
131 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
132 InstrItinClass itin>:
136 (ins CPURegs:$b, CPURegs:$c),
137 !strconcat(instr_asm, "\t$dst, $b, $c"),
138 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
140 let isCommutable = 1 in
141 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
145 (ins CPURegs:$b, CPURegs:$c),
146 !strconcat(instr_asm, "\t$dst, $b, $c"),
149 // Arithmetic 2 register operands
150 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
151 Operand Od, PatLeaf imm_type> :
154 (ins CPURegs:$b, Od:$c),
155 !strconcat(instr_asm, "\t$dst, $b, $c"),
156 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
158 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
159 Operand Od, PatLeaf imm_type> :
162 (ins CPURegs:$b, Od:$c),
163 !strconcat(instr_asm, "\t$dst, $b, $c"),
166 // Arithmetic Multiply ADD/SUB
168 class MArithR<bits<6> func, string instr_asm> :
173 !strconcat(instr_asm, "\t$rs, $rt"),
177 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
181 (ins CPURegs:$b, CPURegs:$c),
182 !strconcat(instr_asm, "\t$dst, $b, $c"),
183 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
185 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
188 (ins CPURegs:$b, uimm16:$c),
189 !strconcat(instr_asm, "\t$dst, $b, $c"),
190 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
192 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
196 (ins CPURegs:$b, CPURegs:$c),
197 !strconcat(instr_asm, "\t$dst, $b, $c"),
198 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
202 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
206 (ins CPURegs:$b, shamt:$c),
207 !strconcat(instr_asm, "\t$dst, $b, $c"),
208 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
210 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
214 (ins CPURegs:$b, CPURegs:$c),
215 !strconcat(instr_asm, "\t$dst, $b, $c"),
216 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
218 // Load Upper Imediate
219 class LoadUpper<bits<6> op, string instr_asm>:
223 !strconcat(instr_asm, "\t$dst, $imm"),
227 let canFoldAsLoad = 1, hasDelaySlot = 1 in
228 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
232 !strconcat(instr_asm, "\t$dst, $addr"),
233 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
235 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
238 (ins CPURegs:$dst, mem:$addr),
239 !strconcat(instr_asm, "\t$dst, $addr"),
240 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
242 // Conditional Branch
243 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
244 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
247 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
248 !strconcat(instr_asm, "\t$a, $b, $offset"),
249 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
253 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
256 (ins CPURegs:$src, brtarget:$offset),
257 !strconcat(instr_asm, "\t$src, $offset"),
258 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
263 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
268 (ins CPURegs:$b, CPURegs:$c),
269 !strconcat(instr_asm, "\t$dst, $b, $c"),
270 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
273 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
274 Operand Od, PatLeaf imm_type>:
277 (ins CPURegs:$b, Od:$c),
278 !strconcat(instr_asm, "\t$dst, $b, $c"),
279 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
282 // Unconditional branch
283 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
284 class JumpFJ<bits<6> op, string instr_asm>:
287 (ins brtarget:$target),
288 !strconcat(instr_asm, "\t$target"),
289 [(br bb:$target)], IIBranch>;
291 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
292 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
296 (ins CPURegs:$target),
297 !strconcat(instr_asm, "\t$target"),
298 [(brind CPURegs:$target)], IIBranch>;
300 // Jump and Link (Call)
301 let isCall=1, hasDelaySlot=1,
302 // All calls clobber the non-callee saved registers...
303 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
304 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
305 class JumpLink<bits<6> op, string instr_asm>:
308 (ins calltarget:$target, variable_ops),
309 !strconcat(instr_asm, "\t$target"),
310 [(MipsJmpLink imm:$target)], IIBranch>;
313 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
317 (ins CPURegs:$rs, variable_ops),
318 !strconcat(instr_asm, "\t$rs"),
319 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
321 class BranchLink<string instr_asm>:
324 (ins CPURegs:$rs, brtarget:$target, variable_ops),
325 !strconcat(instr_asm, "\t$rs, $target"),
330 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
334 (ins CPURegs:$a, CPURegs:$b),
335 !strconcat(instr_asm, "\t$a, $b"),
339 class MoveFromLOHI<bits<6> func, string instr_asm>:
344 !strconcat(instr_asm, "\t$dst"),
347 class MoveToLOHI<bits<6> func, string instr_asm>:
352 !strconcat(instr_asm, "\t$src"),
355 class EffectiveAddress<string instr_asm> :
360 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
362 // Count Leading Ones/Zeros in Word
363 class CountLeading<bits<6> func, string instr_asm, SDNode CountOp>:
364 FR< 0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
365 !strconcat(instr_asm, "\t$dst, $src"),
366 [(set CPURegs:$dst, (CountOp CPURegs:$src))], IIAlu>;
368 // Sign Extend in Register.
369 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
370 FR< 0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
371 !strconcat(instr_asm, "\t$dst, $src"),
372 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
375 class ByteSwap<bits<6> func, string instr_asm>:
376 FR< 0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
377 !strconcat(instr_asm, "\t$dst, $src"),
378 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
381 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
382 FR< 0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
383 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
384 [(set CPURegs:$dst, (MipsCMov CPURegs:$F, CPURegs:$T,
385 CPURegs:$cond, MovCode))], NoItinerary>;
387 //===----------------------------------------------------------------------===//
388 // Pseudo instructions
389 //===----------------------------------------------------------------------===//
391 // As stack alignment is always done with addiu, we need a 16-bit immediate
392 let Defs = [SP], Uses = [SP] in {
393 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
394 "!ADJCALLSTACKDOWN $amt",
395 [(callseq_start timm:$amt)]>;
396 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
397 "!ADJCALLSTACKUP $amt1",
398 [(callseq_end timm:$amt1, timm:$amt2)]>;
401 // Some assembly macros need to avoid pseudoinstructions and assembler
402 // automatic reodering, we should reorder ourselves.
403 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
404 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
405 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
406 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
408 // When handling PIC code the assembler needs .cpload and .cprestore
409 // directives. If the real instructions corresponding these directives
410 // are used, we have the same behavior, but get also a bunch of warnings
411 // from the assembler.
412 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
413 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
415 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
416 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
417 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
418 // replace it for real supported nodes into EmitInstrWithCustomInserter
419 let usesCustomInserter = 1 in {
420 class PseudoSelCC<RegisterClass RC, string asmstr>:
421 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
422 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
425 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
427 //===----------------------------------------------------------------------===//
428 // Instruction definition
429 //===----------------------------------------------------------------------===//
431 //===----------------------------------------------------------------------===//
432 // MipsI Instructions
433 //===----------------------------------------------------------------------===//
435 /// Arithmetic Instructions (ALU Immediate)
436 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
437 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
438 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
439 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
440 def ANDi : LogicI<0x0c, "andi", and>;
441 def ORi : LogicI<0x0d, "ori", or>;
442 def XORi : LogicI<0x0e, "xori", xor>;
443 def LUi : LoadUpper<0x0f, "lui">;
445 /// Arithmetic Instructions (3-Operand, R-Type)
446 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
447 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
448 def ADD : ArithOverflowR<0x00, 0x20, "add">;
449 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
450 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
451 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
452 def AND : LogicR<0x24, "and", and>;
453 def OR : LogicR<0x25, "or", or>;
454 def XOR : LogicR<0x26, "xor", xor>;
455 def NOR : LogicNOR<0x00, 0x27, "nor">;
457 /// Shift Instructions
458 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
459 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
460 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
461 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
462 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
463 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
465 /// Load and Store Instructions
466 def LB : LoadM<0x20, "lb", sextloadi8>;
467 def LBu : LoadM<0x24, "lbu", zextloadi8>;
468 def LH : LoadM<0x21, "lh", sextloadi16>;
469 def LHu : LoadM<0x25, "lhu", zextloadi16>;
470 def LW : LoadM<0x23, "lw", load>;
471 def SB : StoreM<0x28, "sb", truncstorei8>;
472 def SH : StoreM<0x29, "sh", truncstorei16>;
473 def SW : StoreM<0x2b, "sw", store>;
475 /// Jump and Branch Instructions
476 def J : JumpFJ<0x02, "j">;
477 def JR : JumpFR<0x00, 0x08, "jr">;
478 def JAL : JumpLink<0x03, "jal">;
479 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
480 def BEQ : CBranch<0x04, "beq", seteq>;
481 def BNE : CBranch<0x05, "bne", setne>;
484 def BGEZ : CBranchZero<0x01, "bgez", setge>;
487 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
488 def BLEZ : CBranchZero<0x07, "blez", setle>;
489 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
492 def BGEZAL : BranchLink<"bgezal">;
493 def BLTZAL : BranchLink<"bltzal">;
495 let isReturn=1, isTerminator=1, hasDelaySlot=1,
496 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
497 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
498 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
500 /// Multiply and Divide Instructions.
501 let Defs = [HI, LO] in {
502 def MULT : MulDiv<0x18, "mult", IIImul>;
503 def MULTu : MulDiv<0x19, "multu", IIImul>;
504 def DIV : MulDiv<0x1a, "div", IIIdiv>;
505 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
509 def MTHI : MoveToLOHI<0x11, "mthi">;
511 def MTLO : MoveToLOHI<0x13, "mtlo">;
514 def MFHI : MoveFromLOHI<0x10, "mfhi">;
516 def MFLO : MoveFromLOHI<0x12, "mflo">;
518 /// Sign Ext In Register Instructions.
519 let Predicates = [HasSEInReg] in {
520 let shamt = 0x10, rs = 0 in
521 def SEB : SignExtInReg<0x21, "seb", i8>;
523 let shamt = 0x18, rs = 0 in
524 def SEH : SignExtInReg<0x20, "seh", i16>;
528 let Predicates = [HasBitCount] in {
530 def CLZ : CountLeading<0b010110, "clz", ctlz>;
534 let Predicates = [HasSwap] in {
535 let shamt = 0x3, rs = 0 in
536 def WSBW : ByteSwap<0x20, "wsbw">;
540 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
541 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
543 let Predicates = [HasCondMov], isTwoAddress = 1 in {
544 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
545 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
550 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
552 // FrameIndexes are legalized when they are operands from load/store
553 // instructions. The same not happens for stack address copies, so an
554 // add op with mem ComplexPattern is used and the stack address copy
555 // can be matched. It's similar to Sparc LEA_ADDRi
556 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
558 // MADD*/MSUB* are not part of MipsI either.
559 //def MADD : MArithR<0x00, "madd">;
560 //def MADDU : MArithR<0x01, "maddu">;
561 //def MSUB : MArithR<0x04, "msub">;
562 //def MSUBU : MArithR<0x05, "msubu">;
564 // MUL is a assembly macro in the current used ISAs. In recent ISA's
565 // it is a real instruction.
566 //def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
568 //===----------------------------------------------------------------------===//
569 // Arbitrary patterns that map to one or more instructions
570 //===----------------------------------------------------------------------===//
573 def : Pat<(i32 immSExt16:$in),
574 (ADDiu ZERO, imm:$in)>;
575 def : Pat<(i32 immZExt16:$in),
576 (ORi ZERO, imm:$in)>;
578 // Arbitrary immediates
579 def : Pat<(i32 imm:$imm),
580 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
583 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
584 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
585 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
586 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
587 def : Pat<(addc CPURegs:$src, imm:$imm),
588 (ADDiu CPURegs:$src, imm:$imm)>;
591 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
592 (JAL tglobaladdr:$dst)>;
593 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
594 (JAL texternalsym:$dst)>;
595 def : Pat<(MipsJmpLink CPURegs:$dst),
596 (JALR CPURegs:$dst)>;
599 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
600 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
601 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
603 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
604 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
605 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
607 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
608 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
609 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
612 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
613 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
614 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
615 (ADDiu CPURegs:$gp, tconstpool:$in)>;
617 // Mips does not have "not", so we expand our way
618 def : Pat<(not CPURegs:$in),
619 (NOR CPURegs:$in, ZERO)>;
621 // extended load and stores
622 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
623 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
624 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
627 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
630 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
631 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
632 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
633 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
635 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
636 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
637 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
638 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
639 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
640 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
641 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
642 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
644 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
645 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
646 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
647 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
649 def : Pat<(brcond CPURegs:$cond, bb:$dst),
650 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
653 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
654 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
655 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
656 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
657 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
658 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
659 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
660 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
662 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
663 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
664 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
665 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
667 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
668 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
669 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
670 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
672 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
673 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
676 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
677 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
678 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
679 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
681 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
682 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
683 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
684 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
686 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
687 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
688 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
689 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
691 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
692 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
693 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
694 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
696 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
697 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
698 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
699 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
701 //===----------------------------------------------------------------------===//
702 // Floating Point Support
703 //===----------------------------------------------------------------------===//
705 include "MipsInstrFPU.td"