1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
31 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
33 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
34 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
35 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
36 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
38 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
40 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
42 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
44 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
45 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def SDTMipsLoadLR : SDTypeProfile<1, 2,
49 [SDTCisInt<0>, SDTCisPtrTy<1>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
58 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
59 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
61 // Hi and Lo nodes are used to handle global addresses. Used on
62 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
63 // static model. (nothing to do with Mips Registers Hi and Lo)
64 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
65 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
66 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
68 // TlsGd node is used to handle General Dynamic TLS
69 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
71 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
72 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
73 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
76 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
79 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
80 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
82 // These are target-independent nodes, but have target-specific formats.
83 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
84 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
85 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
86 [SDNPHasChain, SDNPSideEffect,
87 SDNPOptInGlue, SDNPOutGlue]>;
89 // Node used to extract integer from LO/HI register.
90 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
92 // Node used to insert 32-bit integers to LOHI register pair.
93 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
96 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
97 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
100 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
101 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
102 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
103 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
106 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
107 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
108 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
110 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
113 // Target constant nodes that are not part of any isel patterns and remain
114 // unchanged can cause instructions with illegal operands to be emitted.
115 // Wrapper node patterns give the instruction selector a chance to replace
116 // target constant nodes that would otherwise remain unchanged with ADDiu
117 // nodes. Without these wrapper node patterns, the following conditional move
118 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
120 // movn %got(d)($gp), %got(c)($gp), $4
121 // This instruction is illegal since movn can take only register operands.
123 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
125 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
127 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
128 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
130 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
133 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
134 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
137 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
138 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
141 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
142 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
144 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
145 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
147 //===----------------------------------------------------------------------===//
148 // Mips Instruction Predicate Definitions.
149 //===----------------------------------------------------------------------===//
150 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
151 AssemblerPredicate<"FeatureSEInReg">;
152 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
153 AssemblerPredicate<"FeatureBitCount">;
154 def HasSwap : Predicate<"Subtarget.hasSwap()">,
155 AssemblerPredicate<"FeatureSwap">;
156 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
157 AssemblerPredicate<"FeatureCondMov">;
158 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
159 AssemblerPredicate<"FeatureFPIdx">;
160 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
161 AssemblerPredicate<"FeatureMips32">;
162 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
163 AssemblerPredicate<"FeatureMips32r2">;
164 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
165 AssemblerPredicate<"FeatureMips64">;
166 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
167 AssemblerPredicate<"!FeatureMips64">;
168 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
169 AssemblerPredicate<"FeatureMips64r2">;
170 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
171 AssemblerPredicate<"FeatureN64">;
172 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
173 AssemblerPredicate<"!FeatureN64">;
174 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
175 AssemblerPredicate<"FeatureMips16">;
176 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
177 AssemblerPredicate<"FeatureMips32">;
178 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
179 AssemblerPredicate<"FeatureMips32">;
180 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
181 AssemblerPredicate<"FeatureMips32">;
182 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
183 AssemblerPredicate<"!FeatureMips16,!FeatureMicroMips">;
184 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
185 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"FeatureMicroMips">;
187 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
188 AssemblerPredicate<"!FeatureMicroMips">;
189 def IsLE : Predicate<"Subtarget.isLittle()">;
190 def IsBE : Predicate<"!Subtarget.isLittle()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64>;
268 def uimm5 : Operand<i32> {
269 let PrintMethod = "printUnsignedImm";
272 def uimm6 : Operand<i32> {
273 let PrintMethod = "printUnsignedImm";
276 def uimm16 : Operand<i32> {
277 let PrintMethod = "printUnsignedImm";
280 def MipsMemAsmOperand : AsmOperandClass {
282 let ParserMethod = "parseMemOperand";
285 def PtrRegAsmOperand : AsmOperandClass {
287 let ParserMethod = "parsePtrReg";
291 def mem : Operand<iPTR> {
292 let PrintMethod = "printMemOperand";
293 let MIOperandInfo = (ops ptr_rc, simm16);
294 let EncoderMethod = "getMemEncoding";
295 let ParserMatchClass = MipsMemAsmOperand;
296 let OperandType = "OPERAND_MEMORY";
299 def mem_ea : Operand<iPTR> {
300 let PrintMethod = "printMemOperandEA";
301 let MIOperandInfo = (ops ptr_rc, simm16);
302 let EncoderMethod = "getMemEncoding";
303 let OperandType = "OPERAND_MEMORY";
306 def PtrRC : Operand<iPTR> {
307 let MIOperandInfo = (ops ptr_rc);
308 let DecoderMethod = "DecodePtrRegisterClass";
309 let ParserMatchClass = PtrRegAsmOperand;
312 // size operand of ext instruction
313 def size_ext : Operand<i32> {
314 let EncoderMethod = "getSizeExtEncoding";
315 let DecoderMethod = "DecodeExtSize";
318 // size operand of ins instruction
319 def size_ins : Operand<i32> {
320 let EncoderMethod = "getSizeInsEncoding";
321 let DecoderMethod = "DecodeInsSize";
324 // Transformation Function - get the lower 16 bits.
325 def LO16 : SDNodeXForm<imm, [{
326 return getImm(N, N->getZExtValue() & 0xFFFF);
329 // Transformation Function - get the higher 16 bits.
330 def HI16 : SDNodeXForm<imm, [{
331 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
335 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
337 // Node immediate fits as 16-bit sign extended on target immediate.
339 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
341 // Node immediate fits as 16-bit sign extended on target immediate.
343 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
345 // Node immediate fits as 15-bit sign extended on target immediate.
347 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
349 // Node immediate fits as 16-bit zero extended on target immediate.
350 // The LO16 param means that only the lower 16 bits of the node
351 // immediate are caught.
353 def immZExt16 : PatLeaf<(imm), [{
354 if (N->getValueType(0) == MVT::i32)
355 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
357 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
360 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
361 def immLow16Zero : PatLeaf<(imm), [{
362 int64_t Val = N->getSExtValue();
363 return isInt<32>(Val) && !(Val & 0xffff);
366 // shamt field must fit in 5 bits.
367 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
369 // True if (N + 1) fits in 16-bit field.
370 def immSExt16Plus1 : PatLeaf<(imm), [{
371 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
374 // Mips Address Mode! SDNode frameindex could possibily be a match
375 // since load and store instructions from stack used it.
377 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
380 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
383 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
386 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
388 //===----------------------------------------------------------------------===//
389 // Instructions specific format
390 //===----------------------------------------------------------------------===//
392 // Arithmetic and logical instructions with 3 register operands.
393 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
394 InstrItinClass Itin = NoItinerary,
395 SDPatternOperator OpNode = null_frag>:
396 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
397 !strconcat(opstr, "\t$rd, $rs, $rt"),
398 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
399 let isCommutable = isComm;
400 let isReMaterializable = 1;
403 // Arithmetic and logical instructions with 2 register operands.
404 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
405 InstrItinClass Itin = NoItinerary,
406 SDPatternOperator imm_type = null_frag,
407 SDPatternOperator OpNode = null_frag> :
408 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
409 !strconcat(opstr, "\t$rt, $rs, $imm16"),
410 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
412 let isReMaterializable = 1;
413 let TwoOperandAliasConstraint = "$rs = $rt";
416 // Arithmetic Multiply ADD/SUB
417 class MArithR<string opstr, bit isComm = 0> :
418 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
419 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
420 let Defs = [HI0, LO0];
421 let Uses = [HI0, LO0];
422 let isCommutable = isComm;
426 class LogicNOR<string opstr, RegisterOperand RO>:
427 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
428 !strconcat(opstr, "\t$rd, $rs, $rt"),
429 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
430 let isCommutable = 1;
434 class shift_rotate_imm<string opstr, Operand ImmOpnd,
435 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
436 SDPatternOperator PF = null_frag> :
437 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
438 !strconcat(opstr, "\t$rd, $rt, $shamt"),
439 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
441 class shift_rotate_reg<string opstr, RegisterOperand RO,
442 SDPatternOperator OpNode = null_frag>:
443 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
444 !strconcat(opstr, "\t$rd, $rt, $rs"),
445 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
447 // Load Upper Imediate
448 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
449 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
450 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
451 let neverHasSideEffects = 1;
452 let isReMaterializable = 1;
456 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
457 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
458 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
459 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
460 let DecoderMethod = "DecodeMem";
461 let canFoldAsLoad = 1;
465 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
466 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
467 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
468 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
469 let DecoderMethod = "DecodeMem";
473 // Load/Store Left/Right
474 let canFoldAsLoad = 1 in
475 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
476 InstrItinClass Itin> :
477 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
478 !strconcat(opstr, "\t$rt, $addr"),
479 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
480 let DecoderMethod = "DecodeMem";
481 string Constraints = "$src = $rt";
484 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
485 InstrItinClass Itin> :
486 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
487 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
488 let DecoderMethod = "DecodeMem";
491 // Conditional Branch
492 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RO> :
493 InstSE<(outs), (ins RO:$rs, RO:$rt, brtarget:$offset),
494 !strconcat(opstr, "\t$rs, $rt, $offset"),
495 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
498 let isTerminator = 1;
499 let hasDelaySlot = 1;
503 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RO> :
504 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
505 !strconcat(opstr, "\t$rs, $offset"),
506 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
508 let isTerminator = 1;
509 let hasDelaySlot = 1;
514 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
515 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
516 !strconcat(opstr, "\t$rd, $rs, $rt"),
517 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
520 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
522 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
523 !strconcat(opstr, "\t$rt, $rs, $imm16"),
524 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
528 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
529 SDPatternOperator targetoperator> :
530 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
531 [(operator targetoperator:$target)], IIBranch, FrmJ> {
534 let hasDelaySlot = 1;
535 let DecoderMethod = "DecodeJumpTarget";
539 // Unconditional branch
540 class UncondBranch<Instruction BEQInst> :
541 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
542 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
544 let isTerminator = 1;
546 let hasDelaySlot = 1;
547 let Predicates = [RelocPIC, HasStdEnc];
551 // Base class for indirect branch and return instruction classes.
552 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
553 class JumpFR<RegisterOperand RO, SDPatternOperator operator = null_frag>:
554 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch, FrmR>;
557 class IndirectBranch<RegisterOperand RO>: JumpFR<RO, brind> {
559 let isIndirectBranch = 1;
562 // Return instruction
563 class RetBase<RegisterOperand RO>: JumpFR<RO> {
565 let isCodeGenOnly = 1;
567 let hasExtraSrcRegAllocReq = 1;
570 // Jump and Link (Call)
571 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
572 class JumpLink<string opstr> :
573 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
574 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
575 let DecoderMethod = "DecodeJumpTarget";
578 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
579 Register RetReg, RegisterOperand ResRO = RO>:
580 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
581 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
583 class JumpLinkReg<string opstr, RegisterOperand RO>:
584 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
587 class BGEZAL_FT<string opstr, RegisterOperand RO> :
588 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
589 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
593 class BAL_BR_Pseudo<Instruction RealInst> :
594 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
595 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
597 let isTerminator = 1;
599 let hasDelaySlot = 1;
604 class SYS_FT<string opstr> :
605 InstSE<(outs), (ins uimm20:$code_),
606 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
608 class BRK_FT<string opstr> :
609 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
610 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
613 class ER_FT<string opstr> :
614 InstSE<(outs), (ins),
615 opstr, [], NoItinerary, FrmOther>;
618 class DEI_FT<string opstr, RegisterOperand RO> :
619 InstSE<(outs RO:$rt), (ins),
620 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
623 class WAIT_FT<string opstr> :
624 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
625 let Inst{31-26} = 0x10;
628 let Inst{5-0} = 0x20;
632 let hasSideEffects = 1 in
634 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
635 NoItinerary, FrmOther>;
637 let hasSideEffects = 1 in
638 class TEQ_FT<string opstr, RegisterOperand RO> :
639 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
640 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary, FrmI>;
642 class TEQI_FT<string opstr, RegisterOperand RO> :
643 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
644 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther>;
646 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
647 list<Register> DefRegs> :
648 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
650 let isCommutable = 1;
652 let neverHasSideEffects = 1;
655 // Pseudo multiply/divide instruction with explicit accumulator register
657 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
658 SDPatternOperator OpNode, InstrItinClass Itin,
659 bit IsComm = 1, bit HasSideEffects = 0,
660 bit UsesCustomInserter = 0> :
661 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
662 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
663 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
664 let isCommutable = IsComm;
665 let hasSideEffects = HasSideEffects;
666 let usesCustomInserter = UsesCustomInserter;
669 // Pseudo multiply add/sub instruction with explicit accumulator register
671 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
672 : PseudoSE<(outs ACC64:$ac),
673 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
675 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
677 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
678 string Constraints = "$acin = $ac";
681 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
682 list<Register> DefRegs> :
683 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
684 [], itin, FrmR, opstr> {
689 class MoveFromLOHI<string opstr, RegisterOperand RO, list<Register> UseRegs>:
690 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo,
693 let neverHasSideEffects = 1;
696 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
697 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
700 let neverHasSideEffects = 1;
703 class EffectiveAddress<string opstr, RegisterOperand RO> :
704 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
705 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
706 let isCodeGenOnly = 1;
707 let DecoderMethod = "DecodeMem";
710 // Count Leading Ones/Zeros in Word
711 class CountLeading0<string opstr, RegisterOperand RO>:
712 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
713 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
714 Requires<[HasBitCount, HasStdEnc]>;
716 class CountLeading1<string opstr, RegisterOperand RO>:
717 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
718 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
719 Requires<[HasBitCount, HasStdEnc]>;
722 // Sign Extend in Register.
723 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
724 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
725 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
726 let Predicates = [HasSEInReg, HasStdEnc];
730 class SubwordSwap<string opstr, RegisterOperand RO>:
731 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
732 NoItinerary, FrmR, opstr> {
733 let Predicates = [HasSwap, HasStdEnc];
734 let neverHasSideEffects = 1;
738 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
739 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
743 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
744 SDPatternOperator Op = null_frag>:
745 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
746 !strconcat(opstr, " $rt, $rs, $pos, $size"),
747 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
749 let Predicates = [HasMips32r2, HasStdEnc];
752 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
753 SDPatternOperator Op = null_frag>:
754 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
755 !strconcat(opstr, " $rt, $rs, $pos, $size"),
756 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
757 NoItinerary, FrmR, opstr> {
758 let Predicates = [HasMips32r2, HasStdEnc];
759 let Constraints = "$src = $rt";
762 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
763 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
764 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
765 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
767 // Atomic Compare & Swap.
768 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
769 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
770 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
772 class LLBase<string opstr, RegisterOperand RO> :
773 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
774 [], NoItinerary, FrmI> {
775 let DecoderMethod = "DecodeMem";
779 class SCBase<string opstr, RegisterOperand RO> :
780 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
781 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
782 let DecoderMethod = "DecodeMem";
784 let Constraints = "$rt = $dst";
787 class MFC3OP<string asmstr, RegisterOperand RO> :
788 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
789 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
791 class TrapBase<Instruction RealInst>
792 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
793 PseudoInstExpansion<(RealInst 0, 0)> {
795 let isTerminator = 1;
796 let isCodeGenOnly = 1;
799 //===----------------------------------------------------------------------===//
800 // Pseudo instructions
801 //===----------------------------------------------------------------------===//
804 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
805 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
807 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
808 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
809 [(callseq_start timm:$amt)]>;
810 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
811 [(callseq_end timm:$amt1, timm:$amt2)]>;
814 let usesCustomInserter = 1 in {
815 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
816 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
817 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
818 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
819 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
820 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
821 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
822 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
823 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
824 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
825 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
826 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
827 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
828 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
829 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
830 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
831 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
832 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
834 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
835 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
836 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
838 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
839 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
840 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
843 /// Pseudo instructions for loading and storing accumulator registers.
844 let isPseudo = 1, isCodeGenOnly = 1 in {
845 def LOAD_ACC64 : Load<"", ACC64>;
846 def STORE_ACC64 : Store<"", ACC64>;
849 //===----------------------------------------------------------------------===//
850 // Instruction definition
851 //===----------------------------------------------------------------------===//
852 //===----------------------------------------------------------------------===//
853 // MipsI Instructions
854 //===----------------------------------------------------------------------===//
856 /// Arithmetic Instructions (ALU Immediate)
857 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
859 ADDI_FM<0x9>, IsAsCheapAsAMove;
860 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
861 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
863 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
865 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
868 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
871 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
874 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
876 /// Arithmetic Instructions (3-Operand, R-Type)
877 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
879 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
881 let Defs = [HI0, LO0] in
882 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
884 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
885 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
886 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
887 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
888 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
890 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
892 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
894 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
896 /// Shift Instructions
897 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
899 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
901 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
903 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
904 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
905 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
907 // Rotate Instructions
908 let Predicates = [HasMips32r2, HasStdEnc] in {
909 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
912 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
916 /// Load and Store Instructions
918 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
919 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
921 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
923 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
924 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
926 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
927 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
928 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
930 /// load/store left/right
931 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
932 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
933 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
934 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
936 def SYNC : SYNC_FT, SYNC_FM;
937 def TEQ : TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
938 def TGE : TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
939 def TGEU : TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
940 def TLT : TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
941 def TLTU : TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
942 def TNE : TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
944 def TEQI : TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
945 def TGEI : TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
946 def TGEIU : TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
947 def TLTI : TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
948 def TTLTIU : TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
949 def TNEI : TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
951 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
952 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
953 def TRAP : TrapBase<BREAK>;
955 def ERET : ER_FT<"eret">, ER_FM<0x18>;
956 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
958 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
959 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
961 def WAIT : WAIT_FT<"wait">;
963 /// Load-linked, Store-conditional
964 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
965 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
967 /// Jump and Branch Instructions
968 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
969 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
970 def JR : IndirectBranch<GPR32Opnd>, MTLO_FM<8>;
971 def BEQ : CBranch<"beq", seteq, GPR32Opnd>, BEQ_FM<4>;
972 def BNE : CBranch<"bne", setne, GPR32Opnd>, BEQ_FM<5>;
973 def BGEZ : CBranchZero<"bgez", setge, GPR32Opnd>, BGEZ_FM<1, 1>;
974 def BGTZ : CBranchZero<"bgtz", setgt, GPR32Opnd>, BGEZ_FM<7, 0>;
975 def BLEZ : CBranchZero<"blez", setle, GPR32Opnd>, BGEZ_FM<6, 0>;
976 def BLTZ : CBranchZero<"bltz", setlt, GPR32Opnd>, BGEZ_FM<1, 0>;
977 def B : UncondBranch<BEQ>;
979 def JAL : JumpLink<"jal">, FJ<3>;
980 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
981 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
982 def BGEZAL : BGEZAL_FT<"bgezal", GPR32Opnd>, BGEZAL_FM<0x11>;
983 def BLTZAL : BGEZAL_FT<"bltzal", GPR32Opnd>, BGEZAL_FM<0x10>;
984 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
985 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
986 def TAILCALL_R : JumpFR<GPR32Opnd, MipsTailCall>, MTLO_FM<8>, IsTailCall;
988 def RET : RetBase<GPR32Opnd>, MTLO_FM<8>;
990 // Exception handling related node and instructions.
991 // The conversion sequence is:
992 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
993 // MIPSeh_return -> (stack change + indirect branch)
995 // MIPSeh_return takes the place of regular return instruction
996 // but takes two arguments (V1, V0) which are used for storing
997 // the offset and return address respectively.
998 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1000 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1001 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1003 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1004 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1005 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1006 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1008 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1011 /// Multiply and Divide Instructions.
1012 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1014 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1016 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1017 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1018 def SDIV : Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1a>;
1019 def UDIV : Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>, MULT_FM<0, 0x1b>;
1020 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1022 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1025 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1026 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1027 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, [HI0]>, MFLO_FM<0x10>;
1028 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, [LO0]>, MFLO_FM<0x12>;
1030 /// Sign Ext In Register Instructions.
1031 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1032 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1035 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1036 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1038 /// Word Swap Bytes Within Halfwords
1039 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1042 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1044 // FrameIndexes are legalized when they are operands from load/store
1045 // instructions. The same not happens for stack address copies, so an
1046 // add op with mem ComplexPattern is used and the stack address copy
1047 // can be matched. It's similar to Sparc LEA_ADDRi
1048 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1051 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1052 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1053 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1054 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1055 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1056 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1057 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1058 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1060 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1062 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1063 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1065 /// Move Control Registers From/To CPU Registers
1066 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1067 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1068 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1069 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1071 //===----------------------------------------------------------------------===//
1072 // Instruction aliases
1073 //===----------------------------------------------------------------------===//
1074 def : InstAlias<"move $dst, $src",
1075 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1076 Requires<[NotMips64]>;
1077 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1078 def : InstAlias<"addu $rs, $rt, $imm",
1079 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1080 def : InstAlias<"add $rs, $rt, $imm",
1081 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1082 def : InstAlias<"and $rs, $rt, $imm",
1083 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1084 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1085 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1086 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1087 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1088 def : InstAlias<"not $rt, $rs",
1089 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1090 def : InstAlias<"neg $rt, $rs",
1091 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1092 def : InstAlias<"negu $rt, $rs",
1093 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1094 def : InstAlias<"slt $rs, $rt, $imm",
1095 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1096 def : InstAlias<"xor $rs, $rt, $imm",
1097 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1098 def : InstAlias<"or $rs, $rt, $imm",
1099 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1100 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1101 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1102 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1103 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1104 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1105 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1106 def : InstAlias<"bnez $rs,$offset",
1107 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1108 def : InstAlias<"beqz $rs,$offset",
1109 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1110 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1112 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1113 def : InstAlias<"break", (BREAK 0, 0), 1>;
1114 def : InstAlias<"ei", (EI ZERO), 1>;
1115 def : InstAlias<"di", (DI ZERO), 1>;
1117 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1118 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1119 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1120 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1121 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1122 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1123 //===----------------------------------------------------------------------===//
1124 // Assembler Pseudo Instructions
1125 //===----------------------------------------------------------------------===//
1127 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1128 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1129 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1130 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1132 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1133 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1134 !strconcat(instr_asm, "\t$rt, $addr")> ;
1135 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1137 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1138 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1139 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1140 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1144 //===----------------------------------------------------------------------===//
1145 // Arbitrary patterns that map to one or more instructions
1146 //===----------------------------------------------------------------------===//
1148 // Load/store pattern templates.
1149 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1150 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1152 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1153 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1156 def : MipsPat<(i32 immSExt16:$in),
1157 (ADDiu ZERO, imm:$in)>;
1158 def : MipsPat<(i32 immZExt16:$in),
1159 (ORi ZERO, imm:$in)>;
1160 def : MipsPat<(i32 immLow16Zero:$in),
1161 (LUi (HI16 imm:$in))>;
1163 // Arbitrary immediates
1164 def : MipsPat<(i32 imm:$imm),
1165 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1167 // Carry MipsPatterns
1168 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1169 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1170 let Predicates = [HasStdEnc, NotDSP] in {
1171 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1172 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1173 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1174 (ADDiu GPR32:$src, imm:$imm)>;
1178 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1179 (JAL tglobaladdr:$dst)>;
1180 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1181 (JAL texternalsym:$dst)>;
1182 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1183 // (JALR GPR32:$dst)>;
1186 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1187 (TAILCALL tglobaladdr:$dst)>;
1188 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1189 (TAILCALL texternalsym:$dst)>;
1191 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1192 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1193 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1194 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1195 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1196 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1198 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1199 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1200 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1201 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1202 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1203 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1205 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1206 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1207 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1208 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1209 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1210 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1211 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1212 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1213 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1214 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1217 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1218 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1219 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1220 (ADDiu GPR32:$gp, tconstpool:$in)>;
1223 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1224 MipsPat<(MipsWrapper RC:$gp, node:$in),
1225 (ADDiuOp RC:$gp, node:$in)>;
1227 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1228 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1229 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1230 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1231 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1232 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1234 // Mips does not have "not", so we expand our way
1235 def : MipsPat<(not GPR32:$in),
1236 (NOR GPR32Opnd:$in, ZERO)>;
1239 let Predicates = [HasStdEnc] in {
1240 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1241 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1242 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1246 let Predicates = [HasStdEnc] in
1247 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1250 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1251 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1252 Instruction SLTiuOp, Register ZEROReg> {
1253 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1254 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1255 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1256 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1258 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1259 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1260 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1261 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1262 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1263 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1264 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1265 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1266 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1267 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1268 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1269 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1271 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1272 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1273 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1274 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1276 def : MipsPat<(brcond RC:$cond, bb:$dst),
1277 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1280 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1282 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1283 (BLEZ i32:$lhs, bb:$dst)>;
1284 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1285 (BGEZ i32:$lhs, bb:$dst)>;
1288 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1289 Instruction SLTuOp, Register ZEROReg> {
1290 def : MipsPat<(seteq RC:$lhs, 0),
1291 (SLTiuOp RC:$lhs, 1)>;
1292 def : MipsPat<(setne RC:$lhs, 0),
1293 (SLTuOp ZEROReg, RC:$lhs)>;
1294 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1295 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1296 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1297 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1300 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1301 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1302 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1303 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1304 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1307 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1308 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1309 (SLTOp RC:$rhs, RC:$lhs)>;
1310 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1311 (SLTuOp RC:$rhs, RC:$lhs)>;
1314 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1315 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1316 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1317 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1318 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1321 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1322 Instruction SLTiuOp> {
1323 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1324 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1325 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1326 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1329 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1330 defm : SetlePats<GPR32, SLT, SLTu>;
1331 defm : SetgtPats<GPR32, SLT, SLTu>;
1332 defm : SetgePats<GPR32, SLT, SLTu>;
1333 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1336 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1338 // mflo/hi patterns.
1339 def : MipsPat<(i32 (ExtractLOHI ACC64:$ac, imm:$lohi_idx)),
1340 (EXTRACT_SUBREG ACC64:$ac, imm:$lohi_idx)>;
1342 // Load halfword/word patterns.
1343 let AddedComplexity = 40 in {
1344 let Predicates = [HasStdEnc] in {
1345 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1346 def : LoadRegImmPat<LH, i32, sextloadi16>;
1347 def : LoadRegImmPat<LW, i32, load>;
1351 //===----------------------------------------------------------------------===//
1352 // Floating Point Support
1353 //===----------------------------------------------------------------------===//
1355 include "MipsInstrFPU.td"
1356 include "Mips64InstrInfo.td"
1357 include "MipsCondMov.td"
1362 include "Mips16InstrFormats.td"
1363 include "Mips16InstrInfo.td"
1366 include "MipsDSPInstrFormats.td"
1367 include "MipsDSPInstrInfo.td"
1370 include "MipsMSAInstrFormats.td"
1371 include "MipsMSAInstrInfo.td"
1374 include "MicroMipsInstrFormats.td"
1375 include "MicroMipsInstrInfo.td"