1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
79 // These are target-independent nodes, but have target-specific formats.
80 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
81 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
82 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
83 [SDNPHasChain, SDNPSideEffect,
84 SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
93 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
94 [SDNPOptInGlue, SDNPOutGlue]>;
97 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
99 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
102 // Target constant nodes that are not part of any isel patterns and remain
103 // unchanged can cause instructions with illegal operands to be emitted.
104 // Wrapper node patterns give the instruction selector a chance to replace
105 // target constant nodes that would otherwise remain unchanged with ADDiu
106 // nodes. Without these wrapper node patterns, the following conditional move
107 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
109 // movn %got(d)($gp), %got(c)($gp), $4
110 // This instruction is illegal since movn can take only register operands.
112 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
114 // Pointer to dynamically allocated stack area.
115 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
116 [SDNPHasChain, SDNPInGlue]>;
118 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
120 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
121 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
123 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
124 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
125 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
128 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
129 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
134 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
135 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
138 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
140 //===----------------------------------------------------------------------===//
141 // Mips Instruction Predicate Definitions.
142 //===----------------------------------------------------------------------===//
143 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
144 AssemblerPredicate<"FeatureSEInReg">;
145 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
146 AssemblerPredicate<"FeatureBitCount">;
147 def HasSwap : Predicate<"Subtarget.hasSwap()">,
148 AssemblerPredicate<"FeatureSwap">;
149 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
150 AssemblerPredicate<"FeatureCondMov">;
151 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
152 AssemblerPredicate<"FeatureMips32">;
153 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
154 AssemblerPredicate<"FeatureMips32r2">;
155 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
156 AssemblerPredicate<"FeatureMips64">;
157 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
158 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
159 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
160 AssemblerPredicate<"!FeatureMips64">;
161 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
162 AssemblerPredicate<"FeatureMips64r2">;
163 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
164 AssemblerPredicate<"FeatureN64">;
165 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
166 AssemblerPredicate<"!FeatureN64">;
167 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
168 AssemblerPredicate<"FeatureMips16">;
169 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
170 AssemblerPredicate<"FeatureMips32">;
171 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
172 AssemblerPredicate<"FeatureMips32">;
173 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
174 AssemblerPredicate<"FeatureMips32">;
175 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
176 AssemblerPredicate<"!FeatureMips16">;
178 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
179 let Predicates = [HasStandardEncoding];
196 bit isTerminator = 1;
199 bit hasExtraSrcRegAllocReq = 1;
200 bit isCodeGenOnly = 1;
203 //===----------------------------------------------------------------------===//
204 // Instruction format superclass
205 //===----------------------------------------------------------------------===//
207 include "MipsInstrFormats.td"
209 //===----------------------------------------------------------------------===//
210 // Mips Operand, Complex Patterns and Transformations Definitions.
211 //===----------------------------------------------------------------------===//
213 // Instruction operand types
214 def jmptarget : Operand<OtherVT> {
215 let EncoderMethod = "getJumpTargetOpValue";
217 def brtarget : Operand<OtherVT> {
218 let EncoderMethod = "getBranchTargetOpValue";
219 let OperandType = "OPERAND_PCREL";
220 let DecoderMethod = "DecodeBranchTarget";
222 def calltarget : Operand<iPTR> {
223 let EncoderMethod = "getJumpTargetOpValue";
225 def calltarget64: Operand<i64>;
226 def simm16 : Operand<i32> {
227 let DecoderMethod= "DecodeSimm16";
229 def simm16_64 : Operand<i64>;
230 def shamt : Operand<i32>;
233 def uimm16 : Operand<i32> {
234 let PrintMethod = "printUnsignedImm";
237 def MipsMemAsmOperand : AsmOperandClass {
239 let ParserMethod = "parseMemOperand";
243 def mem : Operand<i32> {
244 let PrintMethod = "printMemOperand";
245 let MIOperandInfo = (ops CPURegs, simm16);
246 let EncoderMethod = "getMemEncoding";
247 let ParserMatchClass = MipsMemAsmOperand;
250 def mem64 : Operand<i64> {
251 let PrintMethod = "printMemOperand";
252 let MIOperandInfo = (ops CPU64Regs, simm16_64);
253 let EncoderMethod = "getMemEncoding";
254 let ParserMatchClass = MipsMemAsmOperand;
257 def mem_ea : Operand<i32> {
258 let PrintMethod = "printMemOperandEA";
259 let MIOperandInfo = (ops CPURegs, simm16);
260 let EncoderMethod = "getMemEncoding";
263 def mem_ea_64 : Operand<i64> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPU64Regs, simm16_64);
266 let EncoderMethod = "getMemEncoding";
269 // size operand of ext instruction
270 def size_ext : Operand<i32> {
271 let EncoderMethod = "getSizeExtEncoding";
272 let DecoderMethod = "DecodeExtSize";
275 // size operand of ins instruction
276 def size_ins : Operand<i32> {
277 let EncoderMethod = "getSizeInsEncoding";
278 let DecoderMethod = "DecodeInsSize";
281 // Transformation Function - get the lower 16 bits.
282 def LO16 : SDNodeXForm<imm, [{
283 return getImm(N, N->getZExtValue() & 0xFFFF);
286 // Transformation Function - get the higher 16 bits.
287 def HI16 : SDNodeXForm<imm, [{
288 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
291 // Node immediate fits as 16-bit sign extended on target immediate.
293 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
295 // Node immediate fits as 16-bit zero extended on target immediate.
296 // The LO16 param means that only the lower 16 bits of the node
297 // immediate are caught.
299 def immZExt16 : PatLeaf<(imm), [{
300 if (N->getValueType(0) == MVT::i32)
301 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
303 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
306 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
307 def immLow16Zero : PatLeaf<(imm), [{
308 int64_t Val = N->getSExtValue();
309 return isInt<32>(Val) && !(Val & 0xffff);
312 // shamt field must fit in 5 bits.
313 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
315 // Mips Address Mode! SDNode frameindex could possibily be a match
316 // since load and store instructions from stack used it.
318 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
320 //===----------------------------------------------------------------------===//
321 // Instructions specific format
322 //===----------------------------------------------------------------------===//
324 /// Move Control Registers From/To CPU Registers
325 def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
326 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
327 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
329 def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
330 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
331 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
333 def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
334 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
335 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
337 def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
338 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
339 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
341 // Arithmetic and logical instructions with 3 register operands.
342 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
343 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
344 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
345 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
346 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
348 let isCommutable = isComm;
349 let isReMaterializable = 1;
352 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
353 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
354 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
355 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
357 let isCommutable = isComm;
360 // Arithmetic and logical instructions with 2 register operands.
361 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
362 Operand Od, PatLeaf imm_type, RegisterClass RC> :
363 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
364 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
365 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
366 let isReMaterializable = 1;
369 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
370 Operand Od, PatLeaf imm_type, RegisterClass RC> :
371 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
372 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
374 // Arithmetic Multiply ADD/SUB
375 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
376 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
377 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
378 !strconcat(instr_asm, "\t$rs, $rt"),
379 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
382 let isCommutable = isComm;
386 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
387 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
388 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
389 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
391 let isCommutable = 1;
395 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
396 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
398 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
399 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
400 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
404 // 32-bit shift instructions.
405 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
407 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
409 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
410 SDNode OpNode, RegisterClass RC>:
411 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
412 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
413 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
414 let shamt = isRotate;
417 // Load Upper Imediate
418 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
419 FI<op, (outs RC:$rt), (ins Imm:$imm16),
420 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
422 let neverHasSideEffects = 1;
423 let isReMaterializable = 1;
426 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
427 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
429 let Inst{25-21} = addr{20-16};
430 let Inst{15-0} = addr{15-0};
431 let DecoderMethod = "DecodeMem";
435 let canFoldAsLoad = 1 in
436 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
437 Operand MemOpnd, bit Pseudo>:
438 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
439 !strconcat(instr_asm, "\t$rt, $addr"),
440 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
441 let isPseudo = Pseudo;
444 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
445 Operand MemOpnd, bit Pseudo>:
446 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
447 !strconcat(instr_asm, "\t$rt, $addr"),
448 [(OpNode RC:$rt, addr:$addr)], IIStore> {
449 let isPseudo = Pseudo;
453 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
455 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
456 Requires<[NotN64, HasStandardEncoding]>;
457 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
458 Requires<[IsN64, HasStandardEncoding]> {
459 let DecoderNamespace = "Mips64";
460 let isCodeGenOnly = 1;
465 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
467 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
468 Requires<[NotN64, HasStandardEncoding]>;
469 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
470 Requires<[IsN64, HasStandardEncoding]> {
471 let DecoderNamespace = "Mips64";
472 let isCodeGenOnly = 1;
477 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
479 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
480 Requires<[NotN64, HasStandardEncoding]>;
481 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
482 Requires<[IsN64, HasStandardEncoding]> {
483 let DecoderNamespace = "Mips64";
484 let isCodeGenOnly = 1;
489 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
491 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
492 Requires<[NotN64, HasStandardEncoding]>;
493 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
494 Requires<[IsN64, HasStandardEncoding]> {
495 let DecoderNamespace = "Mips64";
496 let isCodeGenOnly = 1;
500 // Load/Store Left/Right
501 let canFoldAsLoad = 1 in
502 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
503 RegisterClass RC, Operand MemOpnd> :
504 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
505 !strconcat(instr_asm, "\t$rt, $addr"),
506 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
507 string Constraints = "$src = $rt";
510 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
511 RegisterClass RC, Operand MemOpnd>:
512 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
513 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
516 // 32-bit load left/right.
517 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
518 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
519 Requires<[NotN64, HasStandardEncoding]>;
520 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
521 Requires<[IsN64, HasStandardEncoding]> {
522 let DecoderNamespace = "Mips64";
523 let isCodeGenOnly = 1;
527 // 64-bit load left/right.
528 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
529 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
530 Requires<[NotN64, HasStandardEncoding]>;
531 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
532 Requires<[IsN64, HasStandardEncoding]> {
533 let DecoderNamespace = "Mips64";
534 let isCodeGenOnly = 1;
538 // 32-bit store left/right.
539 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
540 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
541 Requires<[NotN64, HasStandardEncoding]>;
542 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
543 Requires<[IsN64, HasStandardEncoding]> {
544 let DecoderNamespace = "Mips64";
545 let isCodeGenOnly = 1;
549 // 64-bit store left/right.
550 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
551 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
552 Requires<[NotN64, HasStandardEncoding]>;
553 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
554 Requires<[IsN64, HasStandardEncoding]> {
555 let DecoderNamespace = "Mips64";
556 let isCodeGenOnly = 1;
560 // Conditional Branch
561 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
562 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
563 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
564 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
566 let isTerminator = 1;
567 let hasDelaySlot = 1;
571 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
573 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
574 !strconcat(instr_asm, "\t$rs, $imm16"),
575 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
578 let isTerminator = 1;
579 let hasDelaySlot = 1;
584 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
586 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
587 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
588 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
593 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
594 PatLeaf imm_type, RegisterClass RC>:
595 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
596 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
597 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
601 class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
602 SDPatternOperator operator, SDPatternOperator targetoperator>:
603 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
604 [(operator targetoperator:$target)], IIBranch> {
607 let hasDelaySlot = 1;
608 let DecoderMethod = "DecodeJumpTarget";
612 // Unconditional branch
613 class UncondBranch<bits<6> op, string instr_asm>:
614 BranchBase<op, (outs), (ins brtarget:$imm16),
615 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
619 let isTerminator = 1;
621 let hasDelaySlot = 1;
622 let Predicates = [RelocPIC, HasStandardEncoding];
626 // Base class for indirect branch and return instruction classes.
627 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
628 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
629 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
636 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
638 let isIndirectBranch = 1;
641 // Return instruction
642 class RetBase<RegisterClass RC>: JumpFR<RC> {
644 let isCodeGenOnly = 1;
646 let hasExtraSrcRegAllocReq = 1;
649 // Jump and Link (Call)
650 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
651 class JumpLink<bits<6> op, string instr_asm>:
652 FJ<op, (outs), (ins calltarget:$target),
653 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
655 let DecoderMethod = "DecodeJumpTarget";
658 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
660 FR<op, func, (outs), (ins RC:$rs),
661 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
667 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
668 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
669 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
675 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
676 RegisterClass RC, list<Register> DefRegs>:
677 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
678 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
681 let isCommutable = 1;
683 let neverHasSideEffects = 1;
686 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
687 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
689 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
690 RegisterClass RC, list<Register> DefRegs>:
691 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
692 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
693 [(op RC:$rs, RC:$rt)], itin> {
699 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
700 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
703 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
704 list<Register> UseRegs>:
705 FR<0x00, func, (outs RC:$rd), (ins),
706 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
711 let neverHasSideEffects = 1;
714 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
715 list<Register> DefRegs>:
716 FR<0x00, func, (outs), (ins RC:$rs),
717 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
722 let neverHasSideEffects = 1;
725 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
726 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
727 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
728 let isCodeGenOnly = 1;
731 // Count Leading Ones/Zeros in Word
732 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
733 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
734 !strconcat(instr_asm, "\t$rd, $rs"),
735 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
736 Requires<[HasBitCount, HasStandardEncoding]> {
741 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
742 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
743 !strconcat(instr_asm, "\t$rd, $rs"),
744 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
745 Requires<[HasBitCount, HasStandardEncoding]> {
750 // Sign Extend in Register.
751 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
753 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
754 !strconcat(instr_asm, "\t$rd, $rt"),
755 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
758 let Predicates = [HasSEInReg, HasStandardEncoding];
762 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
763 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
764 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
767 let Predicates = [HasSwap, HasStandardEncoding];
768 let neverHasSideEffects = 1;
772 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
773 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
774 "rdhwr\t$rt, $rd", [], IIAlu> {
780 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
781 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
782 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
783 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
788 let Predicates = [HasMips32r2, HasStandardEncoding];
791 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
792 FR<0x1f, _funct, (outs RC:$rt),
793 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
794 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
795 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
801 let Predicates = [HasMips32r2, HasStandardEncoding];
802 let Constraints = "$src = $rt";
805 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
806 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
808 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
809 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
810 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
812 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
813 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
814 Requires<[NotN64, HasStandardEncoding]>;
815 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
816 Requires<[IsN64, HasStandardEncoding]> {
817 let DecoderNamespace = "Mips64";
821 // Atomic Compare & Swap.
822 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
824 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
825 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
826 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
828 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
829 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
830 Requires<[NotN64, HasStandardEncoding]>;
831 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
832 Requires<[IsN64, HasStandardEncoding]> {
833 let DecoderNamespace = "Mips64";
837 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
838 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
839 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
843 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
844 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
845 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
847 let Constraints = "$rt = $dst";
850 //===----------------------------------------------------------------------===//
851 // Pseudo instructions
852 //===----------------------------------------------------------------------===//
855 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
856 def RetRA : PseudoSE<(outs), (ins), "", [(MipsRet)]>;
858 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
859 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
860 "!ADJCALLSTACKDOWN $amt",
861 [(callseq_start timm:$amt)]>;
862 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
863 "!ADJCALLSTACKUP $amt1",
864 [(callseq_end timm:$amt1, timm:$amt2)]>;
867 // When handling PIC code the assembler needs .cpload and .cprestore
868 // directives. If the real instructions corresponding these directives
869 // are used, we have the same behavior, but get also a bunch of warnings
870 // from the assembler.
871 let neverHasSideEffects = 1 in
872 def CPRESTORE : PseudoSE<(outs), (ins i32imm:$loc, CPURegs:$gp),
873 ".cprestore\t$loc", []>;
875 let usesCustomInserter = 1 in {
876 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
877 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
878 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
879 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
880 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
881 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
882 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
883 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
884 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
885 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
886 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
887 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
888 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
889 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
890 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
891 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
892 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
893 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
895 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
896 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
897 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
899 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
900 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
901 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
904 //===----------------------------------------------------------------------===//
905 // Instruction definition
906 //===----------------------------------------------------------------------===//
908 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
909 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
910 !strconcat(instr_asm, "\t$rt, $imm32")> ;
911 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
913 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
914 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
915 !strconcat(instr_asm, "\t$rt, $addr")> ;
916 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
918 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
919 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
920 !strconcat(instr_asm, "\t$rt, $imm32")> ;
921 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
923 //===----------------------------------------------------------------------===//
924 // MipsI Instructions
925 //===----------------------------------------------------------------------===//
927 /// Arithmetic Instructions (ALU Immediate)
928 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
929 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
930 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
931 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
932 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
933 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
934 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
935 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
937 /// Arithmetic Instructions (3-Operand, R-Type)
938 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
939 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
940 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
941 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
942 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
943 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
944 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
945 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
946 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
947 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
949 /// Shift Instructions
950 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
951 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
952 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
953 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
954 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
955 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
957 // Rotate Instructions
958 let Predicates = [HasMips32r2, HasStandardEncoding] in {
959 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
960 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
963 /// Load and Store Instructions
965 defm LB : LoadM32<0x20, "lb", sextloadi8>;
966 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
967 defm LH : LoadM32<0x21, "lh", sextloadi16>;
968 defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
969 defm LW : LoadM32<0x23, "lw", load>;
970 defm SB : StoreM32<0x28, "sb", truncstorei8>;
971 defm SH : StoreM32<0x29, "sh", truncstorei16>;
972 defm SW : StoreM32<0x2b, "sw", store>;
974 /// load/store left/right
975 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
976 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
977 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
978 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
980 let hasSideEffects = 1 in
981 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
982 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
987 let Inst{10-6} = stype;
991 /// Load-linked, Store-conditional
992 def LL : LLBase<0x30, "ll", CPURegs, mem>,
993 Requires<[NotN64, HasStandardEncoding]>;
994 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
995 Requires<[IsN64, HasStandardEncoding]> {
996 let DecoderNamespace = "Mips64";
999 def SC : SCBase<0x38, "sc", CPURegs, mem>,
1000 Requires<[NotN64, HasStandardEncoding]>;
1001 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
1002 Requires<[IsN64, HasStandardEncoding]> {
1003 let DecoderNamespace = "Mips64";
1006 /// Jump and Branch Instructions
1007 def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
1008 Requires<[RelocStatic, HasStandardEncoding]>, IsBranch;
1009 def JR : IndirectBranch<CPURegs>;
1010 def B : UncondBranch<0x04, "b">;
1011 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
1012 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
1013 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
1014 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
1015 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
1016 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
1018 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
1019 hasDelaySlot = 1, Defs = [RA] in
1020 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
1022 def JAL : JumpLink<0x03, "jal">;
1023 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
1024 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
1025 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
1026 def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
1027 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
1029 def RET : RetBase<CPURegs>;
1031 /// Multiply and Divide Instructions.
1032 def MULT : Mult32<0x18, "mult", IIImul>;
1033 def MULTu : Mult32<0x19, "multu", IIImul>;
1034 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1035 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1037 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1038 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1039 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1040 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1042 /// Sign Ext In Register Instructions.
1043 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1044 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1047 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1048 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1050 /// Word Swap Bytes Within Halfwords
1051 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1055 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1057 // FrameIndexes are legalized when they are operands from load/store
1058 // instructions. The same not happens for stack address copies, so an
1059 // add op with mem ComplexPattern is used and the stack address copy
1060 // can be matched. It's similar to Sparc LEA_ADDRi
1061 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1063 // DynAlloc node points to dynamically allocated stack space.
1064 // $sp is added to the list of implicitly used registers to prevent dead code
1065 // elimination from removing instructions that modify $sp.
1067 def DynAlloc : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1070 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1071 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1072 def MSUB : MArithR<4, "msub", MipsMSub>;
1073 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1075 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1076 // it is a real instruction.
1077 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
1078 Requires<[HasMips32, HasStandardEncoding]>;
1080 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1082 def EXT : ExtBase<0, "ext", CPURegs>;
1083 def INS : InsBase<4, "ins", CPURegs>;
1085 //===----------------------------------------------------------------------===//
1086 // Instruction aliases
1087 //===----------------------------------------------------------------------===//
1088 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
1089 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
1090 def : InstAlias<"addu $rs,$rt,$imm",
1091 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1092 def : InstAlias<"add $rs,$rt,$imm",
1093 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1094 def : InstAlias<"and $rs,$rt,$imm",
1095 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1096 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
1097 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
1098 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
1099 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
1100 def : InstAlias<"slt $rs,$rt,$imm",
1101 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1102 def : InstAlias<"xor $rs,$rt,$imm",
1103 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1105 //===----------------------------------------------------------------------===//
1106 // Arbitrary patterns that map to one or more instructions
1107 //===----------------------------------------------------------------------===//
1110 def : MipsPat<(i32 immSExt16:$in),
1111 (ADDiu ZERO, imm:$in)>;
1112 def : MipsPat<(i32 immZExt16:$in),
1113 (ORi ZERO, imm:$in)>;
1114 def : MipsPat<(i32 immLow16Zero:$in),
1115 (LUi (HI16 imm:$in))>;
1117 // Arbitrary immediates
1118 def : MipsPat<(i32 imm:$imm),
1119 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1121 // Carry MipsPatterns
1122 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1123 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1124 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1125 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1126 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1127 (ADDiu CPURegs:$src, imm:$imm)>;
1130 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1131 (JAL tglobaladdr:$dst)>;
1132 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1133 (JAL texternalsym:$dst)>;
1134 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1135 // (JALR CPURegs:$dst)>;
1138 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1139 (TAILCALL tglobaladdr:$dst)>;
1140 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1141 (TAILCALL texternalsym:$dst)>;
1143 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1144 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1145 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1146 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1147 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1149 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1150 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1151 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1152 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1153 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1155 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1156 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1157 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1158 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1159 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1160 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1161 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1162 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1163 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1164 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1167 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1168 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1169 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1170 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1173 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1174 MipsPat<(MipsWrapper RC:$gp, node:$in),
1175 (ADDiuOp RC:$gp, node:$in)>;
1177 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1178 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1179 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1180 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1181 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1182 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1184 // Mips does not have "not", so we expand our way
1185 def : MipsPat<(not CPURegs:$in),
1186 (NOR CPURegs:$in, ZERO)>;
1189 let Predicates = [NotN64, HasStandardEncoding] in {
1190 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1191 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1192 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1194 let Predicates = [IsN64, HasStandardEncoding] in {
1195 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1196 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1197 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1201 let Predicates = [NotN64, HasStandardEncoding] in {
1202 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1204 let Predicates = [IsN64, HasStandardEncoding] in {
1205 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1209 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1210 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1211 Instruction SLTiuOp, Register ZEROReg> {
1212 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1213 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1214 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1215 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1217 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1218 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1219 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1220 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1221 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1222 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1223 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1224 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1226 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1227 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1228 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1229 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1231 def : MipsPat<(brcond RC:$cond, bb:$dst),
1232 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1235 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1238 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1239 Instruction SLTuOp, Register ZEROReg> {
1240 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1241 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1242 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1243 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1246 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1247 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1248 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1249 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1250 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1253 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1254 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1255 (SLTOp RC:$rhs, RC:$lhs)>;
1256 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1257 (SLTuOp RC:$rhs, RC:$lhs)>;
1260 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1261 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1262 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1263 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1264 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1267 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1268 Instruction SLTiuOp> {
1269 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1270 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1271 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1272 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1275 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1276 defm : SetlePats<CPURegs, SLT, SLTu>;
1277 defm : SetgtPats<CPURegs, SLT, SLTu>;
1278 defm : SetgePats<CPURegs, SLT, SLTu>;
1279 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1281 // select MipsDynAlloc
1282 def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1285 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1287 //===----------------------------------------------------------------------===//
1288 // Floating Point Support
1289 //===----------------------------------------------------------------------===//
1291 include "MipsInstrFPU.td"
1292 include "Mips64InstrInfo.td"
1293 include "MipsCondMov.td"
1298 include "Mips16InstrFormats.td"
1299 include "Mips16InstrInfo.td"
1302 include "MipsDSPInstrFormats.td"
1303 include "MipsDSPInstrInfo.td"