1 //===- MipsInstrInfo.td - Mips Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
20 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def SDT_MipsSelectCC : SDTypeProfile<1, 3, [SDTCisSameAs<0, 2>,
23 SDTCisSameAs<2, 3>, SDTCisInt<1>]>;
24 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 SDTCisSameAs<1, 2>, SDTCisSameAs<3, 4>,
27 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
28 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
29 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
30 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
33 def SDT_MipsDivRem : SDTypeProfile<0, 2,
38 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
39 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
42 // Hi and Lo nodes are used to handle global addresses. Used on
43 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
44 // static model. (nothing to do with Mips Registers Hi and Lo)
45 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
46 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
47 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
50 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
53 // These are target-independent nodes, but have target-specific formats.
54 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
55 [SDNPHasChain, SDNPOutGlue]>;
56 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
57 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
59 // Select Condition Code
60 def MipsSelectCC : SDNode<"MipsISD::SelectCC", SDT_MipsSelectCC>;
63 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
64 [SDNPOptInGlue, SDNPOutGlue]>;
65 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
66 [SDNPOptInGlue, SDNPOutGlue]>;
67 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
68 [SDNPOptInGlue, SDNPOutGlue]>;
69 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
70 [SDNPOptInGlue, SDNPOutGlue]>;
73 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
75 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
78 //===----------------------------------------------------------------------===//
79 // Mips Instruction Predicate Definitions.
80 //===----------------------------------------------------------------------===//
81 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
82 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
83 def HasSwap : Predicate<"Subtarget.hasSwap()">;
84 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
85 def IsMips32 : Predicate<"Subtarget.isMips32()">;
86 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
88 //===----------------------------------------------------------------------===//
89 // Mips Operand, Complex Patterns and Transformations Definitions.
90 //===----------------------------------------------------------------------===//
92 // Instruction operand types
93 def brtarget : Operand<OtherVT>;
94 def calltarget : Operand<i32>;
95 def simm16 : Operand<i32>;
96 def shamt : Operand<i32>;
99 def uimm16 : Operand<i32> {
100 let PrintMethod = "printUnsignedImm";
104 def mem : Operand<i32> {
105 let PrintMethod = "printMemOperand";
106 let MIOperandInfo = (ops simm16, CPURegs);
109 // Transformation Function - get the lower 16 bits.
110 def LO16 : SDNodeXForm<imm, [{
111 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
114 // Transformation Function - get the higher 16 bits.
115 def HI16 : SDNodeXForm<imm, [{
116 return getI32Imm((unsigned)N->getZExtValue() >> 16);
119 // Node immediate fits as 16-bit sign extended on target immediate.
121 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
123 // Node immediate fits as 16-bit zero extended on target immediate.
124 // The LO16 param means that only the lower 16 bits of the node
125 // immediate are caught.
127 def immZExt16 : PatLeaf<(imm), [{
128 if (N->getValueType(0) == MVT::i32)
129 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
131 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
134 // shamt field must fit in 5 bits.
135 def immZExt5 : PatLeaf<(imm), [{
136 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
139 // Mips Address Mode! SDNode frameindex could possibily be a match
140 // since load and store instructions from stack used it.
141 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
143 //===----------------------------------------------------------------------===//
144 // Instructions specific format
145 //===----------------------------------------------------------------------===//
147 // Arithmetic 3 register operands
148 let isCommutable = 1 in
149 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
150 InstrItinClass itin>:
151 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
152 !strconcat(instr_asm, "\t$dst, $b, $c"),
153 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
155 let isCommutable = 1 in
156 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
157 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
158 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
160 // Arithmetic 2 register operands
161 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
162 Operand Od, PatLeaf imm_type> :
163 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
164 !strconcat(instr_asm, "\t$dst, $b, $c"),
165 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
167 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
168 Operand Od, PatLeaf imm_type> :
169 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
170 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
172 // Arithmetic Multiply ADD/SUB
173 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
174 class MArithR<bits<6> func, string instr_asm, SDNode op> :
175 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
176 !strconcat(instr_asm, "\t$rs, $rt"),
177 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul>;
180 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
181 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
182 !strconcat(instr_asm, "\t$dst, $b, $c"),
183 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
185 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
186 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
187 !strconcat(instr_asm, "\t$dst, $b, $c"),
188 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
190 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
191 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
192 !strconcat(instr_asm, "\t$dst, $b, $c"),
193 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
196 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
198 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
199 !strconcat(instr_asm, "\t$dst, $b, $c"),
200 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
204 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
206 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
207 !strconcat(instr_asm, "\t$dst, $b, $c"),
208 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
212 // Load Upper Imediate
213 class LoadUpper<bits<6> op, string instr_asm>:
217 !strconcat(instr_asm, "\t$dst, $imm"),
221 let canFoldAsLoad = 1, hasDelaySlot = 1 in
222 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
223 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
224 !strconcat(instr_asm, "\t$dst, $addr"),
225 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
227 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
228 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
229 !strconcat(instr_asm, "\t$dst, $addr"),
230 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
232 // Conditional Branch
233 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
234 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
235 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
236 !strconcat(instr_asm, "\t$a, $b, $offset"),
237 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
240 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
241 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
242 !strconcat(instr_asm, "\t$src, $offset"),
243 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
248 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
250 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
251 !strconcat(instr_asm, "\t$dst, $b, $c"),
252 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
255 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
256 Operand Od, PatLeaf imm_type>:
257 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
258 !strconcat(instr_asm, "\t$dst, $b, $c"),
259 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
262 // Unconditional branch
263 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
264 class JumpFJ<bits<6> op, string instr_asm>:
265 FJ<op, (outs), (ins brtarget:$target),
266 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
268 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
269 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
270 FR<op, func, (outs), (ins CPURegs:$target),
271 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
273 // Jump and Link (Call)
274 let isCall=1, hasDelaySlot=1,
275 // All calls clobber the non-callee saved registers...
276 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
277 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
278 class JumpLink<bits<6> op, string instr_asm>:
279 FJ<op, (outs), (ins calltarget:$target, variable_ops),
280 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
284 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
285 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
286 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
288 class BranchLink<string instr_asm>:
289 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
290 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
294 let Defs = [HI, LO] in {
295 class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
296 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
297 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
299 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
300 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
301 !strconcat(instr_asm, "\t$$zero, $a, $b"),
302 [(op CPURegs:$a, CPURegs:$b)], itin>;
306 class MoveFromLOHI<bits<6> func, string instr_asm>:
307 FR<0x00, func, (outs CPURegs:$dst), (ins),
308 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
310 class MoveToLOHI<bits<6> func, string instr_asm>:
311 FR<0x00, func, (outs), (ins CPURegs:$src),
312 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
314 class EffectiveAddress<string instr_asm> :
315 FI<0x09, (outs CPURegs:$dst), (ins mem:$addr),
316 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
318 // Count Leading Ones/Zeros in Word
319 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
320 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
321 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
322 Requires<[HasBitCount]> {
327 // Sign Extend in Register.
328 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
329 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
330 !strconcat(instr_asm, "\t$dst, $src"),
331 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
334 class ByteSwap<bits<6> func, string instr_asm>:
335 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
336 !strconcat(instr_asm, "\t$dst, $src"),
337 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
340 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
341 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
342 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
345 //===----------------------------------------------------------------------===//
346 // Pseudo instructions
347 //===----------------------------------------------------------------------===//
349 // As stack alignment is always done with addiu, we need a 16-bit immediate
350 let Defs = [SP], Uses = [SP] in {
351 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
352 "!ADJCALLSTACKDOWN $amt",
353 [(callseq_start timm:$amt)]>;
354 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
355 "!ADJCALLSTACKUP $amt1",
356 [(callseq_end timm:$amt1, timm:$amt2)]>;
359 // Some assembly macros need to avoid pseudoinstructions and assembler
360 // automatic reodering, we should reorder ourselves.
361 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
362 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
363 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
364 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
366 // These macros are inserted to prevent GAS from complaining
367 // when using the AT register.
368 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
369 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
371 // When handling PIC code the assembler needs .cpload and .cprestore
372 // directives. If the real instructions corresponding these directives
373 // are used, we have the same behavior, but get also a bunch of warnings
374 // from the assembler.
375 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
376 def CPRESTORE : MipsPseudo<(outs), (ins uimm16:$loc), ".cprestore\t$loc\n", []>;
378 // The supported Mips ISAs dont have any instruction close to the SELECT_CC
379 // operation. The solution is to create a Mips pseudo SELECT_CC instruction
380 // (MipsSelectCC), use LowerSELECT_CC to generate this instruction and finally
381 // replace it for real supported nodes into EmitInstrWithCustomInserter
382 let usesCustomInserter = 1 in {
383 class PseudoSelCC<RegisterClass RC, string asmstr>:
384 MipsPseudo<(outs RC:$dst), (ins CPURegs:$CmpRes, RC:$T, RC:$F), asmstr,
385 [(set RC:$dst, (MipsSelectCC CPURegs:$CmpRes, RC:$T, RC:$F))]>;
388 def Select_CC : PseudoSelCC<CPURegs, "# MipsSelect_CC_i32">;
390 //===----------------------------------------------------------------------===//
391 // Instruction definition
392 //===----------------------------------------------------------------------===//
394 //===----------------------------------------------------------------------===//
395 // MipsI Instructions
396 //===----------------------------------------------------------------------===//
398 /// Arithmetic Instructions (ALU Immediate)
399 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
400 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
401 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
402 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
403 def ANDi : LogicI<0x0c, "andi", and>;
404 def ORi : LogicI<0x0d, "ori", or>;
405 def XORi : LogicI<0x0e, "xori", xor>;
406 def LUi : LoadUpper<0x0f, "lui">;
408 /// Arithmetic Instructions (3-Operand, R-Type)
409 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
410 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
411 def ADD : ArithOverflowR<0x00, 0x20, "add">;
412 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
413 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
414 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
415 def AND : LogicR<0x24, "and", and>;
416 def OR : LogicR<0x25, "or", or>;
417 def XOR : LogicR<0x26, "xor", xor>;
418 def NOR : LogicNOR<0x00, 0x27, "nor">;
420 /// Shift Instructions
421 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
422 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
423 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
424 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
425 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
426 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
428 // Rotate Instructions
429 let Predicates = [IsMips32r2] in {
430 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
431 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
434 /// Load and Store Instructions
435 def LB : LoadM<0x20, "lb", sextloadi8>;
436 def LBu : LoadM<0x24, "lbu", zextloadi8>;
437 def LH : LoadM<0x21, "lh", sextloadi16>;
438 def LHu : LoadM<0x25, "lhu", zextloadi16>;
439 def LW : LoadM<0x23, "lw", load>;
440 def SB : StoreM<0x28, "sb", truncstorei8>;
441 def SH : StoreM<0x29, "sh", truncstorei16>;
442 def SW : StoreM<0x2b, "sw", store>;
444 /// Jump and Branch Instructions
445 def J : JumpFJ<0x02, "j">;
446 def JR : JumpFR<0x00, 0x08, "jr">;
447 def JAL : JumpLink<0x03, "jal">;
448 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
449 def BEQ : CBranch<0x04, "beq", seteq>;
450 def BNE : CBranch<0x05, "bne", setne>;
453 def BGEZ : CBranchZero<0x01, "bgez", setge>;
456 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
457 def BLEZ : CBranchZero<0x07, "blez", setle>;
458 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
461 def BGEZAL : BranchLink<"bgezal">;
462 def BLTZAL : BranchLink<"bltzal">;
464 let isReturn=1, isTerminator=1, hasDelaySlot=1,
465 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
466 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
467 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
469 /// Multiply and Divide Instructions.
470 def MULT : Mul<0x18, "mult", IIImul>;
471 def MULTu : Mul<0x19, "multu", IIImul>;
472 def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
473 def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
476 def MTHI : MoveToLOHI<0x11, "mthi">;
478 def MTLO : MoveToLOHI<0x13, "mtlo">;
481 def MFHI : MoveFromLOHI<0x10, "mfhi">;
483 def MFLO : MoveFromLOHI<0x12, "mflo">;
485 /// Sign Ext In Register Instructions.
486 let Predicates = [HasSEInReg] in {
487 let shamt = 0x10, rs = 0 in
488 def SEB : SignExtInReg<0x21, "seb", i8>;
490 let shamt = 0x18, rs = 0 in
491 def SEH : SignExtInReg<0x20, "seh", i16>;
495 def CLZ : CountLeading<0b100000, "clz",
496 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
497 def CLO : CountLeading<0b100001, "clo",
498 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
501 let Predicates = [HasSwap] in {
502 let shamt = 0x3, rs = 0 in
503 def WSBW : ByteSwap<0x20, "wsbw">;
507 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
508 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
510 let Predicates = [HasCondMov], Constraints = "$F = $dst" in {
511 def MOVN : CondMov<0x0a, "movn", MIPS_CMOV_NZERO>;
512 def MOVZ : CondMov<0x0b, "movz", MIPS_CMOV_ZERO>;
517 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
519 // FrameIndexes are legalized when they are operands from load/store
520 // instructions. The same not happens for stack address copies, so an
521 // add op with mem ComplexPattern is used and the stack address copy
522 // can be matched. It's similar to Sparc LEA_ADDRi
523 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, ${addr:stackloc}">;
526 def MADD : MArithR<0, "madd", MipsMAdd>;
527 def MADDU : MArithR<1, "maddu", MipsMAddu>;
528 def MSUB : MArithR<4, "msub", MipsMSub>;
529 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
531 // MUL is a assembly macro in the current used ISAs. In recent ISA's
532 // it is a real instruction.
533 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>, Requires<[IsMips32]>;
535 //===----------------------------------------------------------------------===//
536 // Arbitrary patterns that map to one or more instructions
537 //===----------------------------------------------------------------------===//
540 def : Pat<(i32 immSExt16:$in),
541 (ADDiu ZERO, imm:$in)>;
542 def : Pat<(i32 immZExt16:$in),
543 (ORi ZERO, imm:$in)>;
545 // Arbitrary immediates
546 def : Pat<(i32 imm:$imm),
547 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
550 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
551 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
552 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
553 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
554 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
555 (ADDiu CPURegs:$src, imm:$imm)>;
558 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
559 (JAL tglobaladdr:$dst)>;
560 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
561 (JAL texternalsym:$dst)>;
562 //def : Pat<(MipsJmpLink CPURegs:$dst),
563 // (JALR CPURegs:$dst)>;
566 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
567 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
568 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
569 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
570 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
572 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
573 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
574 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
576 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
577 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
578 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
581 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
582 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
583 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
584 (ADDiu CPURegs:$gp, tconstpool:$in)>;
586 // Mips does not have "not", so we expand our way
587 def : Pat<(not CPURegs:$in),
588 (NOR CPURegs:$in, ZERO)>;
590 // extended load and stores
591 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
592 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
593 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
596 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
599 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
600 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
601 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
602 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
604 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
605 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
606 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
607 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
608 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
609 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
610 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
611 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
613 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
614 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
615 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
616 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
618 def : Pat<(brcond CPURegs:$cond, bb:$dst),
619 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
622 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
623 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$lhs, CPURegs:$rhs))>;
624 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
625 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs))>;
626 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), CPURegs:$T, CPURegs:$F),
627 (MOVZ CPURegs:$F, CPURegs:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs))>;
628 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), CPURegs:$T, CPURegs:$F),
629 (MOVZ CPURegs:$F, CPURegs:$T, (SLTiu CPURegs:$lh, immSExt16:$rh))>;
631 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
632 (MOVZ CPURegs:$F, CPURegs:$T, (SLT CPURegs:$rhs, CPURegs:$lhs))>;
633 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
634 (MOVZ CPURegs:$F, CPURegs:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs))>;
636 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
637 (MOVZ CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
638 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), CPURegs:$T, CPURegs:$F),
639 (MOVN CPURegs:$F, CPURegs:$T, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
641 def : Pat<(select CPURegs:$cond, CPURegs:$T, CPURegs:$F),
642 (MOVN CPURegs:$F, CPURegs:$T, CPURegs:$cond)>;
644 // select patterns with got access
645 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs),
646 (i32 tglobaladdr:$T), CPURegs:$F),
647 (MOVN CPURegs:$F, (ADDiu GP, tglobaladdr:$T),
648 (XOR CPURegs:$lhs, CPURegs:$rhs))>;
651 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
652 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
653 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
654 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
656 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
657 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
658 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
659 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
661 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
662 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
663 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
664 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
666 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
667 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
668 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
669 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
671 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
672 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
673 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
674 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
676 //===----------------------------------------------------------------------===//
677 // Floating Point Support
678 //===----------------------------------------------------------------------===//
680 include "MipsInstrFPU.td"