1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
47 SDTCisInt<2>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
49 SDTCisInt<2>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def IsMips32 : Predicate<"Subtarget.isMips32()">;
129 def IsMips32r2 : Predicate<"Subtarget.isMips32r2()">;
131 //===----------------------------------------------------------------------===//
132 // Mips Operand, Complex Patterns and Transformations Definitions.
133 //===----------------------------------------------------------------------===//
135 // Instruction operand types
136 def brtarget : Operand<OtherVT>;
137 def calltarget : Operand<i32>;
138 def simm16 : Operand<i32>;
139 def shamt : Operand<i32>;
142 def uimm16 : Operand<i32> {
143 let PrintMethod = "printUnsignedImm";
147 def mem : Operand<i32> {
148 let PrintMethod = "printMemOperand";
149 let MIOperandInfo = (ops CPURegs, simm16);
152 def mem_ea : Operand<i32> {
153 let PrintMethod = "printMemOperandEA";
154 let MIOperandInfo = (ops CPURegs, simm16);
157 // Transformation Function - get the lower 16 bits.
158 def LO16 : SDNodeXForm<imm, [{
159 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
162 // Transformation Function - get the higher 16 bits.
163 def HI16 : SDNodeXForm<imm, [{
164 return getI32Imm((unsigned)N->getZExtValue() >> 16);
167 // Node immediate fits as 16-bit sign extended on target immediate.
169 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
171 // Node immediate fits as 16-bit zero extended on target immediate.
172 // The LO16 param means that only the lower 16 bits of the node
173 // immediate are caught.
175 def immZExt16 : PatLeaf<(imm), [{
176 if (N->getValueType(0) == MVT::i32)
177 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
179 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
182 // shamt field must fit in 5 bits.
183 def immZExt5 : PatLeaf<(imm), [{
184 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
187 // Mips Address Mode! SDNode frameindex could possibily be a match
188 // since load and store instructions from stack used it.
189 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
191 //===----------------------------------------------------------------------===//
192 // Instructions specific format
193 //===----------------------------------------------------------------------===//
195 // Arithmetic 3 register operands
196 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
197 InstrItinClass itin, bit isComm = 0>:
198 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
199 !strconcat(instr_asm, "\t$dst, $b, $c"),
200 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin> {
201 let isCommutable = isComm;
204 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
206 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
207 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu> {
208 let isCommutable = isComm;
211 // Arithmetic 2 register operands
212 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
213 Operand Od, PatLeaf imm_type> :
214 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
215 !strconcat(instr_asm, "\t$dst, $b, $c"),
216 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
218 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
219 Operand Od, PatLeaf imm_type> :
220 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
221 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
223 // Arithmetic Multiply ADD/SUB
224 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
225 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
226 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
227 !strconcat(instr_asm, "\t$rs, $rt"),
228 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
229 let isCommutable = isComm;
233 let isCommutable = 1 in
234 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
235 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
236 !strconcat(instr_asm, "\t$dst, $b, $c"),
237 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
239 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
240 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
241 !strconcat(instr_asm, "\t$dst, $b, $c"),
242 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
244 let isCommutable = 1 in
245 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
246 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
247 !strconcat(instr_asm, "\t$dst, $b, $c"),
248 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
251 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
253 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
254 !strconcat(instr_asm, "\t$dst, $b, $c"),
255 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu> {
259 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
261 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
262 !strconcat(instr_asm, "\t$dst, $b, $c"),
263 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
267 // Load Upper Imediate
268 class LoadUpper<bits<6> op, string instr_asm>:
272 !strconcat(instr_asm, "\t$dst, $imm"),
276 let canFoldAsLoad = 1 in
277 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
278 FI<op, (outs CPURegs:$dst), (ins mem:$addr),
279 !strconcat(instr_asm, "\t$dst, $addr"),
280 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
282 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
283 FI<op, (outs), (ins CPURegs:$dst, mem:$addr),
284 !strconcat(instr_asm, "\t$dst, $addr"),
285 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
287 // Conditional Branch
288 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
289 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
290 FI<op, (outs), (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
291 !strconcat(instr_asm, "\t$a, $b, $offset"),
292 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
295 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
296 FI<op, (outs), (ins CPURegs:$src, brtarget:$offset),
297 !strconcat(instr_asm, "\t$src, $offset"),
298 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
303 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
305 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
306 !strconcat(instr_asm, "\t$dst, $b, $c"),
307 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
310 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
311 Operand Od, PatLeaf imm_type>:
312 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
313 !strconcat(instr_asm, "\t$dst, $b, $c"),
314 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
317 // Unconditional branch
318 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
319 class JumpFJ<bits<6> op, string instr_asm>:
320 FJ<op, (outs), (ins brtarget:$target),
321 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
323 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
324 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
325 FR<op, func, (outs), (ins CPURegs:$target),
326 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
328 // Jump and Link (Call)
329 let isCall=1, hasDelaySlot=1,
330 // All calls clobber the non-callee saved registers...
331 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
332 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
333 class JumpLink<bits<6> op, string instr_asm>:
334 FJ<op, (outs), (ins calltarget:$target, variable_ops),
335 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
339 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
340 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
341 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
343 class BranchLink<string instr_asm>:
344 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
345 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
349 let Defs = [HI, LO] in {
350 let isCommutable = 1 in
351 class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
352 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
353 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
355 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
356 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
357 !strconcat(instr_asm, "\t$$zero, $a, $b"),
358 [(op CPURegs:$a, CPURegs:$b)], itin>;
362 class MoveFromLOHI<bits<6> func, string instr_asm>:
363 FR<0x00, func, (outs CPURegs:$dst), (ins),
364 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
366 class MoveToLOHI<bits<6> func, string instr_asm>:
367 FR<0x00, func, (outs), (ins CPURegs:$src),
368 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
370 class EffectiveAddress<string instr_asm> :
371 FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr),
372 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
374 // Count Leading Ones/Zeros in Word
375 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
376 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
377 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
378 Requires<[HasBitCount]> {
383 // Sign Extend in Register.
384 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
385 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
386 !strconcat(instr_asm, "\t$dst, $src"),
387 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
390 class ByteSwap<bits<6> func, string instr_asm>:
391 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
392 !strconcat(instr_asm, "\t$dst, $src"),
393 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
396 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
397 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
398 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
402 class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
403 "rdhwr\t$dst, $src", [], IIAlu> {
409 class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
410 list<dag> pattern, InstrItinClass itin>:
411 FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
412 pattern, itin>, Requires<[IsMips32r2]> {
419 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
420 class Atomic2Ops<PatFrag Op, string Opstr> :
421 MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
422 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
424 (Op CPURegs:$ptr, CPURegs:$incr))]>;
426 // Atomic Compare & Swap.
427 class AtomicCmpSwap<PatFrag Op, string Width> :
428 MipsPseudo<(outs CPURegs:$dst),
429 (ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
430 !strconcat("atomic_cmp_swap_", Width,
431 "\t$dst, $ptr, $cmp, $swap"),
433 (Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
435 //===----------------------------------------------------------------------===//
436 // Pseudo instructions
437 //===----------------------------------------------------------------------===//
439 // As stack alignment is always done with addiu, we need a 16-bit immediate
440 let Defs = [SP], Uses = [SP] in {
441 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
442 "!ADJCALLSTACKDOWN $amt",
443 [(callseq_start timm:$amt)]>;
444 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
445 "!ADJCALLSTACKUP $amt1",
446 [(callseq_end timm:$amt1, timm:$amt2)]>;
449 // Some assembly macros need to avoid pseudoinstructions and assembler
450 // automatic reodering, we should reorder ourselves.
451 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
452 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
453 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
454 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
456 // These macros are inserted to prevent GAS from complaining
457 // when using the AT register.
458 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
459 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
461 // When handling PIC code the assembler needs .cpload and .cprestore
462 // directives. If the real instructions corresponding these directives
463 // are used, we have the same behavior, but get also a bunch of warnings
464 // from the assembler.
465 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
466 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
468 let usesCustomInserter = 1 in {
469 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, "load_add_8">;
470 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, "load_add_16">;
471 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, "load_add_32">;
472 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, "load_sub_8">;
473 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, "load_sub_16">;
474 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, "load_sub_32">;
475 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, "load_and_8">;
476 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, "load_and_16">;
477 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, "load_and_32">;
478 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, "load_or_8">;
479 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, "load_or_16">;
480 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, "load_or_32">;
481 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, "load_xor_8">;
482 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, "load_xor_16">;
483 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, "load_xor_32">;
484 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, "load_nand_8">;
485 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, "load_nand_16">;
486 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, "load_nand_32">;
488 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, "swap_8">;
489 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, "swap_16">;
490 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, "swap_32">;
492 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
493 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
494 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
497 // Unaligned loads and stores.
498 // Replaces LW or SW during MCInstLowering if memory access is unaligned.
500 MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulw\t$dst, $addr", []>;
502 MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulh\t$dst, $addr", []>;
504 MipsPseudo<(outs CPURegs:$dst), (ins mem:$addr), "ulhu\t$dst, $addr", []>;
506 MipsPseudo<(outs), (ins CPURegs:$dst, mem:$addr), "usw\t$dst, $addr", []>;
508 MipsPseudo<(outs), (ins CPURegs:$dst, mem:$addr), "ush\t$dst, $addr", []>;
510 //===----------------------------------------------------------------------===//
511 // Instruction definition
512 //===----------------------------------------------------------------------===//
514 //===----------------------------------------------------------------------===//
515 // MipsI Instructions
516 //===----------------------------------------------------------------------===//
518 /// Arithmetic Instructions (ALU Immediate)
519 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
520 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
521 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
522 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16>;
523 def ANDi : LogicI<0x0c, "andi", and>;
524 def ORi : LogicI<0x0d, "ori", or>;
525 def XORi : LogicI<0x0e, "xori", xor>;
526 def LUi : LoadUpper<0x0f, "lui">;
528 /// Arithmetic Instructions (3-Operand, R-Type)
529 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
530 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
531 def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
532 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
533 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
534 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
535 def AND : LogicR<0x24, "and", and>;
536 def OR : LogicR<0x25, "or", or>;
537 def XOR : LogicR<0x26, "xor", xor>;
538 def NOR : LogicNOR<0x00, 0x27, "nor">;
540 /// Shift Instructions
541 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
542 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
543 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
544 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
545 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
546 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
548 // Rotate Instructions
549 let Predicates = [IsMips32r2] in {
550 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
551 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
554 /// Load and Store Instructions
555 def LB : LoadM<0x20, "lb", sextloadi8>;
556 def LBu : LoadM<0x24, "lbu", zextloadi8>;
557 def LH : LoadM<0x21, "lh", sextloadi16>;
558 def LHu : LoadM<0x25, "lhu", zextloadi16>;
559 def LW : LoadM<0x23, "lw", load>;
560 def SB : StoreM<0x28, "sb", truncstorei8>;
561 def SH : StoreM<0x29, "sh", truncstorei16>;
562 def SW : StoreM<0x2b, "sw", store>;
564 let hasSideEffects = 1 in
565 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
566 [(MipsSync imm:$stype)], NoItinerary>
573 /// Load-linked, Store-conditional
575 def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
576 "ll\t$dst, $addr", [], IILoad>;
577 let mayStore = 1, Constraints = "$src = $dst" in
578 def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
579 "sc\t$src, $addr", [], IIStore>;
581 /// Jump and Branch Instructions
582 def J : JumpFJ<0x02, "j">;
583 let isIndirectBranch = 1 in
584 def JR : JumpFR<0x00, 0x08, "jr">;
585 def JAL : JumpLink<0x03, "jal">;
586 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
587 def BEQ : CBranch<0x04, "beq", seteq>;
588 def BNE : CBranch<0x05, "bne", setne>;
591 def BGEZ : CBranchZero<0x01, "bgez", setge>;
594 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
595 def BLEZ : CBranchZero<0x07, "blez", setle>;
596 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
599 def BGEZAL : BranchLink<"bgezal">;
600 def BLTZAL : BranchLink<"bltzal">;
602 let isReturn=1, isTerminator=1, hasDelaySlot=1,
603 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
604 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
605 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
607 /// Multiply and Divide Instructions.
608 def MULT : Mul<0x18, "mult", IIImul>;
609 def MULTu : Mul<0x19, "multu", IIImul>;
610 def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
611 def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
614 def MTHI : MoveToLOHI<0x11, "mthi">;
616 def MTLO : MoveToLOHI<0x13, "mtlo">;
619 def MFHI : MoveFromLOHI<0x10, "mfhi">;
621 def MFLO : MoveFromLOHI<0x12, "mflo">;
623 /// Sign Ext In Register Instructions.
624 let Predicates = [HasSEInReg] in {
625 let shamt = 0x10, rs = 0 in
626 def SEB : SignExtInReg<0x21, "seb", i8>;
628 let shamt = 0x18, rs = 0 in
629 def SEH : SignExtInReg<0x20, "seh", i16>;
633 def CLZ : CountLeading<0b100000, "clz",
634 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
635 def CLO : CountLeading<0b100001, "clo",
636 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
639 let Predicates = [HasSwap] in {
640 let shamt = 0x3, rs = 0 in
641 def WSBW : ByteSwap<0x20, "wsbw">;
645 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
646 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
648 // Conditional moves:
649 // These instructions are expanded in
650 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
651 // conditional move instructions.
652 // flag:int, data:int
653 let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
654 class CondMovIntInt<bits<6> funct, string instr_asm> :
655 FR<0, funct, (outs CPURegs:$dst),
656 (ins CPURegs:$T, CPURegs:$cond, CPURegs:$F),
657 !strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>;
659 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
660 def MOVN_I : CondMovIntInt<0x0b, "movn">;
664 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
666 // FrameIndexes are legalized when they are operands from load/store
667 // instructions. The same not happens for stack address copies, so an
668 // add op with mem ComplexPattern is used and the stack address copy
669 // can be matched. It's similar to Sparc LEA_ADDRi
670 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">;
672 // DynAlloc node points to dynamically allocated stack space.
673 // $sp is added to the list of implicitly used registers to prevent dead code
674 // elimination from removing instructions that modify $sp.
676 def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">;
679 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
680 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
681 def MSUB : MArithR<4, "msub", MipsMSub>;
682 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
684 // MUL is a assembly macro in the current used ISAs. In recent ISA's
685 // it is a real instruction.
686 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[IsMips32]>;
688 def RDHWR : ReadHardware;
690 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
691 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
693 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
696 let Constraints = "$src = $rt" in
697 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
698 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
700 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
704 //===----------------------------------------------------------------------===//
705 // Arbitrary patterns that map to one or more instructions
706 //===----------------------------------------------------------------------===//
709 def : Pat<(i32 immSExt16:$in),
710 (ADDiu ZERO, imm:$in)>;
711 def : Pat<(i32 immZExt16:$in),
712 (ORi ZERO, imm:$in)>;
714 // Arbitrary immediates
715 def : Pat<(i32 imm:$imm),
716 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
719 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
720 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
721 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
722 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
723 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
724 (ADDiu CPURegs:$src, imm:$imm)>;
727 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
728 (JAL tglobaladdr:$dst)>;
729 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
730 (JAL texternalsym:$dst)>;
731 //def : Pat<(MipsJmpLink CPURegs:$dst),
732 // (JALR CPURegs:$dst)>;
735 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
736 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
737 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
738 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
739 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
740 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
741 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
742 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
744 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
745 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
746 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
747 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
749 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
750 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
751 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
752 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
755 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
756 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
757 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
758 (ADDiu CPURegs:$gp, tconstpool:$in)>;
761 def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
762 (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
765 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
766 def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
767 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
768 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
771 class WrapperPICPat<SDNode node>:
772 Pat<(MipsWrapperPIC node:$in),
773 (ADDiu GP, node:$in)>;
775 def : WrapperPICPat<tglobaladdr>;
776 def : WrapperPICPat<tconstpool>;
777 def : WrapperPICPat<texternalsym>;
778 def : WrapperPICPat<tblockaddress>;
779 def : WrapperPICPat<tjumptable>;
781 // Mips does not have "not", so we expand our way
782 def : Pat<(not CPURegs:$in),
783 (NOR CPURegs:$in, ZERO)>;
785 // extended load and stores
786 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
787 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
788 def : Pat<(extloadi16 addr:$src), (LHu addr:$src)>;
791 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
794 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
795 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
796 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
797 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
799 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
800 (BEQ (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
801 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
802 (BEQ (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
803 def : Pat<(brcond (setge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
804 (BEQ (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
805 def : Pat<(brcond (setuge CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
806 (BEQ (SLTiu CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
808 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
809 (BEQ (SLT CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
810 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
811 (BEQ (SLTu CPURegs:$rhs, CPURegs:$lhs), ZERO, bb:$dst)>;
813 def : Pat<(brcond CPURegs:$cond, bb:$dst),
814 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
817 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
818 def : Pat<(select (setge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
819 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
820 def : Pat<(select (setuge CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
821 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
822 def : Pat<(select (setge CPURegs:$lhs, immSExt16:$rhs), RC:$T, RC:$F),
823 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
824 def : Pat<(select (setuge CPURegs:$lh, immSExt16:$rh), RC:$T, RC:$F),
825 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
826 def : Pat<(select (setle CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
827 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
828 def : Pat<(select (setule CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
829 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
830 def : Pat<(select (seteq CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
831 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
832 def : Pat<(select (seteq CPURegs:$lhs, 0), RC:$T, RC:$F),
833 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
836 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
837 def : Pat<(select (setne CPURegs:$lhs, CPURegs:$rhs), RC:$T, RC:$F),
838 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
839 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
840 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
841 def : Pat<(select (setne CPURegs:$lhs, 0), RC:$T, RC:$F),
842 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
845 defm : MovzPats<CPURegs, MOVZ_I>;
846 defm : MovnPats<CPURegs, MOVN_I>;
849 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
850 (SLTu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
851 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
852 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
854 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
855 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
856 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
857 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
859 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
860 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
861 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
862 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
864 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
865 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
866 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
867 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
869 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
870 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
871 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
872 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
874 // select MipsDynAlloc
875 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
877 //===----------------------------------------------------------------------===//
878 // Floating Point Support
879 //===----------------------------------------------------------------------===//
881 include "MipsInstrFPU.td"