1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">;
132 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
133 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
134 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
135 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
136 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
137 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
138 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
140 //===----------------------------------------------------------------------===//
141 // Mips Operand, Complex Patterns and Transformations Definitions.
142 //===----------------------------------------------------------------------===//
144 // Instruction operand types
145 def jmptarget : Operand<OtherVT> {
146 let EncoderMethod = "getJumpTargetOpValue";
148 def brtarget : Operand<OtherVT> {
149 let EncoderMethod = "getBranchTargetOpValue";
150 let OperandType = "OPERAND_PCREL";
152 def calltarget : Operand<iPTR> {
153 let EncoderMethod = "getJumpTargetOpValue";
155 def calltarget64: Operand<i64>;
156 def simm16 : Operand<i32>;
157 def simm16_64 : Operand<i64>;
158 def shamt : Operand<i32>;
161 def uimm16 : Operand<i32> {
162 let PrintMethod = "printUnsignedImm";
166 def mem : Operand<i32> {
167 let PrintMethod = "printMemOperand";
168 let MIOperandInfo = (ops CPURegs, simm16);
169 let EncoderMethod = "getMemEncoding";
172 def mem64 : Operand<i64> {
173 let PrintMethod = "printMemOperand";
174 let MIOperandInfo = (ops CPU64Regs, simm16_64);
177 def mem_ea : Operand<i32> {
178 let PrintMethod = "printMemOperandEA";
179 let MIOperandInfo = (ops CPURegs, simm16);
180 let EncoderMethod = "getMemEncoding";
183 def mem_ea_64 : Operand<i64> {
184 let PrintMethod = "printMemOperandEA";
185 let MIOperandInfo = (ops CPU64Regs, simm16_64);
186 let EncoderMethod = "getMemEncoding";
189 // size operand of ext instruction
190 def size_ext : Operand<i32> {
191 let EncoderMethod = "getSizeExtEncoding";
194 // size operand of ins instruction
195 def size_ins : Operand<i32> {
196 let EncoderMethod = "getSizeInsEncoding";
199 // Transformation Function - get the lower 16 bits.
200 def LO16 : SDNodeXForm<imm, [{
201 return getImm(N, N->getZExtValue() & 0xFFFF);
204 // Transformation Function - get the higher 16 bits.
205 def HI16 : SDNodeXForm<imm, [{
206 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
209 // Node immediate fits as 16-bit sign extended on target immediate.
211 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
213 // Node immediate fits as 16-bit zero extended on target immediate.
214 // The LO16 param means that only the lower 16 bits of the node
215 // immediate are caught.
217 def immZExt16 : PatLeaf<(imm), [{
218 if (N->getValueType(0) == MVT::i32)
219 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
221 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
224 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
225 def immLow16Zero : PatLeaf<(imm), [{
226 int64_t Val = N->getSExtValue();
227 return isInt<32>(Val) && !(Val & 0xffff);
230 // shamt field must fit in 5 bits.
231 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
233 // Mips Address Mode! SDNode frameindex could possibily be a match
234 // since load and store instructions from stack used it.
235 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
237 //===----------------------------------------------------------------------===//
238 // Pattern fragment for load/store
239 //===----------------------------------------------------------------------===//
240 class UnalignedLoad<PatFrag Node> :
241 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
242 LoadSDNode *LD = cast<LoadSDNode>(N);
243 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
246 class AlignedLoad<PatFrag Node> :
247 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
248 LoadSDNode *LD = cast<LoadSDNode>(N);
249 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
252 class UnalignedStore<PatFrag Node> :
253 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
254 StoreSDNode *SD = cast<StoreSDNode>(N);
255 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
258 class AlignedStore<PatFrag Node> :
259 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
260 StoreSDNode *SD = cast<StoreSDNode>(N);
261 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
264 // Load/Store PatFrags.
265 def sextloadi16_a : AlignedLoad<sextloadi16>;
266 def zextloadi16_a : AlignedLoad<zextloadi16>;
267 def extloadi16_a : AlignedLoad<extloadi16>;
268 def load_a : AlignedLoad<load>;
269 def sextloadi32_a : AlignedLoad<sextloadi32>;
270 def zextloadi32_a : AlignedLoad<zextloadi32>;
271 def extloadi32_a : AlignedLoad<extloadi32>;
272 def truncstorei16_a : AlignedStore<truncstorei16>;
273 def store_a : AlignedStore<store>;
274 def truncstorei32_a : AlignedStore<truncstorei32>;
275 def sextloadi16_u : UnalignedLoad<sextloadi16>;
276 def zextloadi16_u : UnalignedLoad<zextloadi16>;
277 def extloadi16_u : UnalignedLoad<extloadi16>;
278 def load_u : UnalignedLoad<load>;
279 def sextloadi32_u : UnalignedLoad<sextloadi32>;
280 def zextloadi32_u : UnalignedLoad<zextloadi32>;
281 def extloadi32_u : UnalignedLoad<extloadi32>;
282 def truncstorei16_u : UnalignedStore<truncstorei16>;
283 def store_u : UnalignedStore<store>;
284 def truncstorei32_u : UnalignedStore<truncstorei32>;
286 //===----------------------------------------------------------------------===//
287 // Instructions specific format
288 //===----------------------------------------------------------------------===//
290 // Arithmetic and logical instructions with 3 register operands.
291 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
292 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
293 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
294 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
295 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
297 let isCommutable = isComm;
300 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
301 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
302 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
303 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
305 let isCommutable = isComm;
308 // Arithmetic and logical instructions with 2 register operands.
309 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
310 Operand Od, PatLeaf imm_type, RegisterClass RC> :
311 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
312 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
313 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu>;
315 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
316 Operand Od, PatLeaf imm_type, RegisterClass RC> :
317 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
318 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
320 // Arithmetic Multiply ADD/SUB
321 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
322 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
323 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
324 !strconcat(instr_asm, "\t$rs, $rt"),
325 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
328 let isCommutable = isComm;
332 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
333 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
334 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
335 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
337 let isCommutable = 1;
341 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
342 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
344 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
345 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
346 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
350 // 32-bit shift instructions.
351 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
353 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
355 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
356 SDNode OpNode, RegisterClass RC>:
357 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
358 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
359 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
360 let shamt = isRotate;
363 // Load Upper Imediate
364 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
365 FI<op, (outs RC:$rt), (ins Imm:$imm16),
366 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
370 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
371 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
373 let Inst{25-21} = addr{20-16};
374 let Inst{15-0} = addr{15-0};
378 let canFoldAsLoad = 1 in
379 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
380 Operand MemOpnd, bit Pseudo>:
381 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
382 !strconcat(instr_asm, "\t$rt, $addr"),
383 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
384 let isPseudo = Pseudo;
387 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
388 Operand MemOpnd, bit Pseudo>:
389 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
390 !strconcat(instr_asm, "\t$rt, $addr"),
391 [(OpNode RC:$rt, addr:$addr)], IIStore> {
392 let isPseudo = Pseudo;
395 // Unaligned Memory Load/Store
396 let canFoldAsLoad = 1 in
397 class LoadUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
398 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), "", [], IILoad> {}
400 class StoreUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
401 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), "", [], IIStore> {}
404 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
406 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
408 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
413 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
415 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
417 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
422 multiclass LoadUnAlign32<bits<6> op> {
423 def #NAME# : LoadUnAlign<op, CPURegs, mem>,
425 def _P8 : LoadUnAlign<op, CPURegs, mem64>,
429 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
431 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
433 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
438 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
440 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
442 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
447 multiclass StoreUnAlign32<bits<6> op> {
448 def #NAME# : StoreUnAlign<op, CPURegs, mem>,
450 def _P8 : StoreUnAlign<op, CPURegs, mem64>,
454 // Conditional Branch
455 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
456 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
457 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
458 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
460 let isTerminator = 1;
461 let hasDelaySlot = 1;
464 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
466 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
467 !strconcat(instr_asm, "\t$rs, $imm16"),
468 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
471 let isTerminator = 1;
472 let hasDelaySlot = 1;
476 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
478 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
479 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
480 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
485 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
486 PatLeaf imm_type, RegisterClass RC>:
487 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
488 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
489 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
493 class JumpFJ<bits<6> op, string instr_asm>:
494 FJ<op, (outs), (ins jmptarget:$target),
495 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
499 let hasDelaySlot = 1;
500 let Predicates = [RelocStatic];
503 // Unconditional branch
504 class UncondBranch<bits<6> op, string instr_asm>:
505 BranchBase<op, (outs), (ins brtarget:$imm16),
506 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
510 let isTerminator = 1;
512 let hasDelaySlot = 1;
513 let Predicates = [RelocPIC];
516 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
517 isIndirectBranch = 1 in
518 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
519 FR<op, func, (outs), (ins RC:$rs),
520 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
526 // Jump and Link (Call)
527 let isCall=1, hasDelaySlot=1 in {
528 class JumpLink<bits<6> op, string instr_asm>:
529 FJ<op, (outs), (ins calltarget:$target, variable_ops),
530 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
533 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
535 FR<op, func, (outs), (ins RC:$rs, variable_ops),
536 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
542 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
543 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
544 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
550 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
551 RegisterClass RC, list<Register> DefRegs>:
552 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
553 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
556 let isCommutable = 1;
560 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
561 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
563 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
564 RegisterClass RC, list<Register> DefRegs>:
565 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
566 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
567 [(op RC:$rs, RC:$rt)], itin> {
573 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
574 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
577 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
578 list<Register> UseRegs>:
579 FR<0x00, func, (outs RC:$rd), (ins),
580 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
587 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
588 list<Register> DefRegs>:
589 FR<0x00, func, (outs), (ins RC:$rs),
590 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
597 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
598 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
599 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
601 // Count Leading Ones/Zeros in Word
602 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
603 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
604 !strconcat(instr_asm, "\t$rd, $rs"),
605 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
606 Requires<[HasBitCount]> {
611 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
612 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
613 !strconcat(instr_asm, "\t$rd, $rs"),
614 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
615 Requires<[HasBitCount]> {
620 // Sign Extend in Register.
621 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
623 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
624 !strconcat(instr_asm, "\t$rd, $rt"),
625 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
628 let Predicates = [HasSEInReg];
632 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
633 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
634 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
637 let Predicates = [HasSwap];
641 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
642 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
643 "rdhwr\t$rt, $rd", [], IIAlu> {
649 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
650 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
651 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
652 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
657 let Predicates = [HasMips32r2];
660 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
661 FR<0x1f, _funct, (outs RC:$rt),
662 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
663 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
664 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
670 let Predicates = [HasMips32r2];
671 let Constraints = "$src = $rt";
674 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
675 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
677 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
678 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
679 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
681 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
682 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>, Requires<[NotN64]>;
683 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>, Requires<[IsN64]>;
686 // Atomic Compare & Swap.
687 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
689 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
690 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
691 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
693 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
694 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>, Requires<[NotN64]>;
695 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>, Requires<[IsN64]>;
698 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
699 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
700 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
704 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
705 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
706 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
708 let Constraints = "$rt = $dst";
711 //===----------------------------------------------------------------------===//
712 // Pseudo instructions
713 //===----------------------------------------------------------------------===//
715 // As stack alignment is always done with addiu, we need a 16-bit immediate
716 let Defs = [SP], Uses = [SP] in {
717 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
718 "!ADJCALLSTACKDOWN $amt",
719 [(callseq_start timm:$amt)]>;
720 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
721 "!ADJCALLSTACKUP $amt1",
722 [(callseq_end timm:$amt1, timm:$amt2)]>;
725 // Some assembly macros need to avoid pseudoinstructions and assembler
726 // automatic reodering, we should reorder ourselves.
727 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
728 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
729 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
730 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
732 // These macros are inserted to prevent GAS from complaining
733 // when using the AT register.
734 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
735 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
737 // When handling PIC code the assembler needs .cpload and .cprestore
738 // directives. If the real instructions corresponding these directives
739 // are used, we have the same behavior, but get also a bunch of warnings
740 // from the assembler.
741 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
742 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
744 // For O32 ABI & PIC & non-fixed global base register, the following instruction
745 // seqeunce is emitted to set the global base register:
747 // 0. lui $2, %hi(_gp_disp)
748 // 1. addiu $2, $2, %lo(_gp_disp)
749 // 2. addu $globalbasereg, $2, $t9
751 // SETGP01 is emitted during Prologue/Epilogue insertion and then converted to
752 // instructions 0 and 1 in the sequence above during MC lowering.
753 // SETGP2 is emitted just before register allocation and converted to
754 // instruction 2 just prior to post-RA scheduling.
756 // These pseudo instructions are needed to ensure no instructions are inserted
757 // before or between instructions 0 and 1, which is a limitation imposed by
760 def SETGP01 : MipsPseudo<(outs CPURegs:$dst), (ins), "", []>;
761 def SETGP2 : MipsPseudo<(outs CPURegs:$globalreg), (ins CPURegs:$picreg), "",
764 let usesCustomInserter = 1 in {
765 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
766 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
767 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
768 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
769 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
770 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
771 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
772 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
773 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
774 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
775 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
776 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
777 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
778 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
779 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
780 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
781 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
782 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
784 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
785 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
786 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
788 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
789 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
790 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
793 //===----------------------------------------------------------------------===//
794 // Instruction definition
795 //===----------------------------------------------------------------------===//
797 //===----------------------------------------------------------------------===//
798 // MipsI Instructions
799 //===----------------------------------------------------------------------===//
801 /// Arithmetic Instructions (ALU Immediate)
802 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
803 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
804 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
805 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
806 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
807 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
808 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
809 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
811 /// Arithmetic Instructions (3-Operand, R-Type)
812 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
813 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
814 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
815 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
816 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
817 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
818 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
819 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
820 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
821 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
823 /// Shift Instructions
824 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
825 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
826 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
827 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
828 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
829 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
831 // Rotate Instructions
832 let Predicates = [HasMips32r2] in {
833 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
834 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
837 /// Load and Store Instructions
839 defm LB : LoadM32<0x20, "lb", sextloadi8>;
840 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
841 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
842 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
843 defm LW : LoadM32<0x23, "lw", load_a>;
844 defm SB : StoreM32<0x28, "sb", truncstorei8>;
845 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
846 defm SW : StoreM32<0x2b, "sw", store_a>;
849 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
850 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
851 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
852 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
853 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
855 /// Primitives for unaligned
856 defm LWL : LoadUnAlign32<0x22>;
857 defm LWR : LoadUnAlign32<0x26>;
858 defm SWL : StoreUnAlign32<0x2A>;
859 defm SWR : StoreUnAlign32<0x2E>;
861 let hasSideEffects = 1 in
862 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
863 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
868 let Inst{10-6} = stype;
872 /// Load-linked, Store-conditional
873 def LL : LLBase<0x30, "ll", CPURegs, mem>, Requires<[NotN64]>;
874 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>, Requires<[IsN64]>;
875 def SC : SCBase<0x38, "sc", CPURegs, mem>, Requires<[NotN64]>;
876 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>, Requires<[IsN64]>;
878 /// Jump and Branch Instructions
879 def J : JumpFJ<0x02, "j">;
880 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
881 def B : UncondBranch<0x04, "b">;
882 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
883 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
884 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
885 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
886 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
887 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
889 // All calls clobber the non-callee saved registers...
890 let Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
891 K0, K1, GP, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9] in {
892 def JAL : JumpLink<0x03, "jal">;
893 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
894 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
895 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
898 let isReturn=1, isTerminator=1, hasDelaySlot=1,
899 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
900 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
901 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
903 /// Multiply and Divide Instructions.
904 def MULT : Mult32<0x18, "mult", IIImul>;
905 def MULTu : Mult32<0x19, "multu", IIImul>;
906 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
907 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
909 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
910 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
911 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
912 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
914 /// Sign Ext In Register Instructions.
915 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
916 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
919 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
920 def CLO : CountLeading1<0x21, "clo", CPURegs>;
922 /// Word Swap Bytes Within Halfwords
923 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
927 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
929 // FrameIndexes are legalized when they are operands from load/store
930 // instructions. The same not happens for stack address copies, so an
931 // add op with mem ComplexPattern is used and the stack address copy
932 // can be matched. It's similar to Sparc LEA_ADDRi
933 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
935 // DynAlloc node points to dynamically allocated stack space.
936 // $sp is added to the list of implicitly used registers to prevent dead code
937 // elimination from removing instructions that modify $sp.
939 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea>;
942 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
943 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
944 def MSUB : MArithR<4, "msub", MipsMSub>;
945 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
947 // MUL is a assembly macro in the current used ISAs. In recent ISA's
948 // it is a real instruction.
949 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
950 Requires<[HasMips32]>;
952 def RDHWR : ReadHardware<CPURegs, HWRegs>;
954 def EXT : ExtBase<0, "ext", CPURegs>;
955 def INS : InsBase<4, "ins", CPURegs>;
957 //===----------------------------------------------------------------------===//
958 // Arbitrary patterns that map to one or more instructions
959 //===----------------------------------------------------------------------===//
962 def : Pat<(i32 immSExt16:$in),
963 (ADDiu ZERO, imm:$in)>;
964 def : Pat<(i32 immZExt16:$in),
965 (ORi ZERO, imm:$in)>;
966 def : Pat<(i32 immLow16Zero:$in),
967 (LUi (HI16 imm:$in))>;
969 // Arbitrary immediates
970 def : Pat<(i32 imm:$imm),
971 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
974 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
975 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
976 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
977 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
978 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
979 (ADDiu CPURegs:$src, imm:$imm)>;
982 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
983 (JAL tglobaladdr:$dst)>;
984 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
985 (JAL texternalsym:$dst)>;
986 //def : Pat<(MipsJmpLink CPURegs:$dst),
987 // (JALR CPURegs:$dst)>;
990 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
991 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
992 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
993 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
994 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
996 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
997 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
998 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
999 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1000 def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1002 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1003 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1004 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1005 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1006 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1007 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1008 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1009 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1010 def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1011 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1014 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1015 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1016 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1017 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1020 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1021 Pat<(MipsWrapper RC:$gp, node:$in),
1022 (ADDiuOp RC:$gp, node:$in)>;
1024 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1025 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1026 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1027 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1028 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1029 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1031 // Mips does not have "not", so we expand our way
1032 def : Pat<(not CPURegs:$in),
1033 (NOR CPURegs:$in, ZERO)>;
1036 let Predicates = [NotN64] in {
1037 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1038 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1039 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1040 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1042 let Predicates = [IsN64] in {
1043 def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1044 def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1045 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1046 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1050 let Predicates = [NotN64] in {
1051 def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1052 def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1054 let Predicates = [IsN64] in {
1055 def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1056 def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1060 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1061 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1062 Instruction SLTiuOp, Register ZEROReg> {
1063 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1064 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1065 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1066 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1068 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1069 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1070 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1071 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1072 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1073 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1074 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1075 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1077 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1078 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1079 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1080 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1082 def : Pat<(brcond RC:$cond, bb:$dst),
1083 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1086 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1089 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1090 Instruction SLTuOp, Register ZEROReg> {
1091 def : Pat<(seteq RC:$lhs, RC:$rhs),
1092 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1093 def : Pat<(setne RC:$lhs, RC:$rhs),
1094 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1097 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1098 def : Pat<(setle RC:$lhs, RC:$rhs),
1099 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1100 def : Pat<(setule RC:$lhs, RC:$rhs),
1101 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1104 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1105 def : Pat<(setgt RC:$lhs, RC:$rhs),
1106 (SLTOp RC:$rhs, RC:$lhs)>;
1107 def : Pat<(setugt RC:$lhs, RC:$rhs),
1108 (SLTuOp RC:$rhs, RC:$lhs)>;
1111 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1112 def : Pat<(setge RC:$lhs, RC:$rhs),
1113 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1114 def : Pat<(setuge RC:$lhs, RC:$rhs),
1115 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1118 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1119 Instruction SLTiuOp> {
1120 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1121 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1122 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1123 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1126 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1127 defm : SetlePats<CPURegs, SLT, SLTu>;
1128 defm : SetgtPats<CPURegs, SLT, SLTu>;
1129 defm : SetgePats<CPURegs, SLT, SLTu>;
1130 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1132 // select MipsDynAlloc
1133 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1136 def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1138 //===----------------------------------------------------------------------===//
1139 // Floating Point Support
1140 //===----------------------------------------------------------------------===//
1142 include "MipsInstrFPU.td"
1143 include "Mips64InstrInfo.td"
1144 include "MipsCondMov.td"