1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
172 AssemblerPredicate<"FeatureMips16">;
173 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
174 AssemblerPredicate<"FeatureMips32">;
175 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
176 AssemblerPredicate<"FeatureMips32">;
177 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
178 AssemblerPredicate<"FeatureMips32">;
179 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
180 AssemblerPredicate<"!FeatureMips16">;
181 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
182 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
183 AssemblerPredicate<"FeatureMicroMips">;
184 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"!FeatureMicroMips">;
186 def IsLE : Predicate<"Subtarget.isLittle()">;
187 def IsBE : Predicate<"!Subtarget.isLittle()">;
188 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
190 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
191 let Predicates = [HasStdEnc];
195 bit isCommutable = 1;
212 bit isTerminator = 1;
215 bit hasExtraSrcRegAllocReq = 1;
216 bit isCodeGenOnly = 1;
219 class IsAsCheapAsAMove {
220 bit isAsCheapAsAMove = 1;
223 class NeverHasSideEffects {
224 bit neverHasSideEffects = 1;
227 //===----------------------------------------------------------------------===//
228 // Instruction format superclass
229 //===----------------------------------------------------------------------===//
231 include "MipsInstrFormats.td"
233 //===----------------------------------------------------------------------===//
234 // Mips Operand, Complex Patterns and Transformations Definitions.
235 //===----------------------------------------------------------------------===//
237 // Instruction operand types
238 def jmptarget : Operand<OtherVT> {
239 let EncoderMethod = "getJumpTargetOpValue";
241 def brtarget : Operand<OtherVT> {
242 let EncoderMethod = "getBranchTargetOpValue";
243 let OperandType = "OPERAND_PCREL";
244 let DecoderMethod = "DecodeBranchTarget";
246 def calltarget : Operand<iPTR> {
247 let EncoderMethod = "getJumpTargetOpValue";
250 def simm10 : Operand<i32>;
252 def simm16 : Operand<i32> {
253 let DecoderMethod= "DecodeSimm16";
256 def simm20 : Operand<i32> {
259 def uimm20 : Operand<i32> {
262 def uimm10 : Operand<i32> {
265 def simm16_64 : Operand<i64> {
266 let DecoderMethod = "DecodeSimm16";
270 def uimm5 : Operand<i32> {
271 let PrintMethod = "printUnsignedImm";
274 def uimm6 : Operand<i32> {
275 let PrintMethod = "printUnsignedImm";
278 def uimm16 : Operand<i32> {
279 let PrintMethod = "printUnsignedImm";
282 def pcrel16 : Operand<i32> {
285 def MipsMemAsmOperand : AsmOperandClass {
287 let ParserMethod = "parseMemOperand";
290 def MipsInvertedImmoperand : AsmOperandClass {
292 let RenderMethod = "addImmOperands";
293 let ParserMethod = "parseInvNum";
296 def PtrRegAsmOperand : AsmOperandClass {
298 let ParserMethod = "parsePtrReg";
302 def InvertedImOperand : Operand<i32> {
303 let ParserMatchClass = MipsInvertedImmoperand;
306 class mem_generic : Operand<iPTR> {
307 let PrintMethod = "printMemOperand";
308 let MIOperandInfo = (ops ptr_rc, simm16);
309 let EncoderMethod = "getMemEncoding";
310 let ParserMatchClass = MipsMemAsmOperand;
311 let OperandType = "OPERAND_MEMORY";
315 def mem : mem_generic;
317 // MSA specific address operand
318 def mem_msa : mem_generic {
319 let MIOperandInfo = (ops ptr_rc, simm10);
320 let EncoderMethod = "getMSAMemEncoding";
323 def mem_ea : Operand<iPTR> {
324 let PrintMethod = "printMemOperandEA";
325 let MIOperandInfo = (ops ptr_rc, simm16);
326 let EncoderMethod = "getMemEncoding";
327 let OperandType = "OPERAND_MEMORY";
330 def PtrRC : Operand<iPTR> {
331 let MIOperandInfo = (ops ptr_rc);
332 let DecoderMethod = "DecodePtrRegisterClass";
333 let ParserMatchClass = PtrRegAsmOperand;
336 // size operand of ext instruction
337 def size_ext : Operand<i32> {
338 let EncoderMethod = "getSizeExtEncoding";
339 let DecoderMethod = "DecodeExtSize";
342 // size operand of ins instruction
343 def size_ins : Operand<i32> {
344 let EncoderMethod = "getSizeInsEncoding";
345 let DecoderMethod = "DecodeInsSize";
348 // Transformation Function - get the lower 16 bits.
349 def LO16 : SDNodeXForm<imm, [{
350 return getImm(N, N->getZExtValue() & 0xFFFF);
353 // Transformation Function - get the higher 16 bits.
354 def HI16 : SDNodeXForm<imm, [{
355 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
359 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
361 // Node immediate fits as 16-bit sign extended on target immediate.
363 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
365 // Node immediate fits as 16-bit sign extended on target immediate.
367 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
369 // Node immediate fits as 15-bit sign extended on target immediate.
371 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
373 // Node immediate fits as 16-bit zero extended on target immediate.
374 // The LO16 param means that only the lower 16 bits of the node
375 // immediate are caught.
377 def immZExt16 : PatLeaf<(imm), [{
378 if (N->getValueType(0) == MVT::i32)
379 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
381 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
384 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
385 def immLow16Zero : PatLeaf<(imm), [{
386 int64_t Val = N->getSExtValue();
387 return isInt<32>(Val) && !(Val & 0xffff);
390 // shamt field must fit in 5 bits.
391 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
393 // True if (N + 1) fits in 16-bit field.
394 def immSExt16Plus1 : PatLeaf<(imm), [{
395 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
398 // Mips Address Mode! SDNode frameindex could possibily be a match
399 // since load and store instructions from stack used it.
401 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
404 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
407 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
410 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
412 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
414 //===----------------------------------------------------------------------===//
415 // Instructions specific format
416 //===----------------------------------------------------------------------===//
418 // Arithmetic and logical instructions with 3 register operands.
419 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
420 InstrItinClass Itin = NoItinerary,
421 SDPatternOperator OpNode = null_frag>:
422 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
423 !strconcat(opstr, "\t$rd, $rs, $rt"),
424 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
425 let isCommutable = isComm;
426 let isReMaterializable = 1;
429 // Arithmetic and logical instructions with 2 register operands.
430 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
431 InstrItinClass Itin = NoItinerary,
432 SDPatternOperator imm_type = null_frag,
433 SDPatternOperator OpNode = null_frag> :
434 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
435 !strconcat(opstr, "\t$rt, $rs, $imm16"),
436 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
438 let isReMaterializable = 1;
439 let TwoOperandAliasConstraint = "$rs = $rt";
442 // Arithmetic Multiply ADD/SUB
443 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
444 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
445 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
446 let Defs = [HI0, LO0];
447 let Uses = [HI0, LO0];
448 let isCommutable = isComm;
452 class LogicNOR<string opstr, RegisterOperand RO>:
453 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
454 !strconcat(opstr, "\t$rd, $rs, $rt"),
455 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
456 let isCommutable = 1;
460 class shift_rotate_imm<string opstr, Operand ImmOpnd,
461 RegisterOperand RO, InstrItinClass itin,
462 SDPatternOperator OpNode = null_frag,
463 SDPatternOperator PF = null_frag> :
464 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
465 !strconcat(opstr, "\t$rd, $rt, $shamt"),
466 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
468 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
469 SDPatternOperator OpNode = null_frag>:
470 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
471 !strconcat(opstr, "\t$rd, $rt, $rs"),
472 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
475 // Load Upper Imediate
476 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
477 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
478 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
479 let neverHasSideEffects = 1;
480 let isReMaterializable = 1;
484 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
485 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
486 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
487 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
488 let DecoderMethod = "DecodeMem";
489 let canFoldAsLoad = 1;
493 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
494 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
495 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
496 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
497 let DecoderMethod = "DecodeMem";
501 // Load/Store Left/Right
502 let canFoldAsLoad = 1 in
503 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
504 InstrItinClass Itin> :
505 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
506 !strconcat(opstr, "\t$rt, $addr"),
507 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
508 let DecoderMethod = "DecodeMem";
509 string Constraints = "$src = $rt";
512 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
513 InstrItinClass Itin> :
514 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
515 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
516 let DecoderMethod = "DecodeMem";
519 // Conditional Branch
520 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
521 RegisterOperand RO> :
522 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
523 !strconcat(opstr, "\t$rs, $rt, $offset"),
524 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
527 let isTerminator = 1;
528 let hasDelaySlot = 1;
532 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
533 RegisterOperand RO> :
534 InstSE<(outs), (ins RO:$rs, opnd:$offset),
535 !strconcat(opstr, "\t$rs, $offset"),
536 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
539 let isTerminator = 1;
540 let hasDelaySlot = 1;
545 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
546 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
547 !strconcat(opstr, "\t$rd, $rs, $rt"),
548 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
549 II_SLT_SLTU, FrmR, opstr>;
551 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
553 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
554 !strconcat(opstr, "\t$rt, $rs, $imm16"),
555 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
556 II_SLTI_SLTIU, FrmI, opstr>;
559 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
560 SDPatternOperator targetoperator, string bopstr> :
561 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
562 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
565 let hasDelaySlot = 1;
566 let DecoderMethod = "DecodeJumpTarget";
570 // Unconditional branch
571 class UncondBranch<Instruction BEQInst> :
572 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
573 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
575 let isTerminator = 1;
577 let hasDelaySlot = 1;
578 let Predicates = [RelocPIC, HasStdEnc];
582 // Base class for indirect branch and return instruction classes.
583 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
584 class JumpFR<string opstr, RegisterOperand RO,
585 SDPatternOperator operator = null_frag>:
586 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
590 class IndirectBranch<string opstr, RegisterOperand RO> :
591 JumpFR<opstr, RO, brind> {
593 let isIndirectBranch = 1;
596 // Return instruction
597 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
599 let isCodeGenOnly = 1;
601 let hasExtraSrcRegAllocReq = 1;
604 // Jump and Link (Call)
605 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
606 class JumpLink<string opstr, DAGOperand opnd> :
607 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
608 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
609 let DecoderMethod = "DecodeJumpTarget";
612 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
613 Register RetReg, RegisterOperand ResRO = RO>:
614 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
615 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
617 class JumpLinkReg<string opstr, RegisterOperand RO>:
618 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
619 [], IIBranch, FrmR, opstr>;
621 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
622 InstSE<(outs), (ins RO:$rs, opnd:$offset),
623 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
627 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
628 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
629 class TailCall<Instruction JumpInst> :
630 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
631 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
633 class TailCallReg<RegisterOperand RO, Instruction JRInst,
634 RegisterOperand ResRO = RO> :
635 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
636 PseudoInstExpansion<(JRInst ResRO:$rs)>;
639 class BAL_BR_Pseudo<Instruction RealInst> :
640 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
641 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
643 let isTerminator = 1;
645 let hasDelaySlot = 1;
650 class SYS_FT<string opstr> :
651 InstSE<(outs), (ins uimm20:$code_),
652 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
654 class BRK_FT<string opstr> :
655 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
656 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
660 class ER_FT<string opstr> :
661 InstSE<(outs), (ins),
662 opstr, [], NoItinerary, FrmOther, opstr>;
665 class DEI_FT<string opstr, RegisterOperand RO> :
666 InstSE<(outs RO:$rt), (ins),
667 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
670 class WAIT_FT<string opstr> :
671 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
674 let hasSideEffects = 1 in
675 class SYNC_FT<string opstr> :
676 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
677 NoItinerary, FrmOther, opstr>;
679 let hasSideEffects = 1 in
680 class TEQ_FT<string opstr, RegisterOperand RO> :
681 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
682 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
685 class TEQI_FT<string opstr, RegisterOperand RO> :
686 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
687 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
689 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
690 list<Register> DefRegs> :
691 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
693 let isCommutable = 1;
695 let neverHasSideEffects = 1;
698 // Pseudo multiply/divide instruction with explicit accumulator register
700 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
701 SDPatternOperator OpNode, InstrItinClass Itin,
702 bit IsComm = 1, bit HasSideEffects = 0,
703 bit UsesCustomInserter = 0> :
704 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
705 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
706 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
707 let isCommutable = IsComm;
708 let hasSideEffects = HasSideEffects;
709 let usesCustomInserter = UsesCustomInserter;
712 // Pseudo multiply add/sub instruction with explicit accumulator register
714 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
716 : PseudoSE<(outs ACC64:$ac),
717 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
719 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
721 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
722 string Constraints = "$acin = $ac";
725 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
726 list<Register> DefRegs> :
727 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
728 [], itin, FrmR, opstr> {
733 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
734 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
735 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
737 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
738 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
741 let neverHasSideEffects = 1;
744 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
745 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
746 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
749 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
750 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
753 let neverHasSideEffects = 1;
756 class EffectiveAddress<string opstr, RegisterOperand RO> :
757 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
758 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
759 !strconcat(opstr, "_lea")> {
760 let isCodeGenOnly = 1;
761 let DecoderMethod = "DecodeMem";
764 // Count Leading Ones/Zeros in Word
765 class CountLeading0<string opstr, RegisterOperand RO>:
766 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
767 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
768 Requires<[HasBitCount, HasStdEnc]>;
770 class CountLeading1<string opstr, RegisterOperand RO>:
771 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
772 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
773 Requires<[HasBitCount, HasStdEnc]>;
776 // Sign Extend in Register.
777 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
778 InstrItinClass itin> :
779 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
780 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
781 let Predicates = [HasSEInReg, HasStdEnc];
785 class SubwordSwap<string opstr, RegisterOperand RO>:
786 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
787 NoItinerary, FrmR, opstr> {
788 let Predicates = [HasSwap, HasStdEnc];
789 let neverHasSideEffects = 1;
793 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
794 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
798 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
799 SDPatternOperator Op = null_frag>:
800 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
801 !strconcat(opstr, " $rt, $rs, $pos, $size"),
802 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
804 let Predicates = [HasMips32r2, HasStdEnc];
807 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
808 SDPatternOperator Op = null_frag>:
809 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
810 !strconcat(opstr, " $rt, $rs, $pos, $size"),
811 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
812 NoItinerary, FrmR, opstr> {
813 let Predicates = [HasMips32r2, HasStdEnc];
814 let Constraints = "$src = $rt";
817 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
818 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
819 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
820 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
822 // Atomic Compare & Swap.
823 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
824 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
825 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
827 class LLBase<string opstr, RegisterOperand RO> :
828 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
829 [], NoItinerary, FrmI> {
830 let DecoderMethod = "DecodeMem";
834 class SCBase<string opstr, RegisterOperand RO> :
835 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
836 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
837 let DecoderMethod = "DecodeMem";
839 let Constraints = "$rt = $dst";
842 class MFC3OP<string asmstr, RegisterOperand RO> :
843 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
844 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
846 class TrapBase<Instruction RealInst>
847 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
848 PseudoInstExpansion<(RealInst 0, 0)> {
850 let isTerminator = 1;
851 let isCodeGenOnly = 1;
854 //===----------------------------------------------------------------------===//
855 // Pseudo instructions
856 //===----------------------------------------------------------------------===//
859 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
860 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
862 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
863 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
864 [(callseq_start timm:$amt)]>;
865 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
866 [(callseq_end timm:$amt1, timm:$amt2)]>;
869 let usesCustomInserter = 1 in {
870 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
871 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
872 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
873 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
874 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
875 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
876 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
877 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
878 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
879 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
880 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
881 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
882 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
883 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
884 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
885 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
886 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
887 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
889 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
890 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
891 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
893 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
894 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
895 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
898 /// Pseudo instructions for loading and storing accumulator registers.
899 let isPseudo = 1, isCodeGenOnly = 1 in {
900 def LOAD_ACC64 : Load<"", ACC64>;
901 def STORE_ACC64 : Store<"", ACC64>;
904 //===----------------------------------------------------------------------===//
905 // Instruction definition
906 //===----------------------------------------------------------------------===//
907 //===----------------------------------------------------------------------===//
908 // MipsI Instructions
909 //===----------------------------------------------------------------------===//
911 /// Arithmetic Instructions (ALU Immediate)
912 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
914 ADDI_FM<0x9>, IsAsCheapAsAMove;
915 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
916 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
918 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
920 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
923 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
926 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
929 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
931 /// Arithmetic Instructions (3-Operand, R-Type)
932 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
934 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
936 let Defs = [HI0, LO0] in
937 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
939 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
940 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
941 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
942 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
943 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
945 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
947 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
949 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
951 /// Shift Instructions
952 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
953 immZExt5>, SRA_FM<0, 0>;
954 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
955 immZExt5>, SRA_FM<2, 0>;
956 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
957 immZExt5>, SRA_FM<3, 0>;
958 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
960 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
962 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
965 // Rotate Instructions
966 let Predicates = [HasMips32r2, HasStdEnc] in {
967 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
968 immZExt5>, SRA_FM<2, 1>;
969 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
973 /// Load and Store Instructions
975 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
976 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
978 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
980 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
981 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
983 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
984 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
985 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
987 /// load/store left/right
988 let Predicates = [NotInMicroMips] in {
989 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
990 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
991 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
992 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
995 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
996 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
997 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
998 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
999 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1000 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1001 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1003 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1004 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1005 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1006 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1007 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1008 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1010 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1011 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1012 def TRAP : TrapBase<BREAK>;
1014 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1015 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1017 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1018 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1020 def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM;
1022 /// Load-linked, Store-conditional
1023 let Predicates = [NotInMicroMips] in {
1024 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1025 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1028 /// Jump and Branch Instructions
1029 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1030 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1031 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1032 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1033 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1034 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1036 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1038 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1040 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1042 def B : UncondBranch<BEQ>;
1044 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1045 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1046 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1047 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1048 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1049 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1050 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1051 def TAILCALL : TailCall<J>;
1052 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1054 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1056 // Exception handling related node and instructions.
1057 // The conversion sequence is:
1058 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1059 // MIPSeh_return -> (stack change + indirect branch)
1061 // MIPSeh_return takes the place of regular return instruction
1062 // but takes two arguments (V1, V0) which are used for storing
1063 // the offset and return address respectively.
1064 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1066 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1067 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1069 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1070 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1071 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1072 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1074 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1077 /// Multiply and Divide Instructions.
1078 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1080 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1082 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1084 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1087 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1088 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1089 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1090 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1092 /// Sign Ext In Register Instructions.
1093 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1094 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1097 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1098 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1100 /// Word Swap Bytes Within Halfwords
1101 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1104 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1106 // FrameIndexes are legalized when they are operands from load/store
1107 // instructions. The same not happens for stack address copies, so an
1108 // add op with mem ComplexPattern is used and the stack address copy
1109 // can be matched. It's similar to Sparc LEA_ADDRi
1110 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1113 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1114 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1115 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1116 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1118 let Predicates = [HasStdEnc, NotDSP] in {
1119 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1120 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1121 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1122 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1123 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1124 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1125 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1126 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1127 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1130 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1132 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1135 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1137 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1138 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1140 /// Move Control Registers From/To CPU Registers
1141 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1142 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1143 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1144 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1146 //===----------------------------------------------------------------------===//
1147 // Instruction aliases
1148 //===----------------------------------------------------------------------===//
1149 def : InstAlias<"move $dst, $src",
1150 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1151 Requires<[NotMips64]>;
1152 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1153 def : InstAlias<"addu $rs, $rt, $imm",
1154 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1155 def : InstAlias<"add $rs, $rt, $imm",
1156 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1157 def : InstAlias<"and $rs, $rt, $imm",
1158 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1159 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1160 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1161 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1162 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1163 def : InstAlias<"not $rt, $rs",
1164 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1165 def : InstAlias<"neg $rt, $rs",
1166 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1167 def : InstAlias<"negu $rt, $rs",
1168 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1169 def : InstAlias<"slt $rs, $rt, $imm",
1170 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1171 def : InstAlias<"xor $rs, $rt, $imm",
1172 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1173 def : InstAlias<"or $rs, $rt, $imm",
1174 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1175 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1176 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1177 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1178 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1179 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1180 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1181 def : InstAlias<"bnez $rs,$offset",
1182 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1183 def : InstAlias<"beqz $rs,$offset",
1184 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1185 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1187 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1188 def : InstAlias<"break", (BREAK 0, 0), 1>;
1189 def : InstAlias<"ei", (EI ZERO), 1>;
1190 def : InstAlias<"di", (DI ZERO), 1>;
1192 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1193 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1194 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1195 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1196 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1197 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1198 def : InstAlias<"sub, $rd, $rs, $imm",
1199 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1200 def : InstAlias<"subu, $rd, $rs, $imm",
1201 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1203 //===----------------------------------------------------------------------===//
1204 // Assembler Pseudo Instructions
1205 //===----------------------------------------------------------------------===//
1207 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1208 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1209 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1210 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1212 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1213 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1214 !strconcat(instr_asm, "\t$rt, $addr")> ;
1215 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1217 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1218 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1219 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1220 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1222 //===----------------------------------------------------------------------===//
1223 // Arbitrary patterns that map to one or more instructions
1224 //===----------------------------------------------------------------------===//
1226 // Load/store pattern templates.
1227 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1228 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1230 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1231 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1234 def : MipsPat<(i32 immSExt16:$in),
1235 (ADDiu ZERO, imm:$in)>;
1236 def : MipsPat<(i32 immZExt16:$in),
1237 (ORi ZERO, imm:$in)>;
1238 def : MipsPat<(i32 immLow16Zero:$in),
1239 (LUi (HI16 imm:$in))>;
1241 // Arbitrary immediates
1242 def : MipsPat<(i32 imm:$imm),
1243 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1245 // Carry MipsPatterns
1246 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1247 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1248 let Predicates = [HasStdEnc, NotDSP] in {
1249 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1250 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1251 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1252 (ADDiu GPR32:$src, imm:$imm)>;
1256 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1257 (JAL tglobaladdr:$dst)>;
1258 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1259 (JAL texternalsym:$dst)>;
1260 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1261 // (JALR GPR32:$dst)>;
1264 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1265 (TAILCALL tglobaladdr:$dst)>;
1266 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1267 (TAILCALL texternalsym:$dst)>;
1269 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1270 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1271 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1272 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1273 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1274 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1276 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1277 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1278 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1279 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1280 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1281 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1283 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1284 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1285 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1286 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1287 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1288 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1289 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1290 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1291 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1292 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1295 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1296 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1297 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1298 (ADDiu GPR32:$gp, tconstpool:$in)>;
1301 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1302 MipsPat<(MipsWrapper RC:$gp, node:$in),
1303 (ADDiuOp RC:$gp, node:$in)>;
1305 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1306 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1307 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1308 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1309 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1310 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1312 // Mips does not have "not", so we expand our way
1313 def : MipsPat<(not GPR32:$in),
1314 (NOR GPR32Opnd:$in, ZERO)>;
1317 let Predicates = [HasStdEnc] in {
1318 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1319 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1320 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1324 let Predicates = [HasStdEnc] in
1325 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1328 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1329 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1330 Instruction SLTiuOp, Register ZEROReg> {
1331 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1332 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1333 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1334 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1336 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1337 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1338 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1339 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1340 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1341 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1342 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1343 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1344 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1345 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1346 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1347 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1349 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1350 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1351 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1352 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1354 def : MipsPat<(brcond RC:$cond, bb:$dst),
1355 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1358 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1360 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1361 (BLEZ i32:$lhs, bb:$dst)>;
1362 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1363 (BGEZ i32:$lhs, bb:$dst)>;
1366 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1367 Instruction SLTuOp, Register ZEROReg> {
1368 def : MipsPat<(seteq RC:$lhs, 0),
1369 (SLTiuOp RC:$lhs, 1)>;
1370 def : MipsPat<(setne RC:$lhs, 0),
1371 (SLTuOp ZEROReg, RC:$lhs)>;
1372 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1373 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1374 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1375 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1378 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1379 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1380 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1381 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1382 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1385 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1386 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1387 (SLTOp RC:$rhs, RC:$lhs)>;
1388 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1389 (SLTuOp RC:$rhs, RC:$lhs)>;
1392 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1393 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1394 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1395 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1396 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1399 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1400 Instruction SLTiuOp> {
1401 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1402 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1403 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1404 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1407 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1408 defm : SetlePats<GPR32, SLT, SLTu>;
1409 defm : SetgtPats<GPR32, SLT, SLTu>;
1410 defm : SetgePats<GPR32, SLT, SLTu>;
1411 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1414 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1416 // Load halfword/word patterns.
1417 let AddedComplexity = 40 in {
1418 let Predicates = [HasStdEnc] in {
1419 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1420 def : LoadRegImmPat<LH, i32, sextloadi16>;
1421 def : LoadRegImmPat<LW, i32, load>;
1425 //===----------------------------------------------------------------------===//
1426 // Floating Point Support
1427 //===----------------------------------------------------------------------===//
1429 include "MipsInstrFPU.td"
1430 include "Mips64InstrInfo.td"
1431 include "MipsCondMov.td"
1436 include "Mips16InstrFormats.td"
1437 include "Mips16InstrInfo.td"
1440 include "MipsDSPInstrFormats.td"
1441 include "MipsDSPInstrInfo.td"
1444 include "MipsMSAInstrFormats.td"
1445 include "MipsMSAInstrInfo.td"
1448 include "MicroMipsInstrFormats.td"
1449 include "MicroMipsInstrInfo.td"
1450 include "MicroMipsInstrFPU.td"