1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
55 // Hi and Lo nodes are used to handle global addresses. Used on
56 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
57 // static model. (nothing to do with Mips Registers Hi and Lo)
58 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
59 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
60 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
62 // TlsGd node is used to handle General Dynamic TLS
63 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
65 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
66 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
67 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
70 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
73 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
75 // These are target-independent nodes, but have target-specific formats.
76 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
77 [SDNPHasChain, SDNPOutGlue]>;
78 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
79 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
82 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
83 [SDNPOptInGlue, SDNPOutGlue]>;
84 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
85 [SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
88 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
89 [SDNPOptInGlue, SDNPOutGlue]>;
92 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
94 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
97 // Target constant nodes that are not part of any isel patterns and remain
98 // unchanged can cause instructions with illegal operands to be emitted.
99 // Wrapper node patterns give the instruction selector a chance to replace
100 // target constant nodes that would otherwise remain unchanged with ADDiu
101 // nodes. Without these wrapper node patterns, the following conditional move
102 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
104 // movn %got(d)($gp), %got(c)($gp), $4
105 // This instruction is illegal since movn can take only register operands.
107 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
109 // Pointer to dynamically allocated stack area.
110 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
111 [SDNPHasChain, SDNPInGlue]>;
113 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
115 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
116 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
118 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
120 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
124 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
126 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
128 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
132 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 //===----------------------------------------------------------------------===//
136 // Mips Instruction Predicate Definitions.
137 //===----------------------------------------------------------------------===//
138 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
139 AssemblerPredicate<"FeatureSEInReg">;
140 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
141 AssemblerPredicate<"FeatureBitCount">;
142 def HasSwap : Predicate<"Subtarget.hasSwap()">,
143 AssemblerPredicate<"FeatureSwap">;
144 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
145 AssemblerPredicate<"FeatureCondMov">;
146 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
147 AssemblerPredicate<"FeatureMips32">;
148 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
149 AssemblerPredicate<"FeatureMips32r2">;
150 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
151 AssemblerPredicate<"FeatureMips64">;
152 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
153 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
154 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
155 AssemblerPredicate<"!FeatureMips64">;
156 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
157 AssemblerPredicate<"FeatureMips64r2">;
158 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
159 AssemblerPredicate<"FeatureN64">;
160 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
161 AssemblerPredicate<"!FeatureN64">;
162 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
163 AssemblerPredicate<"FeatureMips16">;
164 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
165 AssemblerPredicate<"FeatureMips32">;
166 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
167 AssemblerPredicate<"FeatureMips32">;
168 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
169 AssemblerPredicate<"FeatureMips32">;
170 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
171 AssemblerPredicate<"!FeatureMips16">;
173 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
174 let Predicates = [HasStandardEncoding];
177 //===----------------------------------------------------------------------===//
178 // Instruction format superclass
179 //===----------------------------------------------------------------------===//
181 include "MipsInstrFormats.td"
183 //===----------------------------------------------------------------------===//
184 // Mips Operand, Complex Patterns and Transformations Definitions.
185 //===----------------------------------------------------------------------===//
187 // Instruction operand types
188 def jmptarget : Operand<OtherVT> {
189 let EncoderMethod = "getJumpTargetOpValue";
191 def brtarget : Operand<OtherVT> {
192 let EncoderMethod = "getBranchTargetOpValue";
193 let OperandType = "OPERAND_PCREL";
194 let DecoderMethod = "DecodeBranchTarget";
196 def calltarget : Operand<iPTR> {
197 let EncoderMethod = "getJumpTargetOpValue";
199 def calltarget64: Operand<i64>;
200 def simm16 : Operand<i32> {
201 let DecoderMethod= "DecodeSimm16";
203 def simm16_64 : Operand<i64>;
204 def shamt : Operand<i32>;
207 def uimm16 : Operand<i32> {
208 let PrintMethod = "printUnsignedImm";
212 def mem : Operand<i32> {
213 let PrintMethod = "printMemOperand";
214 let MIOperandInfo = (ops CPURegs, simm16);
215 let EncoderMethod = "getMemEncoding";
218 def mem64 : Operand<i64> {
219 let PrintMethod = "printMemOperand";
220 let MIOperandInfo = (ops CPU64Regs, simm16_64);
221 let EncoderMethod = "getMemEncoding";
224 def mem_ea : Operand<i32> {
225 let PrintMethod = "printMemOperandEA";
226 let MIOperandInfo = (ops CPURegs, simm16);
227 let EncoderMethod = "getMemEncoding";
230 def mem_ea_64 : Operand<i64> {
231 let PrintMethod = "printMemOperandEA";
232 let MIOperandInfo = (ops CPU64Regs, simm16_64);
233 let EncoderMethod = "getMemEncoding";
236 // size operand of ext instruction
237 def size_ext : Operand<i32> {
238 let EncoderMethod = "getSizeExtEncoding";
239 let DecoderMethod = "DecodeExtSize";
242 // size operand of ins instruction
243 def size_ins : Operand<i32> {
244 let EncoderMethod = "getSizeInsEncoding";
245 let DecoderMethod = "DecodeInsSize";
248 // Transformation Function - get the lower 16 bits.
249 def LO16 : SDNodeXForm<imm, [{
250 return getImm(N, N->getZExtValue() & 0xFFFF);
253 // Transformation Function - get the higher 16 bits.
254 def HI16 : SDNodeXForm<imm, [{
255 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
258 // Node immediate fits as 16-bit sign extended on target immediate.
260 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
262 // Node immediate fits as 16-bit zero extended on target immediate.
263 // The LO16 param means that only the lower 16 bits of the node
264 // immediate are caught.
266 def immZExt16 : PatLeaf<(imm), [{
267 if (N->getValueType(0) == MVT::i32)
268 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
270 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
273 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
274 def immLow16Zero : PatLeaf<(imm), [{
275 int64_t Val = N->getSExtValue();
276 return isInt<32>(Val) && !(Val & 0xffff);
279 // shamt field must fit in 5 bits.
280 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
282 // Mips Address Mode! SDNode frameindex could possibily be a match
283 // since load and store instructions from stack used it.
285 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
287 //===----------------------------------------------------------------------===//
288 // Pattern fragment for load/store
289 //===----------------------------------------------------------------------===//
290 class UnalignedLoad<PatFrag Node> :
291 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
292 LoadSDNode *LD = cast<LoadSDNode>(N);
293 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
296 class AlignedLoad<PatFrag Node> :
297 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
298 LoadSDNode *LD = cast<LoadSDNode>(N);
299 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
302 class UnalignedStore<PatFrag Node> :
303 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
304 StoreSDNode *SD = cast<StoreSDNode>(N);
305 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
308 class AlignedStore<PatFrag Node> :
309 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
310 StoreSDNode *SD = cast<StoreSDNode>(N);
311 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
314 // Load/Store PatFrags.
315 def sextloadi16_a : AlignedLoad<sextloadi16>;
316 def zextloadi16_a : AlignedLoad<zextloadi16>;
317 def extloadi16_a : AlignedLoad<extloadi16>;
318 def load_a : AlignedLoad<load>;
319 def sextloadi32_a : AlignedLoad<sextloadi32>;
320 def zextloadi32_a : AlignedLoad<zextloadi32>;
321 def extloadi32_a : AlignedLoad<extloadi32>;
322 def truncstorei16_a : AlignedStore<truncstorei16>;
323 def store_a : AlignedStore<store>;
324 def truncstorei32_a : AlignedStore<truncstorei32>;
325 def sextloadi16_u : UnalignedLoad<sextloadi16>;
326 def zextloadi16_u : UnalignedLoad<zextloadi16>;
327 def extloadi16_u : UnalignedLoad<extloadi16>;
328 def load_u : UnalignedLoad<load>;
329 def sextloadi32_u : UnalignedLoad<sextloadi32>;
330 def zextloadi32_u : UnalignedLoad<zextloadi32>;
331 def extloadi32_u : UnalignedLoad<extloadi32>;
332 def truncstorei16_u : UnalignedStore<truncstorei16>;
333 def store_u : UnalignedStore<store>;
334 def truncstorei32_u : UnalignedStore<truncstorei32>;
336 //===----------------------------------------------------------------------===//
337 // Instructions specific format
338 //===----------------------------------------------------------------------===//
340 // Arithmetic and logical instructions with 3 register operands.
341 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
342 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
343 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
344 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
345 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
347 let isCommutable = isComm;
348 let isReMaterializable = 1;
351 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
352 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
353 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
354 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
356 let isCommutable = isComm;
359 // Arithmetic and logical instructions with 2 register operands.
360 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
361 Operand Od, PatLeaf imm_type, RegisterClass RC> :
362 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
363 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
365 let isReMaterializable = 1;
368 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
369 Operand Od, PatLeaf imm_type, RegisterClass RC> :
370 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
371 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
373 // Arithmetic Multiply ADD/SUB
374 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
375 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
376 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
377 !strconcat(instr_asm, "\t$rs, $rt"),
378 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
381 let isCommutable = isComm;
385 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
386 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
387 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
388 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
390 let isCommutable = 1;
394 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
395 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
397 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
398 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
399 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
403 // 32-bit shift instructions.
404 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
406 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
408 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
409 SDNode OpNode, RegisterClass RC>:
410 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
411 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
412 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
413 let shamt = isRotate;
416 // Load Upper Imediate
417 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
418 FI<op, (outs RC:$rt), (ins Imm:$imm16),
419 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
421 let neverHasSideEffects = 1;
422 let isReMaterializable = 1;
425 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
426 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
428 let Inst{25-21} = addr{20-16};
429 let Inst{15-0} = addr{15-0};
430 let DecoderMethod = "DecodeMem";
434 let canFoldAsLoad = 1 in
435 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
436 Operand MemOpnd, bit Pseudo>:
437 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
438 !strconcat(instr_asm, "\t$rt, $addr"),
439 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
440 let isPseudo = Pseudo;
443 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
444 Operand MemOpnd, bit Pseudo>:
445 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
446 !strconcat(instr_asm, "\t$rt, $addr"),
447 [(OpNode RC:$rt, addr:$addr)], IIStore> {
448 let isPseudo = Pseudo;
452 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
454 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
455 Requires<[NotN64, HasStandardEncoding]>;
456 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
457 Requires<[IsN64, HasStandardEncoding]> {
458 let DecoderNamespace = "Mips64";
459 let isCodeGenOnly = 1;
464 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
466 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
467 Requires<[NotN64, HasStandardEncoding]>;
468 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
469 Requires<[IsN64, HasStandardEncoding]> {
470 let DecoderNamespace = "Mips64";
471 let isCodeGenOnly = 1;
476 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
478 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
479 Requires<[NotN64, HasStandardEncoding]>;
480 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
481 Requires<[IsN64, HasStandardEncoding]> {
482 let DecoderNamespace = "Mips64";
483 let isCodeGenOnly = 1;
488 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
490 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
491 Requires<[NotN64, HasStandardEncoding]>;
492 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
493 Requires<[IsN64, HasStandardEncoding]> {
494 let DecoderNamespace = "Mips64";
495 let isCodeGenOnly = 1;
499 // Load/Store Left/Right
500 let canFoldAsLoad = 1 in
501 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
502 RegisterClass RC, Operand MemOpnd> :
503 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
504 !strconcat(instr_asm, "\t$rt, $addr"),
505 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
506 string Constraints = "$src = $rt";
509 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
510 RegisterClass RC, Operand MemOpnd>:
511 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
512 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
515 // 32-bit load left/right.
516 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
517 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
518 Requires<[NotN64, HasStandardEncoding]>;
519 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
520 Requires<[IsN64, HasStandardEncoding]> {
521 let DecoderNamespace = "Mips64";
522 let isCodeGenOnly = 1;
526 // 64-bit load left/right.
527 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
528 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
529 Requires<[NotN64, HasStandardEncoding]>;
530 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
531 Requires<[IsN64, HasStandardEncoding]> {
532 let DecoderNamespace = "Mips64";
533 let isCodeGenOnly = 1;
537 // 32-bit store left/right.
538 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
539 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
540 Requires<[NotN64, HasStandardEncoding]>;
541 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
542 Requires<[IsN64, HasStandardEncoding]> {
543 let DecoderNamespace = "Mips64";
544 let isCodeGenOnly = 1;
548 // 64-bit store left/right.
549 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
550 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
551 Requires<[NotN64, HasStandardEncoding]>;
552 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
553 Requires<[IsN64, HasStandardEncoding]> {
554 let DecoderNamespace = "Mips64";
555 let isCodeGenOnly = 1;
559 // Conditional Branch
560 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
561 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
562 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
563 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
565 let isTerminator = 1;
566 let hasDelaySlot = 1;
570 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
572 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
573 !strconcat(instr_asm, "\t$rs, $imm16"),
574 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
577 let isTerminator = 1;
578 let hasDelaySlot = 1;
583 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
585 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
586 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
587 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
592 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
593 PatLeaf imm_type, RegisterClass RC>:
594 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
595 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
596 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
600 class JumpFJ<bits<6> op, string instr_asm>:
601 FJ<op, (outs), (ins jmptarget:$target),
602 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
606 let hasDelaySlot = 1;
607 let Predicates = [RelocStatic, HasStandardEncoding];
608 let DecoderMethod = "DecodeJumpTarget";
612 // Unconditional branch
613 class UncondBranch<bits<6> op, string instr_asm>:
614 BranchBase<op, (outs), (ins brtarget:$imm16),
615 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
619 let isTerminator = 1;
621 let hasDelaySlot = 1;
622 let Predicates = [RelocPIC, HasStandardEncoding];
626 // Base class for indirect branch and return instruction classes.
627 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
628 class JumpFR<RegisterClass RC, list<dag> pattern>:
629 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", pattern, IIBranch> {
636 class IndirectBranch<RegisterClass RC>: JumpFR<RC, [(brind RC:$rs)]> {
638 let isIndirectBranch = 1;
641 // Return instruction
642 class RetBase<RegisterClass RC>: JumpFR<RC, []> {
644 let isCodeGenOnly = 1;
646 let hasExtraSrcRegAllocReq = 1;
649 // Jump and Link (Call)
650 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
651 class JumpLink<bits<6> op, string instr_asm>:
652 FJ<op, (outs), (ins calltarget:$target),
653 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
655 let DecoderMethod = "DecodeJumpTarget";
658 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
660 FR<op, func, (outs), (ins RC:$rs),
661 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
667 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
668 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
669 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
675 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
676 RegisterClass RC, list<Register> DefRegs>:
677 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
678 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
681 let isCommutable = 1;
683 let neverHasSideEffects = 1;
686 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
687 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
689 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
690 RegisterClass RC, list<Register> DefRegs>:
691 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
692 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
693 [(op RC:$rs, RC:$rt)], itin> {
699 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
700 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
703 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
704 list<Register> UseRegs>:
705 FR<0x00, func, (outs RC:$rd), (ins),
706 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
711 let neverHasSideEffects = 1;
714 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
715 list<Register> DefRegs>:
716 FR<0x00, func, (outs), (ins RC:$rs),
717 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
722 let neverHasSideEffects = 1;
725 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
726 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
727 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
729 // Count Leading Ones/Zeros in Word
730 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
731 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
732 !strconcat(instr_asm, "\t$rd, $rs"),
733 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
734 Requires<[HasBitCount, HasStandardEncoding]> {
739 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
740 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
741 !strconcat(instr_asm, "\t$rd, $rs"),
742 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
743 Requires<[HasBitCount, HasStandardEncoding]> {
748 // Sign Extend in Register.
749 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
751 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
752 !strconcat(instr_asm, "\t$rd, $rt"),
753 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
756 let Predicates = [HasSEInReg, HasStandardEncoding];
760 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
761 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
762 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
765 let Predicates = [HasSwap, HasStandardEncoding];
766 let neverHasSideEffects = 1;
770 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
771 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
772 "rdhwr\t$rt, $rd", [], IIAlu> {
778 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
779 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
780 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
781 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
786 let Predicates = [HasMips32r2, HasStandardEncoding];
789 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
790 FR<0x1f, _funct, (outs RC:$rt),
791 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
792 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
793 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
799 let Predicates = [HasMips32r2, HasStandardEncoding];
800 let Constraints = "$src = $rt";
803 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
804 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
806 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
807 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
808 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
810 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
811 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
812 Requires<[NotN64, HasStandardEncoding]>;
813 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
814 Requires<[IsN64, HasStandardEncoding]> {
815 let DecoderNamespace = "Mips64";
819 // Atomic Compare & Swap.
820 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
822 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
823 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
824 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
826 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
827 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
828 Requires<[NotN64, HasStandardEncoding]>;
829 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
830 Requires<[IsN64, HasStandardEncoding]> {
831 let DecoderNamespace = "Mips64";
835 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
836 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
837 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
841 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
842 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
843 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
845 let Constraints = "$rt = $dst";
848 //===----------------------------------------------------------------------===//
849 // Pseudo instructions
850 //===----------------------------------------------------------------------===//
853 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
854 def RetRA : MipsPseudo<(outs), (ins), "", [(MipsRet)]>;
856 // As stack alignment is always done with addiu, we need a 16-bit immediate
857 let Defs = [SP], Uses = [SP] in {
858 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
859 "!ADJCALLSTACKDOWN $amt",
860 [(callseq_start timm:$amt)]>;
861 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
862 "!ADJCALLSTACKUP $amt1",
863 [(callseq_end timm:$amt1, timm:$amt2)]>;
866 // When handling PIC code the assembler needs .cpload and .cprestore
867 // directives. If the real instructions corresponding these directives
868 // are used, we have the same behavior, but get also a bunch of warnings
869 // from the assembler.
870 let neverHasSideEffects = 1 in
871 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
872 ".cprestore\t$loc", []>;
874 let usesCustomInserter = 1 in {
875 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
876 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
877 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
878 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
879 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
880 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
881 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
882 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
883 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
884 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
885 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
886 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
887 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
888 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
889 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
890 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
891 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
892 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
894 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
895 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
896 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
898 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
899 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
900 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
903 //===----------------------------------------------------------------------===//
904 // Instruction definition
905 //===----------------------------------------------------------------------===//
907 //===----------------------------------------------------------------------===//
908 // MipsI Instructions
909 //===----------------------------------------------------------------------===//
911 /// Arithmetic Instructions (ALU Immediate)
912 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
913 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
914 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
915 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
916 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
917 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
918 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
919 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
921 /// Arithmetic Instructions (3-Operand, R-Type)
922 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
923 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
924 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
925 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
926 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
927 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
928 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
929 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
930 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
931 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
933 /// Shift Instructions
934 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
935 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
936 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
937 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
938 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
939 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
941 // Rotate Instructions
942 let Predicates = [HasMips32r2, HasStandardEncoding] in {
943 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
944 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
947 /// Load and Store Instructions
949 defm LB : LoadM32<0x20, "lb", sextloadi8>;
950 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
951 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
952 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
953 defm LW : LoadM32<0x23, "lw", load_a>;
954 defm SB : StoreM32<0x28, "sb", truncstorei8>;
955 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
956 defm SW : StoreM32<0x2b, "sw", store_a>;
959 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
960 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
961 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
962 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
963 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
965 /// load/store left/right
966 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
967 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
968 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
969 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
971 let hasSideEffects = 1 in
972 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
973 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
978 let Inst{10-6} = stype;
982 /// Load-linked, Store-conditional
983 def LL : LLBase<0x30, "ll", CPURegs, mem>,
984 Requires<[NotN64, HasStandardEncoding]>;
985 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
986 Requires<[IsN64, HasStandardEncoding]> {
987 let DecoderNamespace = "Mips64";
990 def SC : SCBase<0x38, "sc", CPURegs, mem>,
991 Requires<[NotN64, HasStandardEncoding]>;
992 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
993 Requires<[IsN64, HasStandardEncoding]> {
994 let DecoderNamespace = "Mips64";
997 /// Jump and Branch Instructions
998 def J : JumpFJ<0x02, "j">;
999 def JR : IndirectBranch<CPURegs>;
1000 def B : UncondBranch<0x04, "b">;
1001 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
1002 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
1003 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
1004 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
1005 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
1006 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
1008 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
1009 hasDelaySlot = 1, Defs = [RA] in
1010 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
1012 def JAL : JumpLink<0x03, "jal">;
1013 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
1014 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
1015 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
1017 def RET : RetBase<CPURegs>;
1019 /// Multiply and Divide Instructions.
1020 def MULT : Mult32<0x18, "mult", IIImul>;
1021 def MULTu : Mult32<0x19, "multu", IIImul>;
1022 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1023 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1025 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1026 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1027 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1028 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1030 /// Sign Ext In Register Instructions.
1031 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1032 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1035 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1036 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1038 /// Word Swap Bytes Within Halfwords
1039 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1043 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1045 // FrameIndexes are legalized when they are operands from load/store
1046 // instructions. The same not happens for stack address copies, so an
1047 // add op with mem ComplexPattern is used and the stack address copy
1048 // can be matched. It's similar to Sparc LEA_ADDRi
1049 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1050 let isCodeGenOnly = 1;
1053 // DynAlloc node points to dynamically allocated stack space.
1054 // $sp is added to the list of implicitly used registers to prevent dead code
1055 // elimination from removing instructions that modify $sp.
1057 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1058 let isCodeGenOnly = 1;
1062 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1063 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1064 def MSUB : MArithR<4, "msub", MipsMSub>;
1065 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1067 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1068 // it is a real instruction.
1069 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
1070 Requires<[HasMips32, HasStandardEncoding]>;
1072 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1074 def EXT : ExtBase<0, "ext", CPURegs>;
1075 def INS : InsBase<4, "ins", CPURegs>;
1077 //===----------------------------------------------------------------------===//
1078 // Arbitrary patterns that map to one or more instructions
1079 //===----------------------------------------------------------------------===//
1082 def : MipsPat<(i32 immSExt16:$in),
1083 (ADDiu ZERO, imm:$in)>;
1084 def : MipsPat<(i32 immZExt16:$in),
1085 (ORi ZERO, imm:$in)>;
1086 def : MipsPat<(i32 immLow16Zero:$in),
1087 (LUi (HI16 imm:$in))>;
1089 // Arbitrary immediates
1090 def : MipsPat<(i32 imm:$imm),
1091 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1093 // Carry MipsPatterns
1094 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1095 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1096 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1097 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1098 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1099 (ADDiu CPURegs:$src, imm:$imm)>;
1102 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1103 (JAL tglobaladdr:$dst)>;
1104 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1105 (JAL texternalsym:$dst)>;
1106 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1107 // (JALR CPURegs:$dst)>;
1110 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1111 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1112 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1113 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1114 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1116 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1117 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1118 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1119 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1120 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1122 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1123 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1124 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1125 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1126 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1127 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1128 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1129 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1130 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1131 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1134 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1135 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1136 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1137 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1140 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1141 MipsPat<(MipsWrapper RC:$gp, node:$in),
1142 (ADDiuOp RC:$gp, node:$in)>;
1144 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1145 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1146 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1147 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1148 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1149 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1151 // Mips does not have "not", so we expand our way
1152 def : MipsPat<(not CPURegs:$in),
1153 (NOR CPURegs:$in, ZERO)>;
1156 let Predicates = [NotN64, HasStandardEncoding] in {
1157 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1158 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1159 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1160 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1162 let Predicates = [IsN64, HasStandardEncoding] in {
1163 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1164 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1165 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1166 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1170 let Predicates = [NotN64, HasStandardEncoding] in {
1171 def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1172 def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1174 let Predicates = [IsN64, HasStandardEncoding] in {
1175 def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1176 def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1180 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1181 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1182 Instruction SLTiuOp, Register ZEROReg> {
1183 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1184 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1185 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1186 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1188 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1189 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1190 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1191 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1192 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1193 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1194 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1195 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1197 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1198 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1199 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1200 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1202 def : MipsPat<(brcond RC:$cond, bb:$dst),
1203 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1206 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1209 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1210 Instruction SLTuOp, Register ZEROReg> {
1211 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1212 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1213 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1214 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1217 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1218 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1219 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1220 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1221 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1224 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1225 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1226 (SLTOp RC:$rhs, RC:$lhs)>;
1227 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1228 (SLTuOp RC:$rhs, RC:$lhs)>;
1231 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1232 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1233 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1234 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1235 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1238 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1239 Instruction SLTiuOp> {
1240 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1241 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1242 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1243 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1246 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1247 defm : SetlePats<CPURegs, SLT, SLTu>;
1248 defm : SetgtPats<CPURegs, SLT, SLTu>;
1249 defm : SetgePats<CPURegs, SLT, SLTu>;
1250 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1252 // select MipsDynAlloc
1253 def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1256 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1258 //===----------------------------------------------------------------------===//
1259 // Floating Point Support
1260 //===----------------------------------------------------------------------===//
1262 include "MipsInstrFPU.td"
1263 include "Mips64InstrInfo.td"
1264 include "MipsCondMov.td"
1269 include "Mips16InstrFormats.td"
1270 include "Mips16InstrInfo.td"