1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"FeatureMips32r6">;
171 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"!FeatureMips32r6">;
173 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
176 AssemblerPredicate<"!FeatureGP64Bit">;
177 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
178 AssemblerPredicate<"FeatureMips64">;
179 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
180 AssemblerPredicate<"FeatureMips64r2">;
181 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"FeatureMips64r6">;
183 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"!FeatureMips64r6">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_4_32 {
224 list<Predicate> InsnPredicates = [NotMips4_32];
226 class ISA_MIPS1_NOT_32R6_64R6 {
227 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
229 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
230 class ISA_MIPS2_NOT_32R6_64R6 {
231 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
233 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
234 class ISA_MIPS3_NOT_32R6_64R6 {
235 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
237 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
238 class ISA_MIPS32_NOT_32R6_64R6 {
239 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
241 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
242 class ISA_MIPS32R2_NOT_32R6_64R6 {
243 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
245 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
246 class ISA_MIPS64_NOT_64R6 {
247 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
249 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
250 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
251 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
253 // The portions of MIPS-III that were also added to MIPS32
254 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
256 // The portions of MIPS-III that were also added to MIPS32 but were removed in
257 // MIPS32r6 and MIPS64r6.
258 class INSN_MIPS3_32_NOT_32R6_64R6 {
259 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
262 // The portions of MIPS-III that were also added to MIPS32
263 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
265 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS4_32_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
271 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
272 // MIPS32r6 and MIPS64r6.
273 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
274 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
277 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
278 // MIPS32r6 and MIPS64r6.
279 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
280 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
283 //===----------------------------------------------------------------------===//
285 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
286 let EncodingPredicates = [HasStdEnc];
289 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
290 InstAlias<Asm, Result, Emit>, PredicateControl;
293 bit isCommutable = 1;
310 bit isTerminator = 1;
313 bit hasExtraSrcRegAllocReq = 1;
314 bit isCodeGenOnly = 1;
317 class IsAsCheapAsAMove {
318 bit isAsCheapAsAMove = 1;
321 class NeverHasSideEffects {
322 bit hasSideEffects = 0;
325 //===----------------------------------------------------------------------===//
326 // Instruction format superclass
327 //===----------------------------------------------------------------------===//
329 include "MipsInstrFormats.td"
331 //===----------------------------------------------------------------------===//
332 // Mips Operand, Complex Patterns and Transformations Definitions.
333 //===----------------------------------------------------------------------===//
335 def MipsJumpTargetAsmOperand : AsmOperandClass {
336 let Name = "JumpTarget";
337 let ParserMethod = "parseJumpTarget";
338 let PredicateMethod = "isImm";
339 let RenderMethod = "addImmOperands";
342 // Instruction operand types
343 def jmptarget : Operand<OtherVT> {
344 let EncoderMethod = "getJumpTargetOpValue";
345 let ParserMatchClass = MipsJumpTargetAsmOperand;
347 def brtarget : Operand<OtherVT> {
348 let EncoderMethod = "getBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
350 let DecoderMethod = "DecodeBranchTarget";
351 let ParserMatchClass = MipsJumpTargetAsmOperand;
353 def calltarget : Operand<iPTR> {
354 let EncoderMethod = "getJumpTargetOpValue";
355 let ParserMatchClass = MipsJumpTargetAsmOperand;
358 def simm9 : Operand<i32>;
359 def simm10 : Operand<i32>;
360 def simm11 : Operand<i32>;
362 def simm16 : Operand<i32> {
363 let DecoderMethod= "DecodeSimm16";
366 def simm19_lsl2 : Operand<i32> {
367 let EncoderMethod = "getSimm19Lsl2Encoding";
368 let DecoderMethod = "DecodeSimm19Lsl2";
369 let ParserMatchClass = MipsJumpTargetAsmOperand;
372 def simm18_lsl3 : Operand<i32> {
373 let EncoderMethod = "getSimm18Lsl3Encoding";
374 let DecoderMethod = "DecodeSimm18Lsl3";
375 let ParserMatchClass = MipsJumpTargetAsmOperand;
378 def simm20 : Operand<i32> {
381 def uimm20 : Operand<i32> {
384 def uimm10 : Operand<i32> {
387 def simm16_64 : Operand<i64> {
388 let DecoderMethod = "DecodeSimm16";
392 def uimmz : Operand<i32> {
393 let PrintMethod = "printUnsignedImm";
397 def uimm2 : Operand<i32> {
398 let PrintMethod = "printUnsignedImm";
401 def uimm3 : Operand<i32> {
402 let PrintMethod = "printUnsignedImm";
405 def uimm5 : Operand<i32> {
406 let PrintMethod = "printUnsignedImm";
409 def uimm6 : Operand<i32> {
410 let PrintMethod = "printUnsignedImm";
413 def uimm16 : Operand<i32> {
414 let PrintMethod = "printUnsignedImm";
417 def pcrel16 : Operand<i32> {
420 def MipsMemAsmOperand : AsmOperandClass {
422 let ParserMethod = "parseMemOperand";
425 def MipsMemSimm11AsmOperand : AsmOperandClass {
426 let Name = "MemOffsetSimm11";
427 let SuperClasses = [MipsMemAsmOperand];
428 let RenderMethod = "addMemOperands";
429 let ParserMethod = "parseMemOperand";
430 let PredicateMethod = "isMemWithSimmOffset<11>";
433 def MipsMemSimm16AsmOperand : AsmOperandClass {
434 let Name = "MemOffsetSimm16";
435 let SuperClasses = [MipsMemAsmOperand];
436 let RenderMethod = "addMemOperands";
437 let ParserMethod = "parseMemOperand";
438 let PredicateMethod = "isMemWithSimmOffset<16>";
441 def MipsInvertedImmoperand : AsmOperandClass {
443 let RenderMethod = "addImmOperands";
444 let ParserMethod = "parseInvNum";
447 def InvertedImOperand : Operand<i32> {
448 let ParserMatchClass = MipsInvertedImmoperand;
451 def InvertedImOperand64 : Operand<i64> {
452 let ParserMatchClass = MipsInvertedImmoperand;
455 class mem_generic : Operand<iPTR> {
456 let PrintMethod = "printMemOperand";
457 let MIOperandInfo = (ops ptr_rc, simm16);
458 let EncoderMethod = "getMemEncoding";
459 let ParserMatchClass = MipsMemAsmOperand;
460 let OperandType = "OPERAND_MEMORY";
464 def mem : mem_generic;
466 // MSA specific address operand
467 def mem_msa : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm10);
469 let EncoderMethod = "getMSAMemEncoding";
472 def mem_simm9 : mem_generic {
473 let MIOperandInfo = (ops ptr_rc, simm9);
474 let EncoderMethod = "getMemEncoding";
477 def mem_simm11 : mem_generic {
478 let MIOperandInfo = (ops ptr_rc, simm11);
479 let EncoderMethod = "getMemEncoding";
480 let ParserMatchClass = MipsMemSimm11AsmOperand;
483 def mem_simm16 : mem_generic {
484 let MIOperandInfo = (ops ptr_rc, simm16);
485 let EncoderMethod = "getMemEncoding";
486 let ParserMatchClass = MipsMemSimm16AsmOperand;
489 def mem_ea : Operand<iPTR> {
490 let PrintMethod = "printMemOperandEA";
491 let MIOperandInfo = (ops ptr_rc, simm16);
492 let EncoderMethod = "getMemEncoding";
493 let OperandType = "OPERAND_MEMORY";
496 def PtrRC : Operand<iPTR> {
497 let MIOperandInfo = (ops ptr_rc);
498 let DecoderMethod = "DecodePtrRegisterClass";
499 let ParserMatchClass = GPR32AsmOperand;
502 // size operand of ext instruction
503 def size_ext : Operand<i32> {
504 let EncoderMethod = "getSizeExtEncoding";
505 let DecoderMethod = "DecodeExtSize";
508 // size operand of ins instruction
509 def size_ins : Operand<i32> {
510 let EncoderMethod = "getSizeInsEncoding";
511 let DecoderMethod = "DecodeInsSize";
514 // Transformation Function - get the lower 16 bits.
515 def LO16 : SDNodeXForm<imm, [{
516 return getImm(N, N->getZExtValue() & 0xFFFF);
519 // Transformation Function - get the higher 16 bits.
520 def HI16 : SDNodeXForm<imm, [{
521 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
525 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
527 // Node immediate is zero (e.g. insve.d)
528 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
530 // Node immediate fits as 16-bit sign extended on target immediate.
532 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
534 // Node immediate fits as 16-bit sign extended on target immediate.
536 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
538 // Node immediate fits as 15-bit sign extended on target immediate.
540 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
542 // Node immediate fits as 16-bit zero extended on target immediate.
543 // The LO16 param means that only the lower 16 bits of the node
544 // immediate are caught.
546 def immZExt16 : PatLeaf<(imm), [{
547 if (N->getValueType(0) == MVT::i32)
548 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
550 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
553 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
554 def immLow16Zero : PatLeaf<(imm), [{
555 int64_t Val = N->getSExtValue();
556 return isInt<32>(Val) && !(Val & 0xffff);
559 // shamt field must fit in 5 bits.
560 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
562 // True if (N + 1) fits in 16-bit field.
563 def immSExt16Plus1 : PatLeaf<(imm), [{
564 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
567 // Mips Address Mode! SDNode frameindex could possibily be a match
568 // since load and store instructions from stack used it.
570 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
573 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
576 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
579 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
581 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
583 //===----------------------------------------------------------------------===//
584 // Instructions specific format
585 //===----------------------------------------------------------------------===//
587 // Arithmetic and logical instructions with 3 register operands.
588 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
589 InstrItinClass Itin = NoItinerary,
590 SDPatternOperator OpNode = null_frag>:
591 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
592 !strconcat(opstr, "\t$rd, $rs, $rt"),
593 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
594 let isCommutable = isComm;
595 let isReMaterializable = 1;
596 let TwoOperandAliasConstraint = "$rd = $rs";
599 // Arithmetic and logical instructions with 2 register operands.
600 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
601 InstrItinClass Itin = NoItinerary,
602 SDPatternOperator imm_type = null_frag,
603 SDPatternOperator OpNode = null_frag> :
604 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
605 !strconcat(opstr, "\t$rt, $rs, $imm16"),
606 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
608 let isReMaterializable = 1;
609 let TwoOperandAliasConstraint = "$rs = $rt";
612 // Arithmetic Multiply ADD/SUB
613 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
614 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
615 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
616 let Defs = [HI0, LO0];
617 let Uses = [HI0, LO0];
618 let isCommutable = isComm;
622 class LogicNOR<string opstr, RegisterOperand RO>:
623 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
624 !strconcat(opstr, "\t$rd, $rs, $rt"),
625 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
626 let isCommutable = 1;
630 class shift_rotate_imm<string opstr, Operand ImmOpnd,
631 RegisterOperand RO, InstrItinClass itin,
632 SDPatternOperator OpNode = null_frag,
633 SDPatternOperator PF = null_frag> :
634 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
635 !strconcat(opstr, "\t$rd, $rt, $shamt"),
636 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
637 let TwoOperandAliasConstraint = "$rt = $rd";
640 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
641 SDPatternOperator OpNode = null_frag>:
642 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
643 !strconcat(opstr, "\t$rd, $rt, $rs"),
644 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
647 // Load Upper Imediate
648 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
649 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
650 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
651 let hasSideEffects = 0;
652 let isReMaterializable = 1;
656 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
657 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
658 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
659 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
660 let DecoderMethod = "DecodeMem";
661 let canFoldAsLoad = 1;
665 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
666 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
667 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
668 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
669 let DecoderMethod = "DecodeMem";
673 // Load/Store Left/Right
674 let canFoldAsLoad = 1 in
675 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
676 InstrItinClass Itin> :
677 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
678 !strconcat(opstr, "\t$rt, $addr"),
679 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
680 let DecoderMethod = "DecodeMem";
681 string Constraints = "$src = $rt";
684 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
685 InstrItinClass Itin> :
686 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
687 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
688 let DecoderMethod = "DecodeMem";
692 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
693 SDPatternOperator OpNode= null_frag> :
694 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
695 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
696 let DecoderMethod = "DecodeFMem2";
700 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
701 SDPatternOperator OpNode= null_frag> :
702 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
703 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
704 let DecoderMethod = "DecodeFMem2";
709 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
710 SDPatternOperator OpNode= null_frag> :
711 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
712 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
713 let DecoderMethod = "DecodeFMem3";
717 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
718 SDPatternOperator OpNode= null_frag> :
719 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
720 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
721 let DecoderMethod = "DecodeFMem3";
725 // Conditional Branch
726 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
727 RegisterOperand RO, bit DelaySlot = 1> :
728 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
729 !strconcat(opstr, "\t$rs, $rt, $offset"),
730 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
733 let isTerminator = 1;
734 let hasDelaySlot = DelaySlot;
738 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
739 RegisterOperand RO, bit DelaySlot = 1> :
740 InstSE<(outs), (ins RO:$rs, opnd:$offset),
741 !strconcat(opstr, "\t$rs, $offset"),
742 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
745 let isTerminator = 1;
746 let hasDelaySlot = DelaySlot;
751 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
752 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
753 !strconcat(opstr, "\t$rd, $rs, $rt"),
754 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
755 II_SLT_SLTU, FrmR, opstr>;
757 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
759 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
760 !strconcat(opstr, "\t$rt, $rs, $imm16"),
761 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
762 II_SLTI_SLTIU, FrmI, opstr>;
765 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
766 SDPatternOperator targetoperator, string bopstr> :
767 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
768 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
771 let hasDelaySlot = 1;
772 let DecoderMethod = "DecodeJumpTarget";
776 // Unconditional branch
777 class UncondBranch<Instruction BEQInst> :
778 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
779 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
781 let isTerminator = 1;
783 let hasDelaySlot = 1;
784 let AdditionalPredicates = [RelocPIC];
788 // Base class for indirect branch and return instruction classes.
789 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
790 class JumpFR<string opstr, RegisterOperand RO,
791 SDPatternOperator operator = null_frag>:
792 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
796 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
798 let isIndirectBranch = 1;
801 // Jump and Link (Call)
802 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
803 class JumpLink<string opstr, DAGOperand opnd> :
804 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
805 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
806 let DecoderMethod = "DecodeJumpTarget";
809 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
810 Register RetReg, RegisterOperand ResRO = RO>:
811 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
812 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
814 class JumpLinkReg<string opstr, RegisterOperand RO>:
815 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
818 class BGEZAL_FT<string opstr, DAGOperand opnd,
819 RegisterOperand RO, bit DelaySlot = 1> :
820 InstSE<(outs), (ins RO:$rs, opnd:$offset),
821 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
822 let hasDelaySlot = DelaySlot;
827 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
828 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
829 class TailCall<Instruction JumpInst> :
830 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
831 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
833 class TailCallReg<RegisterOperand RO, Instruction JRInst,
834 RegisterOperand ResRO = RO> :
835 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
836 PseudoInstExpansion<(JRInst ResRO:$rs)>;
839 class BAL_BR_Pseudo<Instruction RealInst> :
840 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
841 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
843 let isTerminator = 1;
845 let hasDelaySlot = 1;
850 class SYS_FT<string opstr> :
851 InstSE<(outs), (ins uimm20:$code_),
852 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
854 class BRK_FT<string opstr> :
855 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
856 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
860 class ER_FT<string opstr> :
861 InstSE<(outs), (ins),
862 opstr, [], NoItinerary, FrmOther, opstr>;
865 class DEI_FT<string opstr, RegisterOperand RO> :
866 InstSE<(outs RO:$rt), (ins),
867 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
870 class WAIT_FT<string opstr> :
871 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
874 let hasSideEffects = 1 in
875 class SYNC_FT<string opstr> :
876 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
877 NoItinerary, FrmOther, opstr>;
879 class SYNCI_FT<string opstr> :
880 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
881 NoItinerary, FrmOther, opstr> {
882 let hasSideEffects = 1;
883 let DecoderMethod = "DecodeSyncI";
886 let hasSideEffects = 1 in
887 class TEQ_FT<string opstr, RegisterOperand RO> :
888 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
889 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
892 class TEQI_FT<string opstr, RegisterOperand RO> :
893 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
894 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
896 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
897 list<Register> DefRegs> :
898 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
900 let isCommutable = 1;
902 let hasSideEffects = 0;
905 // Pseudo multiply/divide instruction with explicit accumulator register
907 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
908 SDPatternOperator OpNode, InstrItinClass Itin,
909 bit IsComm = 1, bit HasSideEffects = 0,
910 bit UsesCustomInserter = 0> :
911 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
912 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
913 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
914 let isCommutable = IsComm;
915 let hasSideEffects = HasSideEffects;
916 let usesCustomInserter = UsesCustomInserter;
919 // Pseudo multiply add/sub instruction with explicit accumulator register
921 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
923 : PseudoSE<(outs ACC64:$ac),
924 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
926 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
928 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
929 string Constraints = "$acin = $ac";
932 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
933 list<Register> DefRegs> :
934 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
935 [], itin, FrmR, opstr> {
940 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
941 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
942 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
944 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
945 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
948 let hasSideEffects = 0;
951 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
952 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
953 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
956 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
957 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
960 let hasSideEffects = 0;
963 class EffectiveAddress<string opstr, RegisterOperand RO> :
964 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
965 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
966 !strconcat(opstr, "_lea")> {
967 let isCodeGenOnly = 1;
968 let DecoderMethod = "DecodeMem";
971 // Count Leading Ones/Zeros in Word
972 class CountLeading0<string opstr, RegisterOperand RO>:
973 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
974 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
976 class CountLeading1<string opstr, RegisterOperand RO>:
977 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
978 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
980 // Sign Extend in Register.
981 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
982 InstrItinClass itin> :
983 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
984 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
987 class SubwordSwap<string opstr, RegisterOperand RO>:
988 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
989 NoItinerary, FrmR, opstr> {
990 let hasSideEffects = 0;
994 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
995 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
996 II_RDHWR, FrmR, "rdhwr">;
999 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1000 SDPatternOperator Op = null_frag>:
1001 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1002 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1003 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
1004 FrmR, opstr>, ISA_MIPS32R2;
1006 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1007 SDPatternOperator Op = null_frag>:
1008 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1009 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1010 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1011 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
1012 let Constraints = "$src = $rt";
1015 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1016 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1017 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1018 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1020 // Atomic Compare & Swap.
1021 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1022 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1023 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1025 class LLBase<string opstr, RegisterOperand RO> :
1026 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1027 [], NoItinerary, FrmI> {
1028 let DecoderMethod = "DecodeMem";
1032 class SCBase<string opstr, RegisterOperand RO> :
1033 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1034 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1035 let DecoderMethod = "DecodeMem";
1037 let Constraints = "$rt = $dst";
1040 class MFC3OP<string asmstr, RegisterOperand RO> :
1041 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1042 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1044 class TrapBase<Instruction RealInst>
1045 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1046 PseudoInstExpansion<(RealInst 0, 0)> {
1048 let isTerminator = 1;
1049 let isCodeGenOnly = 1;
1052 //===----------------------------------------------------------------------===//
1053 // Pseudo instructions
1054 //===----------------------------------------------------------------------===//
1057 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1058 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1060 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1061 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1062 [(callseq_start timm:$amt)]>;
1063 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1064 [(callseq_end timm:$amt1, timm:$amt2)]>;
1067 let usesCustomInserter = 1 in {
1068 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1069 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1070 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1071 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1072 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1073 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1074 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1075 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1076 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1077 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1078 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1079 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1080 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1081 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1082 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1083 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1084 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1085 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1087 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1088 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1089 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1091 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1092 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1093 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1096 /// Pseudo instructions for loading and storing accumulator registers.
1097 let isPseudo = 1, isCodeGenOnly = 1 in {
1098 def LOAD_ACC64 : Load<"", ACC64>;
1099 def STORE_ACC64 : Store<"", ACC64>;
1102 // We need these two pseudo instructions to avoid offset calculation for long
1103 // branches. See the comment in file MipsLongBranch.cpp for detailed
1106 // Expands to: lui $dst, %hi($tgt - $baltgt)
1107 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1108 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1110 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1111 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1112 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1114 //===----------------------------------------------------------------------===//
1115 // Instruction definition
1116 //===----------------------------------------------------------------------===//
1117 //===----------------------------------------------------------------------===//
1118 // MipsI Instructions
1119 //===----------------------------------------------------------------------===//
1121 /// Arithmetic Instructions (ALU Immediate)
1122 let AdditionalPredicates = [NotInMicroMips] in {
1123 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1124 add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
1126 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1127 ISA_MIPS1_NOT_32R6_64R6;
1128 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1130 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1132 let AdditionalPredicates = [NotInMicroMips] in {
1133 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1136 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1139 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1142 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1144 /// Arithmetic Instructions (3-Operand, R-Type)
1145 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1147 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1149 let Defs = [HI0, LO0] in
1150 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1151 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1152 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1153 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1154 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1155 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1156 let AdditionalPredicates = [NotInMicroMips] in {
1157 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1159 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1161 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1164 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1166 /// Shift Instructions
1167 let AdditionalPredicates = [NotInMicroMips] in {
1168 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1169 immZExt5>, SRA_FM<0, 0>;
1170 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1171 immZExt5>, SRA_FM<2, 0>;
1173 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1174 immZExt5>, SRA_FM<3, 0>;
1175 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1177 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1179 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1182 // Rotate Instructions
1183 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1185 SRA_FM<2, 1>, ISA_MIPS32R2;
1186 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1187 SRLV_FM<6, 1>, ISA_MIPS32R2;
1189 /// Load and Store Instructions
1191 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1192 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1194 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1196 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1197 let AdditionalPredicates = [NotInMicroMips] in {
1198 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1201 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1202 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1203 let AdditionalPredicates = [NotInMicroMips] in {
1204 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1207 /// load/store left/right
1208 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1209 AdditionalPredicates = [NotInMicroMips] in {
1210 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1211 ISA_MIPS1_NOT_32R6_64R6;
1212 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1213 ISA_MIPS1_NOT_32R6_64R6;
1214 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1215 ISA_MIPS1_NOT_32R6_64R6;
1216 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1217 ISA_MIPS1_NOT_32R6_64R6;
1220 let AdditionalPredicates = [NotInMicroMips] in {
1221 // COP2 Memory Instructions
1222 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1223 ISA_MIPS1_NOT_32R6_64R6;
1224 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1225 ISA_MIPS1_NOT_32R6_64R6;
1226 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1227 ISA_MIPS2_NOT_32R6_64R6;
1228 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1229 ISA_MIPS2_NOT_32R6_64R6;
1231 // COP3 Memory Instructions
1232 let DecoderNamespace = "COP3_" in {
1233 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1234 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1235 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1237 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1242 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1243 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1245 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1246 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1247 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1248 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1249 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1250 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1252 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1253 ISA_MIPS2_NOT_32R6_64R6;
1254 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1255 ISA_MIPS2_NOT_32R6_64R6;
1256 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1257 ISA_MIPS2_NOT_32R6_64R6;
1258 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1259 ISA_MIPS2_NOT_32R6_64R6;
1260 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1261 ISA_MIPS2_NOT_32R6_64R6;
1262 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1263 ISA_MIPS2_NOT_32R6_64R6;
1265 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1266 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1267 def TRAP : TrapBase<BREAK>;
1268 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1270 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1271 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1273 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1274 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1276 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1277 AdditionalPredicates = [NotInMicroMips] in {
1278 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1280 /// Load-linked, Store-conditional
1281 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1282 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1285 /// Jump and Branch Instructions
1286 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1287 AdditionalRequires<[RelocStatic]>, IsBranch;
1288 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1289 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1290 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1291 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1292 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1293 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1294 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1295 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1297 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1298 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1299 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1301 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1302 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1303 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1305 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1306 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1307 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1309 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1310 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1311 def B : UncondBranch<BEQ>;
1313 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1314 let AdditionalPredicates = [NotInMicroMips] in {
1315 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1316 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1319 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1320 ISA_MIPS32_NOT_32R6_64R6;
1321 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1322 ISA_MIPS1_NOT_32R6_64R6;
1323 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1324 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1325 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1326 ISA_MIPS1_NOT_32R6_64R6;
1327 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1328 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1329 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1330 def TAILCALL : TailCall<J>;
1331 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1333 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1334 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1335 class PseudoIndirectBranchBase<RegisterOperand RO> :
1336 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1339 let hasDelaySlot = 1;
1341 let isIndirectBranch = 1;
1344 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1346 // Return instructions are matched as a RetRA instruction, then ar expanded
1347 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1348 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1350 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1352 let isTerminator = 1;
1354 let hasDelaySlot = 1;
1356 let isCodeGenOnly = 1;
1358 let hasExtraSrcRegAllocReq = 1;
1361 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1363 // Exception handling related node and instructions.
1364 // The conversion sequence is:
1365 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1366 // MIPSeh_return -> (stack change + indirect branch)
1368 // MIPSeh_return takes the place of regular return instruction
1369 // but takes two arguments (V1, V0) which are used for storing
1370 // the offset and return address respectively.
1371 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1373 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1374 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1376 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1377 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1378 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1379 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1381 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1384 /// Multiply and Divide Instructions.
1385 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1386 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1387 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1388 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1389 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1390 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1391 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1392 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1394 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1395 ISA_MIPS1_NOT_32R6_64R6;
1396 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1397 ISA_MIPS1_NOT_32R6_64R6;
1398 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1399 AdditionalPredicates = [NotInMicroMips] in {
1400 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1401 ISA_MIPS1_NOT_32R6_64R6;
1402 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1403 ISA_MIPS1_NOT_32R6_64R6;
1406 /// Sign Ext In Register Instructions.
1407 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1408 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1409 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1410 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1413 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1414 ISA_MIPS32_NOT_32R6_64R6;
1415 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1416 ISA_MIPS32_NOT_32R6_64R6;
1418 /// Word Swap Bytes Within Halfwords
1419 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1422 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1424 // FrameIndexes are legalized when they are operands from load/store
1425 // instructions. The same not happens for stack address copies, so an
1426 // add op with mem ComplexPattern is used and the stack address copy
1427 // can be matched. It's similar to Sparc LEA_ADDRi
1428 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1431 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1432 ISA_MIPS32_NOT_32R6_64R6;
1433 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1434 ISA_MIPS32_NOT_32R6_64R6;
1435 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1436 ISA_MIPS32_NOT_32R6_64R6;
1437 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1438 ISA_MIPS32_NOT_32R6_64R6;
1440 let AdditionalPredicates = [NotDSP] in {
1441 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1442 ISA_MIPS1_NOT_32R6_64R6;
1443 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1444 ISA_MIPS1_NOT_32R6_64R6;
1445 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1446 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1447 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1448 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1449 ISA_MIPS32_NOT_32R6_64R6;
1450 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1451 ISA_MIPS32_NOT_32R6_64R6;
1452 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1453 ISA_MIPS32_NOT_32R6_64R6;
1454 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1455 ISA_MIPS32_NOT_32R6_64R6;
1458 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1459 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1460 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1461 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1463 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1465 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1466 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1468 /// Move Control Registers From/To CPU Registers
1469 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1470 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1471 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1472 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1474 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1476 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1477 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1478 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1480 // JR_HB and JALR_HB are defined here using the new style naming
1481 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1482 // and because of that it doesn't follow the naming convention of the
1483 // rest of the file. To avoid a mixture of old vs new style, the new
1484 // style was chosen.
1485 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1486 dag OutOperandList = (outs);
1487 dag InOperandList = (ins GPROpnd:$rs);
1488 string AsmString = !strconcat(instr_asm, "\t$rs");
1489 list<dag> Pattern = [];
1492 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1493 dag OutOperandList = (outs GPROpnd:$rd);
1494 dag InOperandList = (ins GPROpnd:$rs);
1495 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1496 list<dag> Pattern = [];
1499 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1500 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1502 let isIndirectBranch=1;
1508 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1509 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1510 let isIndirectBranch=1;
1514 class JR_HB_ENC : JR_HB_FM<8>;
1515 class JALR_HB_ENC : JALR_HB_FM<9>;
1517 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1518 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1520 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1522 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1523 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1524 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1525 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1527 class CacheOp<string instr_asm, Operand MemOpnd> :
1528 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1529 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1531 let DecoderMethod = "DecodeCacheOp";
1534 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1535 INSN_MIPS3_32_NOT_32R6_64R6;
1536 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1537 INSN_MIPS3_32_NOT_32R6_64R6;
1539 //===----------------------------------------------------------------------===//
1540 // Instruction aliases
1541 //===----------------------------------------------------------------------===//
1542 def : MipsInstAlias<"move $dst, $src",
1543 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1545 let AdditionalPredicates = [NotInMicroMips];
1547 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1548 ISA_MIPS1_NOT_32R6_64R6;
1549 def : MipsInstAlias<"addu $rs, $rt, $imm",
1550 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1551 def : MipsInstAlias<"addu $rs, $imm",
1552 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1553 def : MipsInstAlias<"add $rs, $rt, $imm",
1554 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1555 ISA_MIPS1_NOT_32R6_64R6;
1556 def : MipsInstAlias<"add $rs, $imm",
1557 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1558 ISA_MIPS1_NOT_32R6_64R6;
1559 def : MipsInstAlias<"and $rs, $rt, $imm",
1560 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1561 def : MipsInstAlias<"and $rs, $imm",
1562 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1563 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1564 let Predicates = [NotInMicroMips] in {
1565 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1567 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1568 def : MipsInstAlias<"not $rt, $rs",
1569 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1570 def : MipsInstAlias<"neg $rt, $rs",
1571 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1572 def : MipsInstAlias<"negu $rt",
1573 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1574 def : MipsInstAlias<"negu $rt, $rs",
1575 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1576 def : MipsInstAlias<"slt $rs, $rt, $imm",
1577 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1578 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1579 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1580 def : MipsInstAlias<"xor $rs, $rt, $imm",
1581 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1582 def : MipsInstAlias<"or $rs, $rt, $imm",
1583 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1584 def : MipsInstAlias<"or $rs, $imm",
1585 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1586 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1587 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1588 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1589 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1590 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1591 let AdditionalPredicates = [NotInMicroMips] in {
1592 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1594 def : MipsInstAlias<"bnez $rs,$offset",
1595 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1596 def : MipsInstAlias<"beqz $rs,$offset",
1597 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1598 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1600 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1601 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1602 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1603 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1605 def : MipsInstAlias<"teq $rs, $rt",
1606 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1607 def : MipsInstAlias<"tge $rs, $rt",
1608 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1609 def : MipsInstAlias<"tgeu $rs, $rt",
1610 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1611 def : MipsInstAlias<"tlt $rs, $rt",
1612 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1613 def : MipsInstAlias<"tltu $rs, $rt",
1614 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1615 def : MipsInstAlias<"tne $rs, $rt",
1616 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1618 def : MipsInstAlias<"sll $rd, $rt, $rs",
1619 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1620 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1621 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1622 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1623 def : MipsInstAlias<"sub $rs, $imm",
1624 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1625 0>, ISA_MIPS1_NOT_32R6_64R6;
1626 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1627 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1628 InvertedImOperand:$imm), 0>;
1629 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1630 InvertedImOperand:$imm), 0>;
1631 def : MipsInstAlias<"sra $rd, $rt, $rs",
1632 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1633 def : MipsInstAlias<"srl $rd, $rt, $rs",
1634 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1635 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1636 def : MipsInstAlias<"sync",
1637 (SYNC 0), 1>, ISA_MIPS2;
1638 //===----------------------------------------------------------------------===//
1639 // Assembler Pseudo Instructions
1640 //===----------------------------------------------------------------------===//
1642 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1643 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1644 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1645 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1647 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1648 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1649 !strconcat(instr_asm, "\t$rt, $addr")> ;
1650 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1652 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1653 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1654 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1655 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1657 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1659 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1662 //===----------------------------------------------------------------------===//
1663 // Arbitrary patterns that map to one or more instructions
1664 //===----------------------------------------------------------------------===//
1666 // Load/store pattern templates.
1667 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1668 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1670 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1671 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1674 let AdditionalPredicates = [NotInMicroMips] in {
1675 def : MipsPat<(i32 immSExt16:$in),
1676 (ADDiu ZERO, imm:$in)>;
1677 def : MipsPat<(i32 immZExt16:$in),
1678 (ORi ZERO, imm:$in)>;
1680 def : MipsPat<(i32 immLow16Zero:$in),
1681 (LUi (HI16 imm:$in))>;
1683 // Arbitrary immediates
1684 def : MipsPat<(i32 imm:$imm),
1685 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1687 // Carry MipsPatterns
1688 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1689 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1690 let AdditionalPredicates = [NotDSP] in {
1691 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1692 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1693 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1694 (ADDiu GPR32:$src, imm:$imm)>;
1697 // Support multiplication for pre-Mips32 targets that don't have
1698 // the MUL instruction.
1699 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1700 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1701 ISA_MIPS1_NOT_32R6_64R6;
1704 def : MipsPat<(MipsSync (i32 immz)),
1705 (SYNC 0)>, ISA_MIPS2;
1708 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1709 (JAL tglobaladdr:$dst)>;
1710 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1711 (JAL texternalsym:$dst)>;
1712 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1713 // (JALR GPR32:$dst)>;
1716 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1717 (TAILCALL tglobaladdr:$dst)>;
1718 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1719 (TAILCALL texternalsym:$dst)>;
1721 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1722 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1723 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1724 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1725 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1726 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1728 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1729 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1730 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1731 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1732 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1733 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1735 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1736 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1737 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1738 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1739 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1740 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1741 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1742 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1743 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1744 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1747 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1748 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1749 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1750 (ADDiu GPR32:$gp, tconstpool:$in)>;
1753 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1754 MipsPat<(MipsWrapper RC:$gp, node:$in),
1755 (ADDiuOp RC:$gp, node:$in)>;
1757 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1758 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1759 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1760 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1761 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1762 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1764 // Mips does not have "not", so we expand our way
1765 def : MipsPat<(not GPR32:$in),
1766 (NOR GPR32Opnd:$in, ZERO)>;
1769 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1770 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1771 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1774 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1777 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1778 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1779 Instruction SLTiuOp, Register ZEROReg> {
1780 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1781 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1782 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1783 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1785 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1786 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1787 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1788 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1789 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1790 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1791 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1792 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1793 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1794 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1795 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1796 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1798 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1799 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1800 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1801 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1803 def : MipsPat<(brcond RC:$cond, bb:$dst),
1804 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1807 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1809 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1810 (BLEZ i32:$lhs, bb:$dst)>;
1811 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1812 (BGEZ i32:$lhs, bb:$dst)>;
1815 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1816 Instruction SLTuOp, Register ZEROReg> {
1817 def : MipsPat<(seteq RC:$lhs, 0),
1818 (SLTiuOp RC:$lhs, 1)>;
1819 def : MipsPat<(setne RC:$lhs, 0),
1820 (SLTuOp ZEROReg, RC:$lhs)>;
1821 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1822 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1823 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1824 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1827 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1828 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1829 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1830 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1831 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1834 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1835 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1836 (SLTOp RC:$rhs, RC:$lhs)>;
1837 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1838 (SLTuOp RC:$rhs, RC:$lhs)>;
1841 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1842 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1843 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1844 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1845 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1848 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1849 Instruction SLTiuOp> {
1850 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1851 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1852 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1853 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1856 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1857 defm : SetlePats<GPR32, SLT, SLTu>;
1858 defm : SetgtPats<GPR32, SLT, SLTu>;
1859 defm : SetgePats<GPR32, SLT, SLTu>;
1860 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1863 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1865 // Load halfword/word patterns.
1866 let AddedComplexity = 40 in {
1867 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1868 def : LoadRegImmPat<LH, i32, sextloadi16>;
1869 let AdditionalPredicates = [NotInMicroMips] in {
1870 def : LoadRegImmPat<LW, i32, load>;
1874 //===----------------------------------------------------------------------===//
1875 // Floating Point Support
1876 //===----------------------------------------------------------------------===//
1878 include "MipsInstrFPU.td"
1879 include "Mips64InstrInfo.td"
1880 include "MipsCondMov.td"
1882 include "Mips32r6InstrInfo.td"
1883 include "Mips64r6InstrInfo.td"
1888 include "Mips16InstrFormats.td"
1889 include "Mips16InstrInfo.td"
1892 include "MipsDSPInstrFormats.td"
1893 include "MipsDSPInstrInfo.td"
1896 include "MipsMSAInstrFormats.td"
1897 include "MipsMSAInstrInfo.td"
1900 include "MicroMipsInstrFormats.td"
1901 include "MicroMipsInstrInfo.td"
1902 include "MicroMipsInstrFPU.td"