1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
170 AssemblerPredicate<"FeatureGP64Bit">;
171 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
172 AssemblerPredicate<"!FeatureGP64Bit">;
173 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
174 AssemblerPredicate<"FeatureMips64">;
175 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
176 AssemblerPredicate<"FeatureMips64r2">;
177 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
178 AssemblerPredicate<"FeatureMips64r6">;
179 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
180 AssemblerPredicate<"FeatureN64">;
181 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
182 AssemblerPredicate<"FeatureMips16">;
183 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
184 AssemblerPredicate<"FeatureCnMips">;
185 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
186 AssemblerPredicate<"FeatureMips32">;
187 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
188 AssemblerPredicate<"FeatureMips32">;
189 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
190 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
191 AssemblerPredicate<"!FeatureMips16">;
192 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
193 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
194 AssemblerPredicate<"FeatureMicroMips">;
195 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
196 AssemblerPredicate<"!FeatureMicroMips">;
197 def IsLE : Predicate<"Subtarget.isLittle()">;
198 def IsBE : Predicate<"!Subtarget.isLittle()">;
199 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
201 //===----------------------------------------------------------------------===//
202 // Mips GPR size adjectives.
203 // They are mutually exclusive.
204 //===----------------------------------------------------------------------===//
206 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
207 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
209 //===----------------------------------------------------------------------===//
210 // Mips ISA/ASE membership and instruction group membership adjectives.
211 // They are mutually exclusive.
212 //===----------------------------------------------------------------------===//
214 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
215 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
216 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
217 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
218 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
219 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
220 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
221 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
223 // The portions of MIPS-III that were also added to MIPS32
224 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
226 // The portions of MIPS-III that were also added to MIPS32
227 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
229 // The portions of MIPS-IV that were also added to MIPS32
230 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
232 // The portions of MIPS-IV that were also added to MIPS32R2
233 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
235 // The portions of MIPS-V that were also added to MIPS32R2
236 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
238 //===----------------------------------------------------------------------===//
240 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
241 let EncodingPredicates = [HasStdEnc];
244 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
245 InstAlias<Asm, Result, Emit>, PredicateControl;
248 bit isCommutable = 1;
265 bit isTerminator = 1;
268 bit hasExtraSrcRegAllocReq = 1;
269 bit isCodeGenOnly = 1;
272 class IsAsCheapAsAMove {
273 bit isAsCheapAsAMove = 1;
276 class NeverHasSideEffects {
277 bit neverHasSideEffects = 1;
280 //===----------------------------------------------------------------------===//
281 // Instruction format superclass
282 //===----------------------------------------------------------------------===//
284 include "MipsInstrFormats.td"
286 //===----------------------------------------------------------------------===//
287 // Mips Operand, Complex Patterns and Transformations Definitions.
288 //===----------------------------------------------------------------------===//
290 def MipsJumpTargetAsmOperand : AsmOperandClass {
291 let Name = "JumpTarget";
292 let ParserMethod = "ParseJumpTarget";
293 let PredicateMethod = "isImm";
294 let RenderMethod = "addImmOperands";
297 // Instruction operand types
298 def jmptarget : Operand<OtherVT> {
299 let EncoderMethod = "getJumpTargetOpValue";
300 let ParserMatchClass = MipsJumpTargetAsmOperand;
302 def brtarget : Operand<OtherVT> {
303 let EncoderMethod = "getBranchTargetOpValue";
304 let OperandType = "OPERAND_PCREL";
305 let DecoderMethod = "DecodeBranchTarget";
306 let ParserMatchClass = MipsJumpTargetAsmOperand;
308 def calltarget : Operand<iPTR> {
309 let EncoderMethod = "getJumpTargetOpValue";
310 let ParserMatchClass = MipsJumpTargetAsmOperand;
313 def simm10 : Operand<i32>;
315 def simm16 : Operand<i32> {
316 let DecoderMethod= "DecodeSimm16";
319 def simm19_lsl2 : Operand<i32> {
320 let EncoderMethod = "getSimm19Lsl2Encoding";
321 let DecoderMethod = "DecodeSimm19Lsl2";
324 def simm20 : Operand<i32> {
327 def uimm20 : Operand<i32> {
330 def uimm10 : Operand<i32> {
333 def simm16_64 : Operand<i64> {
334 let DecoderMethod = "DecodeSimm16";
338 def uimmz : Operand<i32> {
339 let PrintMethod = "printUnsignedImm";
343 def uimm5 : Operand<i32> {
344 let PrintMethod = "printUnsignedImm";
347 def uimm6 : Operand<i32> {
348 let PrintMethod = "printUnsignedImm";
351 def uimm16 : Operand<i32> {
352 let PrintMethod = "printUnsignedImm";
355 def pcrel16 : Operand<i32> {
358 def MipsMemAsmOperand : AsmOperandClass {
360 let ParserMethod = "parseMemOperand";
363 def MipsInvertedImmoperand : AsmOperandClass {
365 let RenderMethod = "addImmOperands";
366 let ParserMethod = "parseInvNum";
369 def InvertedImOperand : Operand<i32> {
370 let ParserMatchClass = MipsInvertedImmoperand;
373 def InvertedImOperand64 : Operand<i64> {
374 let ParserMatchClass = MipsInvertedImmoperand;
377 class mem_generic : Operand<iPTR> {
378 let PrintMethod = "printMemOperand";
379 let MIOperandInfo = (ops ptr_rc, simm16);
380 let EncoderMethod = "getMemEncoding";
381 let ParserMatchClass = MipsMemAsmOperand;
382 let OperandType = "OPERAND_MEMORY";
386 def mem : mem_generic;
388 // MSA specific address operand
389 def mem_msa : mem_generic {
390 let MIOperandInfo = (ops ptr_rc, simm10);
391 let EncoderMethod = "getMSAMemEncoding";
394 def mem_ea : Operand<iPTR> {
395 let PrintMethod = "printMemOperandEA";
396 let MIOperandInfo = (ops ptr_rc, simm16);
397 let EncoderMethod = "getMemEncoding";
398 let OperandType = "OPERAND_MEMORY";
401 def PtrRC : Operand<iPTR> {
402 let MIOperandInfo = (ops ptr_rc);
403 let DecoderMethod = "DecodePtrRegisterClass";
404 let ParserMatchClass = GPR32AsmOperand;
407 // size operand of ext instruction
408 def size_ext : Operand<i32> {
409 let EncoderMethod = "getSizeExtEncoding";
410 let DecoderMethod = "DecodeExtSize";
413 // size operand of ins instruction
414 def size_ins : Operand<i32> {
415 let EncoderMethod = "getSizeInsEncoding";
416 let DecoderMethod = "DecodeInsSize";
419 // Transformation Function - get the lower 16 bits.
420 def LO16 : SDNodeXForm<imm, [{
421 return getImm(N, N->getZExtValue() & 0xFFFF);
424 // Transformation Function - get the higher 16 bits.
425 def HI16 : SDNodeXForm<imm, [{
426 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
430 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
432 // Node immediate is zero (e.g. insve.d)
433 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
435 // Node immediate fits as 16-bit sign extended on target immediate.
437 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
439 // Node immediate fits as 16-bit sign extended on target immediate.
441 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
443 // Node immediate fits as 15-bit sign extended on target immediate.
445 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
447 // Node immediate fits as 16-bit zero extended on target immediate.
448 // The LO16 param means that only the lower 16 bits of the node
449 // immediate are caught.
451 def immZExt16 : PatLeaf<(imm), [{
452 if (N->getValueType(0) == MVT::i32)
453 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
455 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
458 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
459 def immLow16Zero : PatLeaf<(imm), [{
460 int64_t Val = N->getSExtValue();
461 return isInt<32>(Val) && !(Val & 0xffff);
464 // shamt field must fit in 5 bits.
465 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
467 // True if (N + 1) fits in 16-bit field.
468 def immSExt16Plus1 : PatLeaf<(imm), [{
469 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
472 // Mips Address Mode! SDNode frameindex could possibily be a match
473 // since load and store instructions from stack used it.
475 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
478 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
481 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
484 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
486 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
488 //===----------------------------------------------------------------------===//
489 // Instructions specific format
490 //===----------------------------------------------------------------------===//
492 // Arithmetic and logical instructions with 3 register operands.
493 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
494 InstrItinClass Itin = NoItinerary,
495 SDPatternOperator OpNode = null_frag>:
496 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
497 !strconcat(opstr, "\t$rd, $rs, $rt"),
498 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
499 let isCommutable = isComm;
500 let isReMaterializable = 1;
501 let TwoOperandAliasConstraint = "$rd = $rs";
504 // Arithmetic and logical instructions with 2 register operands.
505 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
506 InstrItinClass Itin = NoItinerary,
507 SDPatternOperator imm_type = null_frag,
508 SDPatternOperator OpNode = null_frag> :
509 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
510 !strconcat(opstr, "\t$rt, $rs, $imm16"),
511 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
513 let isReMaterializable = 1;
514 let TwoOperandAliasConstraint = "$rs = $rt";
517 // Arithmetic Multiply ADD/SUB
518 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
519 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
520 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
521 let Defs = [HI0, LO0];
522 let Uses = [HI0, LO0];
523 let isCommutable = isComm;
527 class LogicNOR<string opstr, RegisterOperand RO>:
528 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
529 !strconcat(opstr, "\t$rd, $rs, $rt"),
530 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
531 let isCommutable = 1;
535 class shift_rotate_imm<string opstr, Operand ImmOpnd,
536 RegisterOperand RO, InstrItinClass itin,
537 SDPatternOperator OpNode = null_frag,
538 SDPatternOperator PF = null_frag> :
539 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
540 !strconcat(opstr, "\t$rd, $rt, $shamt"),
541 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
542 let TwoOperandAliasConstraint = "$rt = $rd";
545 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
546 SDPatternOperator OpNode = null_frag>:
547 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
548 !strconcat(opstr, "\t$rd, $rt, $rs"),
549 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
552 // Load Upper Imediate
553 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
554 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
555 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
556 let neverHasSideEffects = 1;
557 let isReMaterializable = 1;
561 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
562 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
563 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
564 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
565 let DecoderMethod = "DecodeMem";
566 let canFoldAsLoad = 1;
570 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
571 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
572 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
573 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
574 let DecoderMethod = "DecodeMem";
578 // Load/Store Left/Right
579 let canFoldAsLoad = 1 in
580 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
581 InstrItinClass Itin> :
582 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
583 !strconcat(opstr, "\t$rt, $addr"),
584 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
585 let DecoderMethod = "DecodeMem";
586 string Constraints = "$src = $rt";
589 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
590 InstrItinClass Itin> :
591 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
592 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
593 let DecoderMethod = "DecodeMem";
596 // Conditional Branch
597 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
598 RegisterOperand RO> :
599 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
600 !strconcat(opstr, "\t$rs, $rt, $offset"),
601 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
604 let isTerminator = 1;
605 let hasDelaySlot = 1;
609 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
610 RegisterOperand RO> :
611 InstSE<(outs), (ins RO:$rs, opnd:$offset),
612 !strconcat(opstr, "\t$rs, $offset"),
613 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
616 let isTerminator = 1;
617 let hasDelaySlot = 1;
622 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
623 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
624 !strconcat(opstr, "\t$rd, $rs, $rt"),
625 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
626 II_SLT_SLTU, FrmR, opstr>;
628 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
630 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
631 !strconcat(opstr, "\t$rt, $rs, $imm16"),
632 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
633 II_SLTI_SLTIU, FrmI, opstr>;
636 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
637 SDPatternOperator targetoperator, string bopstr> :
638 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
639 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
642 let hasDelaySlot = 1;
643 let DecoderMethod = "DecodeJumpTarget";
647 // Unconditional branch
648 class UncondBranch<Instruction BEQInst> :
649 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
650 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
652 let isTerminator = 1;
654 let hasDelaySlot = 1;
655 let AdditionalPredicates = [RelocPIC];
659 // Base class for indirect branch and return instruction classes.
660 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
661 class JumpFR<string opstr, RegisterOperand RO,
662 SDPatternOperator operator = null_frag>:
663 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
667 class IndirectBranch<string opstr, RegisterOperand RO> :
668 JumpFR<opstr, RO, brind> {
670 let isIndirectBranch = 1;
673 // Return instruction
674 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
676 let isCodeGenOnly = 1;
678 let hasExtraSrcRegAllocReq = 1;
681 // Jump and Link (Call)
682 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
683 class JumpLink<string opstr, DAGOperand opnd> :
684 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
685 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
686 let DecoderMethod = "DecodeJumpTarget";
689 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
690 Register RetReg, RegisterOperand ResRO = RO>:
691 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
692 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
694 class JumpLinkReg<string opstr, RegisterOperand RO>:
695 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
698 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
699 InstSE<(outs), (ins RO:$rs, opnd:$offset),
700 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
704 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
705 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
706 class TailCall<Instruction JumpInst> :
707 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
708 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
710 class TailCallReg<RegisterOperand RO, Instruction JRInst,
711 RegisterOperand ResRO = RO> :
712 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
713 PseudoInstExpansion<(JRInst ResRO:$rs)>;
716 class BAL_BR_Pseudo<Instruction RealInst> :
717 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
718 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
720 let isTerminator = 1;
722 let hasDelaySlot = 1;
727 class SYS_FT<string opstr> :
728 InstSE<(outs), (ins uimm20:$code_),
729 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
731 class BRK_FT<string opstr> :
732 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
733 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
737 class ER_FT<string opstr> :
738 InstSE<(outs), (ins),
739 opstr, [], NoItinerary, FrmOther, opstr>;
742 class DEI_FT<string opstr, RegisterOperand RO> :
743 InstSE<(outs RO:$rt), (ins),
744 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
747 class WAIT_FT<string opstr> :
748 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
751 let hasSideEffects = 1 in
752 class SYNC_FT<string opstr> :
753 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
754 NoItinerary, FrmOther, opstr>;
756 let hasSideEffects = 1 in
757 class TEQ_FT<string opstr, RegisterOperand RO> :
758 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
759 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
762 class TEQI_FT<string opstr, RegisterOperand RO> :
763 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
764 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
766 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
767 list<Register> DefRegs> :
768 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
770 let isCommutable = 1;
772 let neverHasSideEffects = 1;
775 // Pseudo multiply/divide instruction with explicit accumulator register
777 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
778 SDPatternOperator OpNode, InstrItinClass Itin,
779 bit IsComm = 1, bit HasSideEffects = 0,
780 bit UsesCustomInserter = 0> :
781 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
782 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
783 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
784 let isCommutable = IsComm;
785 let hasSideEffects = HasSideEffects;
786 let usesCustomInserter = UsesCustomInserter;
789 // Pseudo multiply add/sub instruction with explicit accumulator register
791 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
793 : PseudoSE<(outs ACC64:$ac),
794 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
796 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
798 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
799 string Constraints = "$acin = $ac";
802 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
803 list<Register> DefRegs> :
804 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
805 [], itin, FrmR, opstr> {
810 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
811 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
812 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
814 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
815 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
818 let neverHasSideEffects = 1;
821 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
822 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
823 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
826 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
827 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
830 let neverHasSideEffects = 1;
833 class EffectiveAddress<string opstr, RegisterOperand RO> :
834 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
835 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
836 !strconcat(opstr, "_lea")> {
837 let isCodeGenOnly = 1;
838 let DecoderMethod = "DecodeMem";
841 // Count Leading Ones/Zeros in Word
842 class CountLeading0<string opstr, RegisterOperand RO>:
843 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
844 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
846 class CountLeading1<string opstr, RegisterOperand RO>:
847 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
848 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
850 // Sign Extend in Register.
851 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
852 InstrItinClass itin> :
853 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
854 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
857 class SubwordSwap<string opstr, RegisterOperand RO>:
858 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
859 NoItinerary, FrmR, opstr> {
860 let neverHasSideEffects = 1;
864 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
865 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
869 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
870 SDPatternOperator Op = null_frag>:
871 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
872 !strconcat(opstr, " $rt, $rs, $pos, $size"),
873 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
874 FrmR, opstr>, ISA_MIPS32R2;
876 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
877 SDPatternOperator Op = null_frag>:
878 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
879 !strconcat(opstr, " $rt, $rs, $pos, $size"),
880 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
881 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
882 let Constraints = "$src = $rt";
885 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
886 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
887 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
888 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
890 // Atomic Compare & Swap.
891 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
892 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
893 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
895 class LLBase<string opstr, RegisterOperand RO> :
896 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
897 [], NoItinerary, FrmI> {
898 let DecoderMethod = "DecodeMem";
902 class SCBase<string opstr, RegisterOperand RO> :
903 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
904 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
905 let DecoderMethod = "DecodeMem";
907 let Constraints = "$rt = $dst";
910 class MFC3OP<string asmstr, RegisterOperand RO> :
911 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
912 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
914 class TrapBase<Instruction RealInst>
915 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
916 PseudoInstExpansion<(RealInst 0, 0)> {
918 let isTerminator = 1;
919 let isCodeGenOnly = 1;
922 //===----------------------------------------------------------------------===//
923 // Pseudo instructions
924 //===----------------------------------------------------------------------===//
927 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
928 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
930 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
931 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
932 [(callseq_start timm:$amt)]>;
933 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
934 [(callseq_end timm:$amt1, timm:$amt2)]>;
937 let usesCustomInserter = 1 in {
938 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
939 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
940 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
941 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
942 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
943 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
944 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
945 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
946 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
947 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
948 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
949 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
950 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
951 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
952 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
953 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
954 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
955 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
957 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
958 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
959 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
961 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
962 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
963 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
966 /// Pseudo instructions for loading and storing accumulator registers.
967 let isPseudo = 1, isCodeGenOnly = 1 in {
968 def LOAD_ACC64 : Load<"", ACC64>;
969 def STORE_ACC64 : Store<"", ACC64>;
972 // We need these two pseudo instructions to avoid offset calculation for long
973 // branches. See the comment in file MipsLongBranch.cpp for detailed
976 // Expands to: lui $dst, %hi($tgt - $baltgt)
977 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
978 (ins brtarget:$tgt, brtarget:$baltgt), []>;
980 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
981 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
982 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
984 //===----------------------------------------------------------------------===//
985 // Instruction definition
986 //===----------------------------------------------------------------------===//
987 //===----------------------------------------------------------------------===//
988 // MipsI Instructions
989 //===----------------------------------------------------------------------===//
991 /// Arithmetic Instructions (ALU Immediate)
992 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
994 ADDI_FM<0x9>, IsAsCheapAsAMove;
995 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
996 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
998 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1000 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1003 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1006 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1009 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1011 /// Arithmetic Instructions (3-Operand, R-Type)
1012 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1014 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1016 let Defs = [HI0, LO0] in
1017 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1018 ADD_FM<0x1c, 2>, ISA_MIPS32;
1019 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1020 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1021 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1022 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1023 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1025 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1027 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1029 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1031 /// Shift Instructions
1032 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1033 immZExt5>, SRA_FM<0, 0>;
1034 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1035 immZExt5>, SRA_FM<2, 0>;
1036 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1037 immZExt5>, SRA_FM<3, 0>;
1038 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1040 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1042 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1045 // Rotate Instructions
1046 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1048 SRA_FM<2, 1>, ISA_MIPS32R2;
1049 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1050 SRLV_FM<6, 1>, ISA_MIPS32R2;
1052 /// Load and Store Instructions
1054 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1055 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1057 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1059 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1060 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1062 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1063 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1064 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1066 /// load/store left/right
1067 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1068 AdditionalPredicates = [NotInMicroMips] in {
1069 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1070 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1071 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1072 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1075 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1076 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1077 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1078 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1079 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1080 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1081 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1083 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>, ISA_MIPS2;
1084 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>, ISA_MIPS2;
1085 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>, ISA_MIPS2;
1086 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>, ISA_MIPS2;
1087 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>, ISA_MIPS2;
1088 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>, ISA_MIPS2;
1090 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1091 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1092 def TRAP : TrapBase<BREAK>;
1094 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1095 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1097 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1098 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1100 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1101 AdditionalPredicates = [NotInMicroMips] in {
1102 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1104 /// Load-linked, Store-conditional
1105 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1106 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1109 /// Jump and Branch Instructions
1110 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1111 AdditionalRequires<[RelocStatic]>, IsBranch;
1112 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1113 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1114 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1115 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1117 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1119 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1121 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1123 def B : UncondBranch<BEQ>;
1125 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1126 let AdditionalPredicates = [NotInMicroMips] in {
1127 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1128 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1130 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1131 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1132 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1133 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1134 def TAILCALL : TailCall<J>;
1135 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1137 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1139 // Exception handling related node and instructions.
1140 // The conversion sequence is:
1141 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1142 // MIPSeh_return -> (stack change + indirect branch)
1144 // MIPSeh_return takes the place of regular return instruction
1145 // but takes two arguments (V1, V0) which are used for storing
1146 // the offset and return address respectively.
1147 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1149 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1150 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1152 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1153 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1154 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1155 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1157 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1160 /// Multiply and Divide Instructions.
1161 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1163 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1165 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1167 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1170 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1171 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1172 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1173 AdditionalPredicates = [NotInMicroMips] in {
1174 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1175 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1178 /// Sign Ext In Register Instructions.
1179 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1180 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1181 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1182 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1185 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1186 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1188 /// Word Swap Bytes Within Halfwords
1189 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1192 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1194 // FrameIndexes are legalized when they are operands from load/store
1195 // instructions. The same not happens for stack address copies, so an
1196 // add op with mem ComplexPattern is used and the stack address copy
1197 // can be matched. It's similar to Sparc LEA_ADDRi
1198 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1201 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>, ISA_MIPS32;
1202 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>, ISA_MIPS32;
1203 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>, ISA_MIPS32;
1204 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>, ISA_MIPS32;
1206 let AdditionalPredicates = [NotDSP] in {
1207 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1208 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1209 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1210 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1211 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1212 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1213 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1214 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1215 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1218 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1220 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1223 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1225 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1226 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1228 /// Move Control Registers From/To CPU Registers
1229 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1230 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1231 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1232 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1234 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1236 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1237 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1238 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1240 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1242 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1243 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1244 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1245 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1247 //===----------------------------------------------------------------------===//
1248 // Instruction aliases
1249 //===----------------------------------------------------------------------===//
1250 def : MipsInstAlias<"move $dst, $src",
1251 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1253 let AdditionalPredicates = [NotInMicroMips];
1255 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1256 def : MipsInstAlias<"addu $rs, $rt, $imm",
1257 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1258 def : MipsInstAlias<"add $rs, $rt, $imm",
1259 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1260 def : MipsInstAlias<"and $rs, $rt, $imm",
1261 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1262 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1263 let Predicates = [NotInMicroMips] in {
1264 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1266 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1267 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1268 def : MipsInstAlias<"not $rt, $rs",
1269 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1270 def : MipsInstAlias<"neg $rt, $rs",
1271 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1272 def : MipsInstAlias<"negu $rt",
1273 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1274 def : MipsInstAlias<"negu $rt, $rs",
1275 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1276 def : MipsInstAlias<"slt $rs, $rt, $imm",
1277 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1278 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1279 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1280 def : MipsInstAlias<"xor $rs, $rt, $imm",
1281 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1282 def : MipsInstAlias<"or $rs, $rt, $imm",
1283 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1284 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1285 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1286 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1287 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1288 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1289 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1290 def : MipsInstAlias<"bnez $rs,$offset",
1291 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1292 def : MipsInstAlias<"beqz $rs,$offset",
1293 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1294 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1296 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1297 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1298 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1299 def : MipsInstAlias<"di", (DI ZERO), 1>;
1301 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1302 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1303 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1305 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1306 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1308 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1309 def : MipsInstAlias<"sll $rd, $rt, $rs",
1310 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1311 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1312 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1313 InvertedImOperand:$imm)>;
1314 def : MipsInstAlias<"sub $rs, $imm",
1315 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1317 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1318 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1319 InvertedImOperand:$imm)>;
1320 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1321 InvertedImOperand:$imm), 0>;
1322 def : MipsInstAlias<"sra $rd, $rt, $rs",
1323 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1324 def : MipsInstAlias<"srl $rd, $rt, $rs",
1325 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1326 //===----------------------------------------------------------------------===//
1327 // Assembler Pseudo Instructions
1328 //===----------------------------------------------------------------------===//
1330 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1331 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1332 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1333 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1335 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1336 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1337 !strconcat(instr_asm, "\t$rt, $addr")> ;
1338 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1340 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1341 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1342 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1343 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1345 //===----------------------------------------------------------------------===//
1346 // Arbitrary patterns that map to one or more instructions
1347 //===----------------------------------------------------------------------===//
1349 // Load/store pattern templates.
1350 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1351 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1353 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1354 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1357 def : MipsPat<(i32 immSExt16:$in),
1358 (ADDiu ZERO, imm:$in)>;
1359 def : MipsPat<(i32 immZExt16:$in),
1360 (ORi ZERO, imm:$in)>;
1361 def : MipsPat<(i32 immLow16Zero:$in),
1362 (LUi (HI16 imm:$in))>;
1364 // Arbitrary immediates
1365 def : MipsPat<(i32 imm:$imm),
1366 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1368 // Carry MipsPatterns
1369 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1370 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1371 let AdditionalPredicates = [NotDSP] in {
1372 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1373 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1374 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1375 (ADDiu GPR32:$src, imm:$imm)>;
1379 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1380 (JAL tglobaladdr:$dst)>;
1381 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1382 (JAL texternalsym:$dst)>;
1383 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1384 // (JALR GPR32:$dst)>;
1387 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1388 (TAILCALL tglobaladdr:$dst)>;
1389 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1390 (TAILCALL texternalsym:$dst)>;
1392 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1393 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1394 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1395 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1396 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1397 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1399 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1400 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1401 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1402 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1403 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1404 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1406 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1407 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1408 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1409 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1410 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1411 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1412 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1413 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1414 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1415 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1418 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1419 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1420 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1421 (ADDiu GPR32:$gp, tconstpool:$in)>;
1424 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1425 MipsPat<(MipsWrapper RC:$gp, node:$in),
1426 (ADDiuOp RC:$gp, node:$in)>;
1428 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1429 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1430 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1431 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1432 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1433 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1435 // Mips does not have "not", so we expand our way
1436 def : MipsPat<(not GPR32:$in),
1437 (NOR GPR32Opnd:$in, ZERO)>;
1440 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1441 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1442 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1445 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1448 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1449 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1450 Instruction SLTiuOp, Register ZEROReg> {
1451 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1452 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1453 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1454 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1456 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1457 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1458 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1459 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1460 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1461 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1462 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1463 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1464 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1465 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1466 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1467 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1469 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1470 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1471 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1472 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1474 def : MipsPat<(brcond RC:$cond, bb:$dst),
1475 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1478 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1480 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1481 (BLEZ i32:$lhs, bb:$dst)>;
1482 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1483 (BGEZ i32:$lhs, bb:$dst)>;
1486 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1487 Instruction SLTuOp, Register ZEROReg> {
1488 def : MipsPat<(seteq RC:$lhs, 0),
1489 (SLTiuOp RC:$lhs, 1)>;
1490 def : MipsPat<(setne RC:$lhs, 0),
1491 (SLTuOp ZEROReg, RC:$lhs)>;
1492 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1493 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1494 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1495 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1498 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1499 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1500 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1501 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1502 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1505 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1506 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1507 (SLTOp RC:$rhs, RC:$lhs)>;
1508 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1509 (SLTuOp RC:$rhs, RC:$lhs)>;
1512 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1513 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1514 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1515 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1516 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1519 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1520 Instruction SLTiuOp> {
1521 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1522 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1523 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1524 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1527 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1528 defm : SetlePats<GPR32, SLT, SLTu>;
1529 defm : SetgtPats<GPR32, SLT, SLTu>;
1530 defm : SetgePats<GPR32, SLT, SLTu>;
1531 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1534 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1536 // Load halfword/word patterns.
1537 let AddedComplexity = 40 in {
1538 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1539 def : LoadRegImmPat<LH, i32, sextloadi16>;
1540 def : LoadRegImmPat<LW, i32, load>;
1543 //===----------------------------------------------------------------------===//
1544 // Floating Point Support
1545 //===----------------------------------------------------------------------===//
1547 include "MipsInstrFPU.td"
1548 include "Mips64InstrInfo.td"
1549 include "MipsCondMov.td"
1551 include "Mips32r6InstrInfo.td"
1552 include "Mips64r6InstrInfo.td"
1557 include "Mips16InstrFormats.td"
1558 include "Mips16InstrInfo.td"
1561 include "MipsDSPInstrFormats.td"
1562 include "MipsDSPInstrInfo.td"
1565 include "MipsMSAInstrFormats.td"
1566 include "MipsMSAInstrInfo.td"
1569 include "MicroMipsInstrFormats.td"
1570 include "MicroMipsInstrInfo.td"
1571 include "MicroMipsInstrFPU.td"