1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
20 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
21 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
26 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
27 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
28 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
31 def SDT_MipsDivRem : SDTypeProfile<0, 2,
35 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
37 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
39 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
41 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
43 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
47 def SDTMipsLoadLR : SDTypeProfile<1, 2,
48 [SDTCisInt<0>, SDTCisPtrTy<1>,
52 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 // Hi and Lo nodes are used to handle global addresses. Used on
57 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
58 // static model. (nothing to do with Mips Registers Hi and Lo)
59 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
60 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
61 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
63 // TlsGd node is used to handle General Dynamic TLS
64 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
66 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
67 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
68 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
71 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
74 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
84 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
85 [SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
88 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
89 [SDNPOptInGlue, SDNPOutGlue]>;
90 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
91 [SDNPOptInGlue, SDNPOutGlue]>;
94 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
96 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
99 // Target constant nodes that are not part of any isel patterns and remain
100 // unchanged can cause instructions with illegal operands to be emitted.
101 // Wrapper node patterns give the instruction selector a chance to replace
102 // target constant nodes that would otherwise remain unchanged with ADDiu
103 // nodes. Without these wrapper node patterns, the following conditional move
104 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
106 // movn %got(d)($gp), %got(c)($gp), $4
107 // This instruction is illegal since movn can take only register operands.
109 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
111 // Pointer to dynamically allocated stack area.
112 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
113 [SDNPHasChain, SDNPInGlue]>;
115 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
117 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
118 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
120 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
123 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
124 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
126 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
127 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
128 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 //===----------------------------------------------------------------------===//
138 // Mips Instruction Predicate Definitions.
139 //===----------------------------------------------------------------------===//
140 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
141 AssemblerPredicate<"FeatureSEInReg">;
142 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
143 AssemblerPredicate<"FeatureBitCount">;
144 def HasSwap : Predicate<"Subtarget.hasSwap()">,
145 AssemblerPredicate<"FeatureSwap">;
146 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
147 AssemblerPredicate<"FeatureCondMov">;
148 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
149 AssemblerPredicate<"FeatureMips32">;
150 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
151 AssemblerPredicate<"FeatureMips32r2">;
152 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
153 AssemblerPredicate<"FeatureMips64">;
154 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
155 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
156 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
157 AssemblerPredicate<"!FeatureMips64">;
158 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
159 AssemblerPredicate<"FeatureMips64r2">;
160 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
161 AssemblerPredicate<"FeatureN64">;
162 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
163 AssemblerPredicate<"!FeatureN64">;
164 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
165 AssemblerPredicate<"FeatureMips16">;
166 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
167 AssemblerPredicate<"FeatureMips32">;
168 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
169 AssemblerPredicate<"FeatureMips32">;
170 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
171 AssemblerPredicate<"FeatureMips32">;
172 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
173 AssemblerPredicate<"!FeatureMips16">;
175 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
176 let Predicates = [HasStandardEncoding];
179 //===----------------------------------------------------------------------===//
180 // Instruction format superclass
181 //===----------------------------------------------------------------------===//
183 include "MipsInstrFormats.td"
185 //===----------------------------------------------------------------------===//
186 // Mips Operand, Complex Patterns and Transformations Definitions.
187 //===----------------------------------------------------------------------===//
189 // Instruction operand types
190 def jmptarget : Operand<OtherVT> {
191 let EncoderMethod = "getJumpTargetOpValue";
193 def brtarget : Operand<OtherVT> {
194 let EncoderMethod = "getBranchTargetOpValue";
195 let OperandType = "OPERAND_PCREL";
196 let DecoderMethod = "DecodeBranchTarget";
198 def calltarget : Operand<iPTR> {
199 let EncoderMethod = "getJumpTargetOpValue";
201 def calltarget64: Operand<i64>;
202 def simm16 : Operand<i32> {
203 let DecoderMethod= "DecodeSimm16";
205 def simm16_64 : Operand<i64>;
206 def shamt : Operand<i32>;
209 def uimm16 : Operand<i32> {
210 let PrintMethod = "printUnsignedImm";
214 def mem : Operand<i32> {
215 let PrintMethod = "printMemOperand";
216 let MIOperandInfo = (ops CPURegs, simm16);
217 let EncoderMethod = "getMemEncoding";
220 def mem64 : Operand<i64> {
221 let PrintMethod = "printMemOperand";
222 let MIOperandInfo = (ops CPU64Regs, simm16_64);
225 def mem_ea : Operand<i32> {
226 let PrintMethod = "printMemOperandEA";
227 let MIOperandInfo = (ops CPURegs, simm16);
228 let EncoderMethod = "getMemEncoding";
231 def mem_ea_64 : Operand<i64> {
232 let PrintMethod = "printMemOperandEA";
233 let MIOperandInfo = (ops CPU64Regs, simm16_64);
234 let EncoderMethod = "getMemEncoding";
237 // size operand of ext instruction
238 def size_ext : Operand<i32> {
239 let EncoderMethod = "getSizeExtEncoding";
240 let DecoderMethod = "DecodeExtSize";
243 // size operand of ins instruction
244 def size_ins : Operand<i32> {
245 let EncoderMethod = "getSizeInsEncoding";
246 let DecoderMethod = "DecodeInsSize";
249 // Transformation Function - get the lower 16 bits.
250 def LO16 : SDNodeXForm<imm, [{
251 return getImm(N, N->getZExtValue() & 0xFFFF);
254 // Transformation Function - get the higher 16 bits.
255 def HI16 : SDNodeXForm<imm, [{
256 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
259 // Node immediate fits as 16-bit sign extended on target immediate.
261 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
263 // Node immediate fits as 16-bit zero extended on target immediate.
264 // The LO16 param means that only the lower 16 bits of the node
265 // immediate are caught.
267 def immZExt16 : PatLeaf<(imm), [{
268 if (N->getValueType(0) == MVT::i32)
269 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
271 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
274 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
275 def immLow16Zero : PatLeaf<(imm), [{
276 int64_t Val = N->getSExtValue();
277 return isInt<32>(Val) && !(Val & 0xffff);
280 // shamt field must fit in 5 bits.
281 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
283 // Mips Address Mode! SDNode frameindex could possibily be a match
284 // since load and store instructions from stack used it.
286 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
288 //===----------------------------------------------------------------------===//
289 // Pattern fragment for load/store
290 //===----------------------------------------------------------------------===//
291 class UnalignedLoad<PatFrag Node> :
292 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
293 LoadSDNode *LD = cast<LoadSDNode>(N);
294 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
297 class AlignedLoad<PatFrag Node> :
298 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
299 LoadSDNode *LD = cast<LoadSDNode>(N);
300 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
303 class UnalignedStore<PatFrag Node> :
304 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
305 StoreSDNode *SD = cast<StoreSDNode>(N);
306 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
309 class AlignedStore<PatFrag Node> :
310 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
311 StoreSDNode *SD = cast<StoreSDNode>(N);
312 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
315 // Load/Store PatFrags.
316 def sextloadi16_a : AlignedLoad<sextloadi16>;
317 def zextloadi16_a : AlignedLoad<zextloadi16>;
318 def extloadi16_a : AlignedLoad<extloadi16>;
319 def load_a : AlignedLoad<load>;
320 def sextloadi32_a : AlignedLoad<sextloadi32>;
321 def zextloadi32_a : AlignedLoad<zextloadi32>;
322 def extloadi32_a : AlignedLoad<extloadi32>;
323 def truncstorei16_a : AlignedStore<truncstorei16>;
324 def store_a : AlignedStore<store>;
325 def truncstorei32_a : AlignedStore<truncstorei32>;
326 def sextloadi16_u : UnalignedLoad<sextloadi16>;
327 def zextloadi16_u : UnalignedLoad<zextloadi16>;
328 def extloadi16_u : UnalignedLoad<extloadi16>;
329 def load_u : UnalignedLoad<load>;
330 def sextloadi32_u : UnalignedLoad<sextloadi32>;
331 def zextloadi32_u : UnalignedLoad<zextloadi32>;
332 def extloadi32_u : UnalignedLoad<extloadi32>;
333 def truncstorei16_u : UnalignedStore<truncstorei16>;
334 def store_u : UnalignedStore<store>;
335 def truncstorei32_u : UnalignedStore<truncstorei32>;
337 //===----------------------------------------------------------------------===//
338 // Instructions specific format
339 //===----------------------------------------------------------------------===//
341 // Arithmetic and logical instructions with 3 register operands.
342 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
343 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
344 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
345 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
346 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
348 let isCommutable = isComm;
349 let isReMaterializable = 1;
352 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
353 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
354 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
355 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
357 let isCommutable = isComm;
360 // Arithmetic and logical instructions with 2 register operands.
361 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
362 Operand Od, PatLeaf imm_type, RegisterClass RC> :
363 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
364 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
365 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
366 let isReMaterializable = 1;
369 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
370 Operand Od, PatLeaf imm_type, RegisterClass RC> :
371 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
372 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
374 // Arithmetic Multiply ADD/SUB
375 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
376 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
377 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
378 !strconcat(instr_asm, "\t$rs, $rt"),
379 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
382 let isCommutable = isComm;
386 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
387 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
388 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
389 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
391 let isCommutable = 1;
395 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
396 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
398 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
399 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
400 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
404 // 32-bit shift instructions.
405 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
407 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
409 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
410 SDNode OpNode, RegisterClass RC>:
411 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
412 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
413 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
414 let shamt = isRotate;
417 // Load Upper Imediate
418 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
419 FI<op, (outs RC:$rt), (ins Imm:$imm16),
420 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
422 let neverHasSideEffects = 1;
423 let isReMaterializable = 1;
426 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
427 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
429 let Inst{25-21} = addr{20-16};
430 let Inst{15-0} = addr{15-0};
431 let DecoderMethod = "DecodeMem";
435 let canFoldAsLoad = 1 in
436 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
437 Operand MemOpnd, bit Pseudo>:
438 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
439 !strconcat(instr_asm, "\t$rt, $addr"),
440 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
441 let isPseudo = Pseudo;
444 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
445 Operand MemOpnd, bit Pseudo>:
446 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
447 !strconcat(instr_asm, "\t$rt, $addr"),
448 [(OpNode RC:$rt, addr:$addr)], IIStore> {
449 let isPseudo = Pseudo;
453 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
455 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
456 Requires<[NotN64, HasStandardEncoding]>;
457 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
458 Requires<[IsN64, HasStandardEncoding]> {
459 let DecoderNamespace = "Mips64";
460 let isCodeGenOnly = 1;
465 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
467 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
468 Requires<[NotN64, HasStandardEncoding]>;
469 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
470 Requires<[IsN64, HasStandardEncoding]> {
471 let DecoderNamespace = "Mips64";
472 let isCodeGenOnly = 1;
477 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
479 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
480 Requires<[NotN64, HasStandardEncoding]>;
481 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
482 Requires<[IsN64, HasStandardEncoding]> {
483 let DecoderNamespace = "Mips64";
484 let isCodeGenOnly = 1;
489 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
491 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
492 Requires<[NotN64, HasStandardEncoding]>;
493 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
494 Requires<[IsN64, HasStandardEncoding]> {
495 let DecoderNamespace = "Mips64";
496 let isCodeGenOnly = 1;
500 // Load/Store Left/Right
501 let canFoldAsLoad = 1 in
502 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
503 RegisterClass RC, Operand MemOpnd> :
504 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
505 !strconcat(instr_asm, "\t$rt, $addr"),
506 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
507 string Constraints = "$src = $rt";
510 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
511 RegisterClass RC, Operand MemOpnd>:
512 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
513 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
516 // 32-bit load left/right.
517 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
518 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
519 Requires<[NotN64, HasStandardEncoding]>;
520 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
521 Requires<[IsN64, HasStandardEncoding]> {
522 let DecoderNamespace = "Mips64";
523 let isCodeGenOnly = 1;
527 // 64-bit load left/right.
528 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
529 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
530 Requires<[NotN64, HasStandardEncoding]>;
531 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
532 Requires<[IsN64, HasStandardEncoding]> {
533 let DecoderNamespace = "Mips64";
534 let isCodeGenOnly = 1;
538 // 32-bit store left/right.
539 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
540 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
541 Requires<[NotN64, HasStandardEncoding]>;
542 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
543 Requires<[IsN64, HasStandardEncoding]> {
544 let DecoderNamespace = "Mips64";
545 let isCodeGenOnly = 1;
549 // 64-bit store left/right.
550 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
551 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
552 Requires<[NotN64, HasStandardEncoding]>;
553 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
554 Requires<[IsN64, HasStandardEncoding]> {
555 let DecoderNamespace = "Mips64";
556 let isCodeGenOnly = 1;
560 // Conditional Branch
561 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
562 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
563 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
564 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
566 let isTerminator = 1;
567 let hasDelaySlot = 1;
571 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
573 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
574 !strconcat(instr_asm, "\t$rs, $imm16"),
575 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
578 let isTerminator = 1;
579 let hasDelaySlot = 1;
584 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
586 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
587 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
588 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
593 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
594 PatLeaf imm_type, RegisterClass RC>:
595 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
596 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
597 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
601 class JumpFJ<bits<6> op, string instr_asm>:
602 FJ<op, (outs), (ins jmptarget:$target),
603 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
607 let hasDelaySlot = 1;
608 let Predicates = [RelocStatic, HasStandardEncoding];
609 let DecoderMethod = "DecodeJumpTarget";
613 // Unconditional branch
614 class UncondBranch<bits<6> op, string instr_asm>:
615 BranchBase<op, (outs), (ins brtarget:$imm16),
616 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
620 let isTerminator = 1;
622 let hasDelaySlot = 1;
623 let Predicates = [RelocPIC, HasStandardEncoding];
627 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
628 isIndirectBranch = 1 in
629 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
630 FR<op, func, (outs), (ins RC:$rs),
631 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
637 // Jump and Link (Call)
638 let isCall=1, hasDelaySlot=1 in {
639 class JumpLink<bits<6> op, string instr_asm>:
640 FJ<op, (outs), (ins calltarget:$target, variable_ops),
641 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
643 let DecoderMethod = "DecodeJumpTarget";
646 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
648 FR<op, func, (outs), (ins RC:$rs, variable_ops),
649 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
655 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
656 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
657 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
663 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
664 RegisterClass RC, list<Register> DefRegs>:
665 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
666 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
669 let isCommutable = 1;
671 let neverHasSideEffects = 1;
674 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
675 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
677 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
678 RegisterClass RC, list<Register> DefRegs>:
679 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
680 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
681 [(op RC:$rs, RC:$rt)], itin> {
687 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
688 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
691 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
692 list<Register> UseRegs>:
693 FR<0x00, func, (outs RC:$rd), (ins),
694 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
699 let neverHasSideEffects = 1;
702 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
703 list<Register> DefRegs>:
704 FR<0x00, func, (outs), (ins RC:$rs),
705 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
710 let neverHasSideEffects = 1;
713 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
714 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
715 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
717 // Count Leading Ones/Zeros in Word
718 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
719 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
720 !strconcat(instr_asm, "\t$rd, $rs"),
721 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
722 Requires<[HasBitCount, HasStandardEncoding]> {
727 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
728 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
729 !strconcat(instr_asm, "\t$rd, $rs"),
730 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
731 Requires<[HasBitCount, HasStandardEncoding]> {
736 // Sign Extend in Register.
737 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
739 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
740 !strconcat(instr_asm, "\t$rd, $rt"),
741 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
744 let Predicates = [HasSEInReg, HasStandardEncoding];
748 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
749 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
750 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
753 let Predicates = [HasSwap, HasStandardEncoding];
754 let neverHasSideEffects = 1;
758 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
759 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
760 "rdhwr\t$rt, $rd", [], IIAlu> {
766 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
767 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
768 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
769 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
774 let Predicates = [HasMips32r2, HasStandardEncoding];
777 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
778 FR<0x1f, _funct, (outs RC:$rt),
779 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
780 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
781 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
787 let Predicates = [HasMips32r2, HasStandardEncoding];
788 let Constraints = "$src = $rt";
791 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
792 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
794 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
795 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
796 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
798 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
799 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
800 Requires<[NotN64, HasStandardEncoding]>;
801 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
802 Requires<[IsN64, HasStandardEncoding]> {
803 let DecoderNamespace = "Mips64";
807 // Atomic Compare & Swap.
808 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
810 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
811 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
812 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
814 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
815 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
816 Requires<[NotN64, HasStandardEncoding]>;
817 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
818 Requires<[IsN64, HasStandardEncoding]> {
819 let DecoderNamespace = "Mips64";
823 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
824 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
825 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
829 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
830 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
831 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
833 let Constraints = "$rt = $dst";
836 //===----------------------------------------------------------------------===//
837 // Pseudo instructions
838 //===----------------------------------------------------------------------===//
840 // As stack alignment is always done with addiu, we need a 16-bit immediate
841 let Defs = [SP], Uses = [SP] in {
842 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
843 "!ADJCALLSTACKDOWN $amt",
844 [(callseq_start timm:$amt)]>;
845 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
846 "!ADJCALLSTACKUP $amt1",
847 [(callseq_end timm:$amt1, timm:$amt2)]>;
850 // When handling PIC code the assembler needs .cpload and .cprestore
851 // directives. If the real instructions corresponding these directives
852 // are used, we have the same behavior, but get also a bunch of warnings
853 // from the assembler.
854 let neverHasSideEffects = 1 in
855 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
856 ".cprestore\t$loc", []>;
858 let usesCustomInserter = 1 in {
859 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
860 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
861 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
862 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
863 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
864 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
865 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
866 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
867 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
868 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
869 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
870 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
871 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
872 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
873 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
874 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
875 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
876 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
878 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
879 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
880 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
882 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
883 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
884 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
887 //===----------------------------------------------------------------------===//
888 // Instruction definition
889 //===----------------------------------------------------------------------===//
891 //===----------------------------------------------------------------------===//
892 // MipsI Instructions
893 //===----------------------------------------------------------------------===//
895 /// Arithmetic Instructions (ALU Immediate)
896 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
897 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
898 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
899 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
900 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
901 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
902 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
903 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
905 /// Arithmetic Instructions (3-Operand, R-Type)
906 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
907 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
908 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
909 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
910 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
911 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
912 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
913 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
914 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
915 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
917 /// Shift Instructions
918 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
919 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
920 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
921 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
922 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
923 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
925 // Rotate Instructions
926 let Predicates = [HasMips32r2, HasStandardEncoding] in {
927 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
928 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
931 /// Load and Store Instructions
933 defm LB : LoadM32<0x20, "lb", sextloadi8>;
934 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
935 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
936 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
937 defm LW : LoadM32<0x23, "lw", load_a>;
938 defm SB : StoreM32<0x28, "sb", truncstorei8>;
939 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
940 defm SW : StoreM32<0x2b, "sw", store_a>;
943 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
944 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
945 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
946 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
947 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
949 /// load/store left/right
950 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
951 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
952 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
953 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
955 let hasSideEffects = 1 in
956 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
957 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
962 let Inst{10-6} = stype;
966 /// Load-linked, Store-conditional
967 def LL : LLBase<0x30, "ll", CPURegs, mem>,
968 Requires<[NotN64, HasStandardEncoding]>;
969 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
970 Requires<[IsN64, HasStandardEncoding]> {
971 let DecoderNamespace = "Mips64";
974 def SC : SCBase<0x38, "sc", CPURegs, mem>,
975 Requires<[NotN64, HasStandardEncoding]>;
976 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
977 Requires<[IsN64, HasStandardEncoding]> {
978 let DecoderNamespace = "Mips64";
981 /// Jump and Branch Instructions
982 def J : JumpFJ<0x02, "j">;
983 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
984 def B : UncondBranch<0x04, "b">;
985 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
986 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
987 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
988 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
989 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
990 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
992 def JAL : JumpLink<0x03, "jal">;
993 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
994 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
995 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
997 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
998 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
999 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
1000 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
1002 /// Multiply and Divide Instructions.
1003 def MULT : Mult32<0x18, "mult", IIImul>;
1004 def MULTu : Mult32<0x19, "multu", IIImul>;
1005 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1006 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1008 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1009 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1010 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1011 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1013 /// Sign Ext In Register Instructions.
1014 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1015 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1018 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1019 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1021 /// Word Swap Bytes Within Halfwords
1022 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1026 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1028 // FrameIndexes are legalized when they are operands from load/store
1029 // instructions. The same not happens for stack address copies, so an
1030 // add op with mem ComplexPattern is used and the stack address copy
1031 // can be matched. It's similar to Sparc LEA_ADDRi
1032 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1033 let isCodeGenOnly = 1;
1036 // DynAlloc node points to dynamically allocated stack space.
1037 // $sp is added to the list of implicitly used registers to prevent dead code
1038 // elimination from removing instructions that modify $sp.
1040 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
1041 let isCodeGenOnly = 1;
1045 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1046 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1047 def MSUB : MArithR<4, "msub", MipsMSub>;
1048 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1050 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1051 // it is a real instruction.
1052 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
1053 Requires<[HasMips32, HasStandardEncoding]>;
1055 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1057 def EXT : ExtBase<0, "ext", CPURegs>;
1058 def INS : InsBase<4, "ins", CPURegs>;
1060 //===----------------------------------------------------------------------===//
1061 // Arbitrary patterns that map to one or more instructions
1062 //===----------------------------------------------------------------------===//
1065 def : MipsPat<(i32 immSExt16:$in),
1066 (ADDiu ZERO, imm:$in)>;
1067 def : MipsPat<(i32 immZExt16:$in),
1068 (ORi ZERO, imm:$in)>;
1069 def : MipsPat<(i32 immLow16Zero:$in),
1070 (LUi (HI16 imm:$in))>;
1072 // Arbitrary immediates
1073 def : MipsPat<(i32 imm:$imm),
1074 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1076 // Carry MipsPatterns
1077 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1078 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1079 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1080 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1081 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1082 (ADDiu CPURegs:$src, imm:$imm)>;
1085 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1086 (JAL tglobaladdr:$dst)>;
1087 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1088 (JAL texternalsym:$dst)>;
1089 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1090 // (JALR CPURegs:$dst)>;
1093 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1094 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1095 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1096 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1097 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1099 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1100 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1101 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1102 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1103 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1105 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1106 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1107 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1108 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1109 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1110 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1111 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1112 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1113 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1114 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1117 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1118 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1119 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1120 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1123 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1124 MipsPat<(MipsWrapper RC:$gp, node:$in),
1125 (ADDiuOp RC:$gp, node:$in)>;
1127 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1128 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1129 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1130 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1131 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1132 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1134 // Mips does not have "not", so we expand our way
1135 def : MipsPat<(not CPURegs:$in),
1136 (NOR CPURegs:$in, ZERO)>;
1139 let Predicates = [NotN64, HasStandardEncoding] in {
1140 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1141 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1142 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1143 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1145 let Predicates = [IsN64, HasStandardEncoding] in {
1146 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1147 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1148 def : MipsPat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1149 def : MipsPat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1153 let Predicates = [NotN64, HasStandardEncoding] in {
1154 def : MipsPat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1155 def : MipsPat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1157 let Predicates = [IsN64, HasStandardEncoding] in {
1158 def : MipsPat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1159 def : MipsPat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1163 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1164 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1165 Instruction SLTiuOp, Register ZEROReg> {
1166 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1167 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1168 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1169 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1171 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1172 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1173 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1174 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1175 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1176 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1177 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1178 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1180 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1181 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1182 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1183 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1185 def : MipsPat<(brcond RC:$cond, bb:$dst),
1186 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1189 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1192 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1193 Instruction SLTuOp, Register ZEROReg> {
1194 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1195 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1196 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1197 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1200 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1201 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1202 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1203 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1204 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1207 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1208 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1209 (SLTOp RC:$rhs, RC:$lhs)>;
1210 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1211 (SLTuOp RC:$rhs, RC:$lhs)>;
1214 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1215 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1216 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1217 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1218 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1221 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1222 Instruction SLTiuOp> {
1223 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1224 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1225 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1226 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1229 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1230 defm : SetlePats<CPURegs, SLT, SLTu>;
1231 defm : SetgtPats<CPURegs, SLT, SLTu>;
1232 defm : SetgePats<CPURegs, SLT, SLTu>;
1233 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1235 // select MipsDynAlloc
1236 def : MipsPat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1239 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1241 //===----------------------------------------------------------------------===//
1242 // Floating Point Support
1243 //===----------------------------------------------------------------------===//
1245 include "MipsInstrFPU.td"
1246 include "Mips64InstrInfo.td"
1247 include "MipsCondMov.td"
1252 include "Mips16InstrFormats.td"
1253 include "Mips16InstrInfo.td"