1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget->isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64_NOT_64R6 {
244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
246 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
247 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
248 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
253 // The portions of MIPS-III that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS3_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-III that were also added to MIPS32
260 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
262 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
263 // MIPS32r6 and MIPS64r6.
264 class INSN_MIPS4_32_NOT_32R6_64R6 {
265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
268 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
280 //===----------------------------------------------------------------------===//
282 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
283 let EncodingPredicates = [HasStdEnc];
286 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
287 InstAlias<Asm, Result, Emit>, PredicateControl;
290 bit isCommutable = 1;
307 bit isTerminator = 1;
310 bit hasExtraSrcRegAllocReq = 1;
311 bit isCodeGenOnly = 1;
314 class IsAsCheapAsAMove {
315 bit isAsCheapAsAMove = 1;
318 class NeverHasSideEffects {
319 bit neverHasSideEffects = 1;
322 //===----------------------------------------------------------------------===//
323 // Instruction format superclass
324 //===----------------------------------------------------------------------===//
326 include "MipsInstrFormats.td"
328 //===----------------------------------------------------------------------===//
329 // Mips Operand, Complex Patterns and Transformations Definitions.
330 //===----------------------------------------------------------------------===//
332 def MipsJumpTargetAsmOperand : AsmOperandClass {
333 let Name = "JumpTarget";
334 let ParserMethod = "ParseJumpTarget";
335 let PredicateMethod = "isImm";
336 let RenderMethod = "addImmOperands";
339 // Instruction operand types
340 def jmptarget : Operand<OtherVT> {
341 let EncoderMethod = "getJumpTargetOpValue";
342 let ParserMatchClass = MipsJumpTargetAsmOperand;
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBranchTarget";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def calltarget : Operand<iPTR> {
351 let EncoderMethod = "getJumpTargetOpValue";
352 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def simm9 : Operand<i32>;
356 def simm10 : Operand<i32>;
357 def simm11 : Operand<i32>;
359 def simm16 : Operand<i32> {
360 let DecoderMethod= "DecodeSimm16";
363 def simm19_lsl2 : Operand<i32> {
364 let EncoderMethod = "getSimm19Lsl2Encoding";
365 let DecoderMethod = "DecodeSimm19Lsl2";
366 let ParserMatchClass = MipsJumpTargetAsmOperand;
369 def simm18_lsl3 : Operand<i32> {
370 let EncoderMethod = "getSimm18Lsl3Encoding";
371 let DecoderMethod = "DecodeSimm18Lsl3";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm20 : Operand<i32> {
378 def uimm20 : Operand<i32> {
381 def uimm10 : Operand<i32> {
384 def simm16_64 : Operand<i64> {
385 let DecoderMethod = "DecodeSimm16";
389 def uimmz : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
394 def uimm2 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm3 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm5 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm6 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def uimm16 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def pcrel16 : Operand<i32> {
417 def MipsMemAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseMemOperand";
422 def MipsMemSimm11AsmOperand : AsmOperandClass {
423 let Name = "MemOffsetSimm11";
424 let SuperClasses = [MipsMemAsmOperand];
425 let RenderMethod = "addMemOperands";
426 let ParserMethod = "parseMemOperand";
427 let PredicateMethod = "isMemWithSimmOffset<11>";
428 //let DiagnosticType = "Simm11";
431 def MipsInvertedImmoperand : AsmOperandClass {
433 let RenderMethod = "addImmOperands";
434 let ParserMethod = "parseInvNum";
437 def InvertedImOperand : Operand<i32> {
438 let ParserMatchClass = MipsInvertedImmoperand;
441 def InvertedImOperand64 : Operand<i64> {
442 let ParserMatchClass = MipsInvertedImmoperand;
445 class mem_generic : Operand<iPTR> {
446 let PrintMethod = "printMemOperand";
447 let MIOperandInfo = (ops ptr_rc, simm16);
448 let EncoderMethod = "getMemEncoding";
449 let ParserMatchClass = MipsMemAsmOperand;
450 let OperandType = "OPERAND_MEMORY";
454 def mem : mem_generic;
456 // MSA specific address operand
457 def mem_msa : mem_generic {
458 let MIOperandInfo = (ops ptr_rc, simm10);
459 let EncoderMethod = "getMSAMemEncoding";
462 def mem_simm9 : mem_generic {
463 let MIOperandInfo = (ops ptr_rc, simm9);
464 let EncoderMethod = "getMemEncoding";
467 def mem_simm11 : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm11);
469 let EncoderMethod = "getMemEncoding";
470 let ParserMatchClass = MipsMemSimm11AsmOperand;
473 def mem_ea : Operand<iPTR> {
474 let PrintMethod = "printMemOperandEA";
475 let MIOperandInfo = (ops ptr_rc, simm16);
476 let EncoderMethod = "getMemEncoding";
477 let OperandType = "OPERAND_MEMORY";
480 def PtrRC : Operand<iPTR> {
481 let MIOperandInfo = (ops ptr_rc);
482 let DecoderMethod = "DecodePtrRegisterClass";
483 let ParserMatchClass = GPR32AsmOperand;
486 // size operand of ext instruction
487 def size_ext : Operand<i32> {
488 let EncoderMethod = "getSizeExtEncoding";
489 let DecoderMethod = "DecodeExtSize";
492 // size operand of ins instruction
493 def size_ins : Operand<i32> {
494 let EncoderMethod = "getSizeInsEncoding";
495 let DecoderMethod = "DecodeInsSize";
498 // Transformation Function - get the lower 16 bits.
499 def LO16 : SDNodeXForm<imm, [{
500 return getImm(N, N->getZExtValue() & 0xFFFF);
503 // Transformation Function - get the higher 16 bits.
504 def HI16 : SDNodeXForm<imm, [{
505 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
509 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
511 // Node immediate is zero (e.g. insve.d)
512 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
514 // Node immediate fits as 16-bit sign extended on target immediate.
516 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
518 // Node immediate fits as 16-bit sign extended on target immediate.
520 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
522 // Node immediate fits as 15-bit sign extended on target immediate.
524 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
526 // Node immediate fits as 16-bit zero extended on target immediate.
527 // The LO16 param means that only the lower 16 bits of the node
528 // immediate are caught.
530 def immZExt16 : PatLeaf<(imm), [{
531 if (N->getValueType(0) == MVT::i32)
532 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
534 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
537 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
538 def immLow16Zero : PatLeaf<(imm), [{
539 int64_t Val = N->getSExtValue();
540 return isInt<32>(Val) && !(Val & 0xffff);
543 // shamt field must fit in 5 bits.
544 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
546 // True if (N + 1) fits in 16-bit field.
547 def immSExt16Plus1 : PatLeaf<(imm), [{
548 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
551 // Mips Address Mode! SDNode frameindex could possibily be a match
552 // since load and store instructions from stack used it.
554 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
557 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
560 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
563 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
565 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
567 //===----------------------------------------------------------------------===//
568 // Instructions specific format
569 //===----------------------------------------------------------------------===//
571 // Arithmetic and logical instructions with 3 register operands.
572 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
573 InstrItinClass Itin = NoItinerary,
574 SDPatternOperator OpNode = null_frag>:
575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
576 !strconcat(opstr, "\t$rd, $rs, $rt"),
577 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
578 let isCommutable = isComm;
579 let isReMaterializable = 1;
580 let TwoOperandAliasConstraint = "$rd = $rs";
583 // Arithmetic and logical instructions with 2 register operands.
584 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
585 InstrItinClass Itin = NoItinerary,
586 SDPatternOperator imm_type = null_frag,
587 SDPatternOperator OpNode = null_frag> :
588 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
589 !strconcat(opstr, "\t$rt, $rs, $imm16"),
590 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
592 let isReMaterializable = 1;
593 let TwoOperandAliasConstraint = "$rs = $rt";
596 // Arithmetic Multiply ADD/SUB
597 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
598 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
599 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
600 let Defs = [HI0, LO0];
601 let Uses = [HI0, LO0];
602 let isCommutable = isComm;
606 class LogicNOR<string opstr, RegisterOperand RO>:
607 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
608 !strconcat(opstr, "\t$rd, $rs, $rt"),
609 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
610 let isCommutable = 1;
614 class shift_rotate_imm<string opstr, Operand ImmOpnd,
615 RegisterOperand RO, InstrItinClass itin,
616 SDPatternOperator OpNode = null_frag,
617 SDPatternOperator PF = null_frag> :
618 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
619 !strconcat(opstr, "\t$rd, $rt, $shamt"),
620 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
621 let TwoOperandAliasConstraint = "$rt = $rd";
624 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
625 SDPatternOperator OpNode = null_frag>:
626 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
627 !strconcat(opstr, "\t$rd, $rt, $rs"),
628 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
631 // Load Upper Imediate
632 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
633 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
634 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
635 let neverHasSideEffects = 1;
636 let isReMaterializable = 1;
640 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
641 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
642 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
643 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
644 let DecoderMethod = "DecodeMem";
645 let canFoldAsLoad = 1;
649 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
650 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
652 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
653 let DecoderMethod = "DecodeMem";
657 // Load/Store Left/Right
658 let canFoldAsLoad = 1 in
659 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
660 InstrItinClass Itin> :
661 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
662 !strconcat(opstr, "\t$rt, $addr"),
663 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
664 let DecoderMethod = "DecodeMem";
665 string Constraints = "$src = $rt";
668 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
669 InstrItinClass Itin> :
670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
671 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
672 let DecoderMethod = "DecodeMem";
675 // Conditional Branch
676 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
677 RegisterOperand RO> :
678 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
679 !strconcat(opstr, "\t$rs, $rt, $offset"),
680 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
683 let isTerminator = 1;
684 let hasDelaySlot = 1;
688 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
689 RegisterOperand RO> :
690 InstSE<(outs), (ins RO:$rs, opnd:$offset),
691 !strconcat(opstr, "\t$rs, $offset"),
692 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
695 let isTerminator = 1;
696 let hasDelaySlot = 1;
701 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
702 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
703 !strconcat(opstr, "\t$rd, $rs, $rt"),
704 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
705 II_SLT_SLTU, FrmR, opstr>;
707 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
709 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
710 !strconcat(opstr, "\t$rt, $rs, $imm16"),
711 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
712 II_SLTI_SLTIU, FrmI, opstr>;
715 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
716 SDPatternOperator targetoperator, string bopstr> :
717 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
718 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
721 let hasDelaySlot = 1;
722 let DecoderMethod = "DecodeJumpTarget";
726 // Unconditional branch
727 class UncondBranch<Instruction BEQInst> :
728 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
729 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
731 let isTerminator = 1;
733 let hasDelaySlot = 1;
734 let AdditionalPredicates = [RelocPIC];
738 // Base class for indirect branch and return instruction classes.
739 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
740 class JumpFR<string opstr, RegisterOperand RO,
741 SDPatternOperator operator = null_frag>:
742 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
746 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
748 let isIndirectBranch = 1;
751 // Jump and Link (Call)
752 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
753 class JumpLink<string opstr, DAGOperand opnd> :
754 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
755 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
756 let DecoderMethod = "DecodeJumpTarget";
759 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
760 Register RetReg, RegisterOperand ResRO = RO>:
761 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
762 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
764 class JumpLinkReg<string opstr, RegisterOperand RO>:
765 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
768 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
769 InstSE<(outs), (ins RO:$rs, opnd:$offset),
770 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
774 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
775 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
776 class TailCall<Instruction JumpInst> :
777 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
778 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
780 class TailCallReg<RegisterOperand RO, Instruction JRInst,
781 RegisterOperand ResRO = RO> :
782 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
783 PseudoInstExpansion<(JRInst ResRO:$rs)>;
786 class BAL_BR_Pseudo<Instruction RealInst> :
787 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
788 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
790 let isTerminator = 1;
792 let hasDelaySlot = 1;
797 class SYS_FT<string opstr> :
798 InstSE<(outs), (ins uimm20:$code_),
799 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
801 class BRK_FT<string opstr> :
802 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
803 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
807 class ER_FT<string opstr> :
808 InstSE<(outs), (ins),
809 opstr, [], NoItinerary, FrmOther, opstr>;
812 class DEI_FT<string opstr, RegisterOperand RO> :
813 InstSE<(outs RO:$rt), (ins),
814 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
817 class WAIT_FT<string opstr> :
818 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
821 let hasSideEffects = 1 in
822 class SYNC_FT<string opstr> :
823 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
824 NoItinerary, FrmOther, opstr>;
826 let hasSideEffects = 1 in
827 class TEQ_FT<string opstr, RegisterOperand RO> :
828 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
829 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
832 class TEQI_FT<string opstr, RegisterOperand RO> :
833 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
834 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
836 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
837 list<Register> DefRegs> :
838 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
840 let isCommutable = 1;
842 let neverHasSideEffects = 1;
845 // Pseudo multiply/divide instruction with explicit accumulator register
847 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
848 SDPatternOperator OpNode, InstrItinClass Itin,
849 bit IsComm = 1, bit HasSideEffects = 0,
850 bit UsesCustomInserter = 0> :
851 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
852 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
853 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
854 let isCommutable = IsComm;
855 let hasSideEffects = HasSideEffects;
856 let usesCustomInserter = UsesCustomInserter;
859 // Pseudo multiply add/sub instruction with explicit accumulator register
861 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
863 : PseudoSE<(outs ACC64:$ac),
864 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
866 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
868 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
869 string Constraints = "$acin = $ac";
872 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
873 list<Register> DefRegs> :
874 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
875 [], itin, FrmR, opstr> {
880 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
881 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
882 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
884 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
885 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
888 let neverHasSideEffects = 1;
891 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
892 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
893 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
896 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
897 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
900 let neverHasSideEffects = 1;
903 class EffectiveAddress<string opstr, RegisterOperand RO> :
904 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
905 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
906 !strconcat(opstr, "_lea")> {
907 let isCodeGenOnly = 1;
908 let DecoderMethod = "DecodeMem";
911 // Count Leading Ones/Zeros in Word
912 class CountLeading0<string opstr, RegisterOperand RO>:
913 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
914 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
916 class CountLeading1<string opstr, RegisterOperand RO>:
917 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
918 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
920 // Sign Extend in Register.
921 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
922 InstrItinClass itin> :
923 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
924 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
927 class SubwordSwap<string opstr, RegisterOperand RO>:
928 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
929 NoItinerary, FrmR, opstr> {
930 let neverHasSideEffects = 1;
934 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
935 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
939 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
940 SDPatternOperator Op = null_frag>:
941 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
942 !strconcat(opstr, " $rt, $rs, $pos, $size"),
943 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
944 FrmR, opstr>, ISA_MIPS32R2;
946 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
947 SDPatternOperator Op = null_frag>:
948 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
949 !strconcat(opstr, " $rt, $rs, $pos, $size"),
950 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
951 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
952 let Constraints = "$src = $rt";
955 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
956 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
957 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
958 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
960 // Atomic Compare & Swap.
961 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
962 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
963 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
965 class LLBase<string opstr, RegisterOperand RO> :
966 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
967 [], NoItinerary, FrmI> {
968 let DecoderMethod = "DecodeMem";
972 class SCBase<string opstr, RegisterOperand RO> :
973 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
974 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
975 let DecoderMethod = "DecodeMem";
977 let Constraints = "$rt = $dst";
980 class MFC3OP<string asmstr, RegisterOperand RO> :
981 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
982 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
984 class TrapBase<Instruction RealInst>
985 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
986 PseudoInstExpansion<(RealInst 0, 0)> {
988 let isTerminator = 1;
989 let isCodeGenOnly = 1;
992 //===----------------------------------------------------------------------===//
993 // Pseudo instructions
994 //===----------------------------------------------------------------------===//
997 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
998 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1000 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1001 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1002 [(callseq_start timm:$amt)]>;
1003 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1004 [(callseq_end timm:$amt1, timm:$amt2)]>;
1007 let usesCustomInserter = 1 in {
1008 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1009 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1010 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1011 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1012 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1013 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1014 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1015 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1016 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1017 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1018 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1019 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1020 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1021 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1022 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1023 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1024 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1025 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1027 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1028 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1029 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1031 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1032 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1033 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1036 /// Pseudo instructions for loading and storing accumulator registers.
1037 let isPseudo = 1, isCodeGenOnly = 1 in {
1038 def LOAD_ACC64 : Load<"", ACC64>;
1039 def STORE_ACC64 : Store<"", ACC64>;
1042 // We need these two pseudo instructions to avoid offset calculation for long
1043 // branches. See the comment in file MipsLongBranch.cpp for detailed
1046 // Expands to: lui $dst, %hi($tgt - $baltgt)
1047 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1048 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1050 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1051 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1052 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1054 //===----------------------------------------------------------------------===//
1055 // Instruction definition
1056 //===----------------------------------------------------------------------===//
1057 //===----------------------------------------------------------------------===//
1058 // MipsI Instructions
1059 //===----------------------------------------------------------------------===//
1061 /// Arithmetic Instructions (ALU Immediate)
1062 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1064 ADDI_FM<0x9>, IsAsCheapAsAMove;
1065 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1066 ISA_MIPS1_NOT_32R6_64R6;
1067 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1069 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1071 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1074 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1077 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1080 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1082 /// Arithmetic Instructions (3-Operand, R-Type)
1083 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1085 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1087 let Defs = [HI0, LO0] in
1088 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1089 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1090 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1091 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1092 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1093 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1094 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1096 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1098 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1100 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1102 /// Shift Instructions
1103 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1104 immZExt5>, SRA_FM<0, 0>;
1105 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1106 immZExt5>, SRA_FM<2, 0>;
1107 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1108 immZExt5>, SRA_FM<3, 0>;
1109 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1111 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1113 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1116 // Rotate Instructions
1117 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1119 SRA_FM<2, 1>, ISA_MIPS32R2;
1120 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1121 SRLV_FM<6, 1>, ISA_MIPS32R2;
1123 /// Load and Store Instructions
1125 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1126 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1128 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1130 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1131 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1133 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1134 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1135 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1137 /// load/store left/right
1138 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1139 AdditionalPredicates = [NotInMicroMips] in {
1140 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1141 ISA_MIPS1_NOT_32R6_64R6;
1142 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1143 ISA_MIPS1_NOT_32R6_64R6;
1144 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1145 ISA_MIPS1_NOT_32R6_64R6;
1146 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1147 ISA_MIPS1_NOT_32R6_64R6;
1150 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1151 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1152 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1153 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1154 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1155 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1156 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1158 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1159 ISA_MIPS2_NOT_32R6_64R6;
1160 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1161 ISA_MIPS2_NOT_32R6_64R6;
1162 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1163 ISA_MIPS2_NOT_32R6_64R6;
1164 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1165 ISA_MIPS2_NOT_32R6_64R6;
1166 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1167 ISA_MIPS2_NOT_32R6_64R6;
1168 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1169 ISA_MIPS2_NOT_32R6_64R6;
1171 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1172 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1173 def TRAP : TrapBase<BREAK>;
1174 def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1176 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1177 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1179 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1180 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1182 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1183 AdditionalPredicates = [NotInMicroMips] in {
1184 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1186 /// Load-linked, Store-conditional
1187 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1188 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1191 /// Jump and Branch Instructions
1192 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1193 AdditionalRequires<[RelocStatic]>, IsBranch;
1194 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1195 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1196 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1197 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1199 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1201 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1203 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1205 def B : UncondBranch<BEQ>;
1207 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1208 let AdditionalPredicates = [NotInMicroMips] in {
1209 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1210 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1213 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1214 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1215 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1216 ISA_MIPS1_NOT_32R6_64R6;
1217 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1218 ISA_MIPS1_NOT_32R6_64R6;
1219 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1220 def TAILCALL : TailCall<J>;
1221 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1223 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1224 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1225 class PseudoIndirectBranchBase<RegisterOperand RO> :
1226 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1229 let hasDelaySlot = 1;
1231 let isIndirectBranch = 1;
1234 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1236 // Return instructions are matched as a RetRA instruction, then ar expanded
1237 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1238 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1240 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1242 let isTerminator = 1;
1244 let hasDelaySlot = 1;
1246 let isCodeGenOnly = 1;
1248 let hasExtraSrcRegAllocReq = 1;
1251 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1253 // Exception handling related node and instructions.
1254 // The conversion sequence is:
1255 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1256 // MIPSeh_return -> (stack change + indirect branch)
1258 // MIPSeh_return takes the place of regular return instruction
1259 // but takes two arguments (V1, V0) which are used for storing
1260 // the offset and return address respectively.
1261 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1263 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1264 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1266 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1267 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1268 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1269 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1271 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1274 /// Multiply and Divide Instructions.
1275 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1276 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1277 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1278 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1279 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1280 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1281 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1282 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1284 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1285 ISA_MIPS1_NOT_32R6_64R6;
1286 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1287 ISA_MIPS1_NOT_32R6_64R6;
1288 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1289 AdditionalPredicates = [NotInMicroMips] in {
1290 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1291 ISA_MIPS1_NOT_32R6_64R6;
1292 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1293 ISA_MIPS1_NOT_32R6_64R6;
1296 /// Sign Ext In Register Instructions.
1297 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1298 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1299 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1300 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1303 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1304 ISA_MIPS32_NOT_32R6_64R6;
1305 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1306 ISA_MIPS32_NOT_32R6_64R6;
1308 /// Word Swap Bytes Within Halfwords
1309 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1312 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1314 // FrameIndexes are legalized when they are operands from load/store
1315 // instructions. The same not happens for stack address copies, so an
1316 // add op with mem ComplexPattern is used and the stack address copy
1317 // can be matched. It's similar to Sparc LEA_ADDRi
1318 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1321 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1322 ISA_MIPS32_NOT_32R6_64R6;
1323 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1324 ISA_MIPS32_NOT_32R6_64R6;
1325 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1326 ISA_MIPS32_NOT_32R6_64R6;
1327 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1328 ISA_MIPS32_NOT_32R6_64R6;
1330 let AdditionalPredicates = [NotDSP] in {
1331 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1332 ISA_MIPS1_NOT_32R6_64R6;
1333 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1334 ISA_MIPS1_NOT_32R6_64R6;
1335 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1336 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1337 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1338 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1339 ISA_MIPS32_NOT_32R6_64R6;
1340 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1341 ISA_MIPS32_NOT_32R6_64R6;
1342 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1343 ISA_MIPS32_NOT_32R6_64R6;
1344 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1345 ISA_MIPS32_NOT_32R6_64R6;
1348 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1349 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1350 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1351 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1353 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1355 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1356 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1358 /// Move Control Registers From/To CPU Registers
1359 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1360 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1361 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1362 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1364 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1366 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1367 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1368 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1370 // JR_HB and JALR_HB are defined here using the new style naming
1371 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1372 // and because of that it doesn't follow the naming convention of the
1373 // rest of the file. To avoid a mixture of old vs new style, the new
1374 // style was chosen.
1375 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1376 dag OutOperandList = (outs);
1377 dag InOperandList = (ins GPROpnd:$rs);
1378 string AsmString = !strconcat(instr_asm, "\t$rs");
1379 list<dag> Pattern = [];
1382 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1383 dag OutOperandList = (outs GPROpnd:$rd);
1384 dag InOperandList = (ins GPROpnd:$rs);
1385 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1386 list<dag> Pattern = [];
1389 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1390 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1392 let isIndirectBranch=1;
1398 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1399 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1400 let isIndirectBranch=1;
1404 class JR_HB_ENC : JR_HB_FM<8>;
1405 class JALR_HB_ENC : JALR_HB_FM<9>;
1407 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1408 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1410 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1412 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1413 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1414 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1415 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1417 class CacheOp<string instr_asm, Operand MemOpnd, RegisterOperand GPROpnd> :
1418 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1419 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther>;
1421 def CACHE : CacheOp<"cache", mem, GPR32Opnd>, CACHEOP_FM<0b101111>,
1422 INSN_MIPS3_32_NOT_32R6_64R6;
1423 def PREF : CacheOp<"pref", mem, GPR32Opnd>, CACHEOP_FM<0b110011>,
1424 INSN_MIPS3_32_NOT_32R6_64R6;
1426 //===----------------------------------------------------------------------===//
1427 // Instruction aliases
1428 //===----------------------------------------------------------------------===//
1429 def : MipsInstAlias<"move $dst, $src",
1430 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1432 let AdditionalPredicates = [NotInMicroMips];
1434 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1435 ISA_MIPS1_NOT_32R6_64R6;
1436 def : MipsInstAlias<"addu $rs, $rt, $imm",
1437 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1438 def : MipsInstAlias<"add $rs, $rt, $imm",
1439 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1440 def : MipsInstAlias<"and $rs, $rt, $imm",
1441 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1442 def : MipsInstAlias<"and $rs, $imm",
1443 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1444 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1445 let Predicates = [NotInMicroMips] in {
1446 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1448 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1449 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1450 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1451 def : MipsInstAlias<"not $rt, $rs",
1452 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1453 def : MipsInstAlias<"neg $rt, $rs",
1454 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1455 def : MipsInstAlias<"negu $rt",
1456 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1457 def : MipsInstAlias<"negu $rt, $rs",
1458 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1459 def : MipsInstAlias<"slt $rs, $rt, $imm",
1460 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1461 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1462 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1463 def : MipsInstAlias<"xor $rs, $rt, $imm",
1464 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1465 def : MipsInstAlias<"or $rs, $rt, $imm",
1466 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1467 def : MipsInstAlias<"or $rs, $imm",
1468 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1469 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1470 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1471 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1472 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1473 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1474 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1475 def : MipsInstAlias<"bnez $rs,$offset",
1476 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1477 def : MipsInstAlias<"beqz $rs,$offset",
1478 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1479 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1481 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1482 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1483 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1484 def : MipsInstAlias<"di", (DI ZERO), 1>;
1486 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1487 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1488 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1490 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1491 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1493 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1494 def : MipsInstAlias<"sll $rd, $rt, $rs",
1495 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1496 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1497 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1498 InvertedImOperand:$imm), 0>;
1499 def : MipsInstAlias<"sub $rs, $imm",
1500 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1502 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1503 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1504 InvertedImOperand:$imm), 0>;
1505 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1506 InvertedImOperand:$imm), 0>;
1507 def : MipsInstAlias<"sra $rd, $rt, $rs",
1508 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1509 def : MipsInstAlias<"srl $rd, $rt, $rs",
1510 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1511 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1512 def : MipsInstAlias<"sync",
1513 (SYNC 0), 1>, ISA_MIPS2;
1514 //===----------------------------------------------------------------------===//
1515 // Assembler Pseudo Instructions
1516 //===----------------------------------------------------------------------===//
1518 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1519 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1520 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1521 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1523 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1524 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1525 !strconcat(instr_asm, "\t$rt, $addr")> ;
1526 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1528 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1529 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1530 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1531 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1533 //===----------------------------------------------------------------------===//
1534 // Arbitrary patterns that map to one or more instructions
1535 //===----------------------------------------------------------------------===//
1537 // Load/store pattern templates.
1538 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1539 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1541 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1542 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1545 def : MipsPat<(i32 immSExt16:$in),
1546 (ADDiu ZERO, imm:$in)>;
1547 def : MipsPat<(i32 immZExt16:$in),
1548 (ORi ZERO, imm:$in)>;
1549 def : MipsPat<(i32 immLow16Zero:$in),
1550 (LUi (HI16 imm:$in))>;
1552 // Arbitrary immediates
1553 def : MipsPat<(i32 imm:$imm),
1554 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1556 // Carry MipsPatterns
1557 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1558 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1559 let AdditionalPredicates = [NotDSP] in {
1560 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1561 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1562 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1563 (ADDiu GPR32:$src, imm:$imm)>;
1567 def : MipsPat<(MipsSync (i32 immz)),
1568 (SYNC 0)>, ISA_MIPS2;
1571 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1572 (JAL tglobaladdr:$dst)>;
1573 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1574 (JAL texternalsym:$dst)>;
1575 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1576 // (JALR GPR32:$dst)>;
1579 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1580 (TAILCALL tglobaladdr:$dst)>;
1581 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1582 (TAILCALL texternalsym:$dst)>;
1584 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1585 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1586 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1587 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1588 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1589 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1591 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1592 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1593 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1594 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1595 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1596 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1598 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1599 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1600 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1601 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1602 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1603 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1604 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1605 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1606 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1607 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1610 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1611 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1612 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1613 (ADDiu GPR32:$gp, tconstpool:$in)>;
1616 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1617 MipsPat<(MipsWrapper RC:$gp, node:$in),
1618 (ADDiuOp RC:$gp, node:$in)>;
1620 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1621 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1622 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1623 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1624 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1625 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1627 // Mips does not have "not", so we expand our way
1628 def : MipsPat<(not GPR32:$in),
1629 (NOR GPR32Opnd:$in, ZERO)>;
1632 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1633 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1634 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1637 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1640 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1641 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1642 Instruction SLTiuOp, Register ZEROReg> {
1643 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1644 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1645 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1646 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1648 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1649 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1650 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1651 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1652 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1653 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1654 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1655 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1656 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1657 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1658 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1659 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1661 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1662 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1663 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1664 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1666 def : MipsPat<(brcond RC:$cond, bb:$dst),
1667 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1670 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1672 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1673 (BLEZ i32:$lhs, bb:$dst)>;
1674 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1675 (BGEZ i32:$lhs, bb:$dst)>;
1678 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1679 Instruction SLTuOp, Register ZEROReg> {
1680 def : MipsPat<(seteq RC:$lhs, 0),
1681 (SLTiuOp RC:$lhs, 1)>;
1682 def : MipsPat<(setne RC:$lhs, 0),
1683 (SLTuOp ZEROReg, RC:$lhs)>;
1684 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1685 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1686 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1687 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1690 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1691 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1692 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1693 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1694 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1697 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1698 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1699 (SLTOp RC:$rhs, RC:$lhs)>;
1700 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1701 (SLTuOp RC:$rhs, RC:$lhs)>;
1704 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1705 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1706 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1707 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1708 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1711 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1712 Instruction SLTiuOp> {
1713 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1714 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1715 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1716 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1719 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1720 defm : SetlePats<GPR32, SLT, SLTu>;
1721 defm : SetgtPats<GPR32, SLT, SLTu>;
1722 defm : SetgePats<GPR32, SLT, SLTu>;
1723 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1726 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1728 // Load halfword/word patterns.
1729 let AddedComplexity = 40 in {
1730 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1731 def : LoadRegImmPat<LH, i32, sextloadi16>;
1732 def : LoadRegImmPat<LW, i32, load>;
1735 //===----------------------------------------------------------------------===//
1736 // Floating Point Support
1737 //===----------------------------------------------------------------------===//
1739 include "MipsInstrFPU.td"
1740 include "Mips64InstrInfo.td"
1741 include "MipsCondMov.td"
1743 include "Mips32r6InstrInfo.td"
1744 include "Mips64r6InstrInfo.td"
1749 include "Mips16InstrFormats.td"
1750 include "Mips16InstrInfo.td"
1753 include "MipsDSPInstrFormats.td"
1754 include "MipsDSPInstrInfo.td"
1757 include "MipsMSAInstrFormats.td"
1758 include "MipsMSAInstrInfo.td"
1761 include "MicroMipsInstrFormats.td"
1762 include "MicroMipsInstrInfo.td"
1763 include "MicroMipsInstrFPU.td"