1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r5 : Predicate<"Subtarget->hasMips32r5()">,
170 AssemblerPredicate<"FeatureMips32r5">;
171 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"FeatureMips32r6">;
173 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
174 AssemblerPredicate<"!FeatureMips32r6">;
175 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
176 AssemblerPredicate<"FeatureGP64Bit">;
177 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
178 AssemblerPredicate<"!FeatureGP64Bit">;
179 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
180 AssemblerPredicate<"FeatureMips64">;
181 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
182 AssemblerPredicate<"FeatureMips64r2">;
183 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"FeatureMips64r6">;
185 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
186 AssemblerPredicate<"!FeatureMips64r6">;
187 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
188 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
189 def HasMicroMips64r6 : Predicate<"Subtarget->inMicroMips64r6Mode()">,
190 AssemblerPredicate<"FeatureMicroMips,FeatureMips64r6">;
191 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
192 AssemblerPredicate<"FeatureMips16">;
193 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
194 AssemblerPredicate<"FeatureCnMips">;
195 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
196 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
197 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
198 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
199 AssemblerPredicate<"!FeatureMips16">;
200 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
201 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
202 AssemblerPredicate<"FeatureMicroMips">;
203 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
204 AssemblerPredicate<"!FeatureMicroMips">;
205 def IsLE : Predicate<"Subtarget->isLittle()">;
206 def IsBE : Predicate<"!Subtarget->isLittle()">;
207 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
208 def UseTCCInDIV : AssemblerPredicate<"FeatureUseTCCInDIV">;
210 //===----------------------------------------------------------------------===//
211 // Mips GPR size adjectives.
212 // They are mutually exclusive.
213 //===----------------------------------------------------------------------===//
215 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
216 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
218 //===----------------------------------------------------------------------===//
219 // Mips ISA/ASE membership and instruction group membership adjectives.
220 // They are mutually exclusive.
221 //===----------------------------------------------------------------------===//
223 // FIXME: I'd prefer to use additive predicates to build the instruction sets
224 // but we are short on assembler feature bits at the moment. Using a
225 // subtractive predicate will hopefully keep us under the 32 predicate
226 // limit long enough to develop an alternative way to handle P1||P2
228 class ISA_MIPS1_NOT_4_32 {
229 list<Predicate> InsnPredicates = [NotMips4_32];
231 class ISA_MIPS1_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
234 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
235 class ISA_MIPS2_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
238 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
239 class ISA_MIPS3_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
242 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
243 class ISA_MIPS32_NOT_32R6_64R6 {
244 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
246 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
247 class ISA_MIPS32R2_NOT_32R6_64R6 {
248 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
250 class ISA_MIPS32R5 { list<Predicate> InsnPredicates = [HasMips32r5]; }
251 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
252 class ISA_MIPS64_NOT_64R6 {
253 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
255 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
256 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
257 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
258 class ISA_MICROMIPS { list<Predicate> InsnPredicates = [InMicroMips]; }
259 class ISA_MICROMIPS32R6 {
260 list<Predicate> InsnPredicates = [HasMicroMips32r6];
262 class ISA_MICROMIPS64R6 {
263 list<Predicate> InsnPredicates = [HasMicroMips64r6];
266 // The portions of MIPS-III that were also added to MIPS32
267 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
269 // The portions of MIPS-III that were also added to MIPS32 but were removed in
270 // MIPS32r6 and MIPS64r6.
271 class INSN_MIPS3_32_NOT_32R6_64R6 {
272 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
275 // The portions of MIPS-III that were also added to MIPS32
276 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
278 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
279 // MIPS32r6 and MIPS64r6.
280 class INSN_MIPS4_32_NOT_32R6_64R6 {
281 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
284 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
285 // MIPS32r6 and MIPS64r6.
286 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
287 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
290 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
291 // MIPS32r6 and MIPS64r6.
292 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
293 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
296 // Class used for separating microMIPSr6 and microMIPS (r3) instruction.
297 // It can be used only on instructions that doesn't inherit PredicateControl.
298 class ISA_MICROMIPS_NOT_32R6_64R6 : PredicateControl {
299 let InsnPredicates = [InMicroMips, NotMips32r6, NotMips64r6];
302 //===----------------------------------------------------------------------===//
304 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
305 let EncodingPredicates = [HasStdEnc];
308 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
309 InstAlias<Asm, Result, Emit>, PredicateControl;
312 bit isCommutable = 1;
329 bit isTerminator = 1;
332 bit hasExtraSrcRegAllocReq = 1;
333 bit isCodeGenOnly = 1;
336 class IsAsCheapAsAMove {
337 bit isAsCheapAsAMove = 1;
340 class NeverHasSideEffects {
341 bit hasSideEffects = 0;
344 //===----------------------------------------------------------------------===//
345 // Instruction format superclass
346 //===----------------------------------------------------------------------===//
348 include "MipsInstrFormats.td"
350 //===----------------------------------------------------------------------===//
351 // Mips Operand, Complex Patterns and Transformations Definitions.
352 //===----------------------------------------------------------------------===//
354 def MipsJumpTargetAsmOperand : AsmOperandClass {
355 let Name = "JumpTarget";
356 let ParserMethod = "parseJumpTarget";
357 let PredicateMethod = "isImm";
358 let RenderMethod = "addImmOperands";
361 // Instruction operand types
362 def jmptarget : Operand<OtherVT> {
363 let EncoderMethod = "getJumpTargetOpValue";
364 let ParserMatchClass = MipsJumpTargetAsmOperand;
366 def brtarget : Operand<OtherVT> {
367 let EncoderMethod = "getBranchTargetOpValue";
368 let OperandType = "OPERAND_PCREL";
369 let DecoderMethod = "DecodeBranchTarget";
370 let ParserMatchClass = MipsJumpTargetAsmOperand;
372 def calltarget : Operand<iPTR> {
373 let EncoderMethod = "getJumpTargetOpValue";
374 let ParserMatchClass = MipsJumpTargetAsmOperand;
377 def imm64: Operand<i64>;
379 def simm9 : Operand<i32>;
380 def simm10 : Operand<i32>;
381 def simm11 : Operand<i32>;
383 def simm16 : Operand<i32> {
384 let DecoderMethod= "DecodeSimm16";
387 def simm19_lsl2 : Operand<i32> {
388 let EncoderMethod = "getSimm19Lsl2Encoding";
389 let DecoderMethod = "DecodeSimm19Lsl2";
390 let ParserMatchClass = MipsJumpTargetAsmOperand;
393 def simm18_lsl3 : Operand<i32> {
394 let EncoderMethod = "getSimm18Lsl3Encoding";
395 let DecoderMethod = "DecodeSimm18Lsl3";
396 let ParserMatchClass = MipsJumpTargetAsmOperand;
399 def simm20 : Operand<i32> {
402 def uimm20 : Operand<i32> {
405 def MipsUImm10AsmOperand : AsmOperandClass {
407 let RenderMethod = "addImmOperands";
408 let ParserMethod = "parseImm";
409 let PredicateMethod = "isUImm<10>";
412 def uimm10 : Operand<i32> {
413 let ParserMatchClass = MipsUImm10AsmOperand;
416 def simm16_64 : Operand<i64> {
417 let DecoderMethod = "DecodeSimm16";
421 def uimmz : Operand<i32> {
422 let PrintMethod = "printUnsignedImm";
426 def uimm2 : Operand<i32> {
427 let PrintMethod = "printUnsignedImm";
430 def uimm3 : Operand<i32> {
431 let PrintMethod = "printUnsignedImm";
434 def uimm5 : Operand<i32> {
435 let PrintMethod = "printUnsignedImm";
438 def uimm6 : Operand<i32> {
439 let PrintMethod = "printUnsignedImm";
442 def uimm16 : Operand<i32> {
443 let PrintMethod = "printUnsignedImm";
446 def pcrel16 : Operand<i32> {
449 def MipsMemAsmOperand : AsmOperandClass {
451 let ParserMethod = "parseMemOperand";
454 def MipsMemSimm9AsmOperand : AsmOperandClass {
455 let Name = "MemOffsetSimm9";
456 let SuperClasses = [MipsMemAsmOperand];
457 let RenderMethod = "addMemOperands";
458 let ParserMethod = "parseMemOperand";
459 let PredicateMethod = "isMemWithSimmOffset<9>";
462 def MipsMemSimm11AsmOperand : AsmOperandClass {
463 let Name = "MemOffsetSimm11";
464 let SuperClasses = [MipsMemAsmOperand];
465 let RenderMethod = "addMemOperands";
466 let ParserMethod = "parseMemOperand";
467 let PredicateMethod = "isMemWithSimmOffset<11>";
470 def MipsMemSimm16AsmOperand : AsmOperandClass {
471 let Name = "MemOffsetSimm16";
472 let SuperClasses = [MipsMemAsmOperand];
473 let RenderMethod = "addMemOperands";
474 let ParserMethod = "parseMemOperand";
475 let PredicateMethod = "isMemWithSimmOffset<16>";
478 def MipsInvertedImmoperand : AsmOperandClass {
480 let RenderMethod = "addImmOperands";
481 let ParserMethod = "parseInvNum";
484 def InvertedImOperand : Operand<i32> {
485 let ParserMatchClass = MipsInvertedImmoperand;
488 def InvertedImOperand64 : Operand<i64> {
489 let ParserMatchClass = MipsInvertedImmoperand;
492 class mem_generic : Operand<iPTR> {
493 let PrintMethod = "printMemOperand";
494 let MIOperandInfo = (ops ptr_rc, simm16);
495 let EncoderMethod = "getMemEncoding";
496 let ParserMatchClass = MipsMemAsmOperand;
497 let OperandType = "OPERAND_MEMORY";
501 def mem : mem_generic;
503 // MSA specific address operand
504 def mem_msa : mem_generic {
505 let MIOperandInfo = (ops ptr_rc, simm10);
506 let EncoderMethod = "getMSAMemEncoding";
509 def mem_simm9 : mem_generic {
510 let MIOperandInfo = (ops ptr_rc, simm9);
511 let EncoderMethod = "getMemEncoding";
512 let ParserMatchClass = MipsMemSimm9AsmOperand;
515 def mem_simm11 : mem_generic {
516 let MIOperandInfo = (ops ptr_rc, simm11);
517 let EncoderMethod = "getMemEncoding";
518 let ParserMatchClass = MipsMemSimm11AsmOperand;
521 def mem_simm16 : mem_generic {
522 let MIOperandInfo = (ops ptr_rc, simm16);
523 let EncoderMethod = "getMemEncoding";
524 let ParserMatchClass = MipsMemSimm16AsmOperand;
527 def mem_ea : Operand<iPTR> {
528 let PrintMethod = "printMemOperandEA";
529 let MIOperandInfo = (ops ptr_rc, simm16);
530 let EncoderMethod = "getMemEncoding";
531 let OperandType = "OPERAND_MEMORY";
534 def PtrRC : Operand<iPTR> {
535 let MIOperandInfo = (ops ptr_rc);
536 let DecoderMethod = "DecodePtrRegisterClass";
537 let ParserMatchClass = GPR32AsmOperand;
540 // size operand of ext instruction
541 def size_ext : Operand<i32> {
542 let EncoderMethod = "getSizeExtEncoding";
543 let DecoderMethod = "DecodeExtSize";
546 // size operand of ins instruction
547 def size_ins : Operand<i32> {
548 let EncoderMethod = "getSizeInsEncoding";
549 let DecoderMethod = "DecodeInsSize";
552 // Transformation Function - get the lower 16 bits.
553 def LO16 : SDNodeXForm<imm, [{
554 return getImm(N, N->getZExtValue() & 0xFFFF);
557 // Transformation Function - get the higher 16 bits.
558 def HI16 : SDNodeXForm<imm, [{
559 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
563 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
565 // Node immediate is zero (e.g. insve.d)
566 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
568 // Node immediate fits as 16-bit sign extended on target immediate.
570 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
572 // Node immediate fits as 16-bit sign extended on target immediate.
574 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
576 // Node immediate fits as 15-bit sign extended on target immediate.
578 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
580 // Node immediate fits as 16-bit zero extended on target immediate.
581 // The LO16 param means that only the lower 16 bits of the node
582 // immediate are caught.
584 def immZExt16 : PatLeaf<(imm), [{
585 if (N->getValueType(0) == MVT::i32)
586 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
588 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
591 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
592 def immLow16Zero : PatLeaf<(imm), [{
593 int64_t Val = N->getSExtValue();
594 return isInt<32>(Val) && !(Val & 0xffff);
597 // shamt field must fit in 5 bits.
598 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
600 // True if (N + 1) fits in 16-bit field.
601 def immSExt16Plus1 : PatLeaf<(imm), [{
602 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
605 // Mips Address Mode! SDNode frameindex could possibily be a match
606 // since load and store instructions from stack used it.
608 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
611 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
614 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
617 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
619 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
621 //===----------------------------------------------------------------------===//
622 // Instructions specific format
623 //===----------------------------------------------------------------------===//
625 // Arithmetic and logical instructions with 3 register operands.
626 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
627 InstrItinClass Itin = NoItinerary,
628 SDPatternOperator OpNode = null_frag>:
629 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
630 !strconcat(opstr, "\t$rd, $rs, $rt"),
631 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
632 let isCommutable = isComm;
633 let isReMaterializable = 1;
634 let TwoOperandAliasConstraint = "$rd = $rs";
637 // Arithmetic and logical instructions with 2 register operands.
638 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
639 InstrItinClass Itin = NoItinerary,
640 SDPatternOperator imm_type = null_frag,
641 SDPatternOperator OpNode = null_frag> :
642 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
643 !strconcat(opstr, "\t$rt, $rs, $imm16"),
644 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
646 let isReMaterializable = 1;
647 let TwoOperandAliasConstraint = "$rs = $rt";
650 // Arithmetic Multiply ADD/SUB
651 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
652 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
653 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
654 let Defs = [HI0, LO0];
655 let Uses = [HI0, LO0];
656 let isCommutable = isComm;
660 class LogicNOR<string opstr, RegisterOperand RO>:
661 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
662 !strconcat(opstr, "\t$rd, $rs, $rt"),
663 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
664 let isCommutable = 1;
668 class shift_rotate_imm<string opstr, Operand ImmOpnd,
669 RegisterOperand RO, InstrItinClass itin,
670 SDPatternOperator OpNode = null_frag,
671 SDPatternOperator PF = null_frag> :
672 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
673 !strconcat(opstr, "\t$rd, $rt, $shamt"),
674 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
675 let TwoOperandAliasConstraint = "$rt = $rd";
678 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
679 SDPatternOperator OpNode = null_frag>:
680 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
681 !strconcat(opstr, "\t$rd, $rt, $rs"),
682 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
685 // Load Upper Immediate
686 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
687 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
688 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
689 let hasSideEffects = 0;
690 let isReMaterializable = 1;
694 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
695 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
696 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
697 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
698 let DecoderMethod = "DecodeMem";
699 let canFoldAsLoad = 1;
703 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
704 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
705 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
706 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
707 let DecoderMethod = "DecodeMem";
711 // Load/Store Left/Right
712 let canFoldAsLoad = 1 in
713 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
714 InstrItinClass Itin> :
715 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
716 !strconcat(opstr, "\t$rt, $addr"),
717 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
718 let DecoderMethod = "DecodeMem";
719 string Constraints = "$src = $rt";
722 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
723 InstrItinClass Itin> :
724 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
725 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
726 let DecoderMethod = "DecodeMem";
730 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
731 SDPatternOperator OpNode= null_frag> :
732 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
733 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
734 let DecoderMethod = "DecodeFMem2";
738 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
739 SDPatternOperator OpNode= null_frag> :
740 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
741 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
742 let DecoderMethod = "DecodeFMem2";
747 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
748 SDPatternOperator OpNode= null_frag> :
749 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
750 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
751 let DecoderMethod = "DecodeFMem3";
755 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
756 SDPatternOperator OpNode= null_frag> :
757 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
758 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
759 let DecoderMethod = "DecodeFMem3";
763 // Conditional Branch
764 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
765 RegisterOperand RO, bit DelaySlot = 1> :
766 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
767 !strconcat(opstr, "\t$rs, $rt, $offset"),
768 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
771 let isTerminator = 1;
772 let hasDelaySlot = DelaySlot;
776 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
777 RegisterOperand RO, bit DelaySlot = 1> :
778 InstSE<(outs), (ins RO:$rs, opnd:$offset),
779 !strconcat(opstr, "\t$rs, $offset"),
780 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
783 let isTerminator = 1;
784 let hasDelaySlot = DelaySlot;
789 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
790 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
791 !strconcat(opstr, "\t$rd, $rs, $rt"),
792 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
793 II_SLT_SLTU, FrmR, opstr>;
795 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
797 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
798 !strconcat(opstr, "\t$rt, $rs, $imm16"),
799 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
800 II_SLTI_SLTIU, FrmI, opstr>;
803 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
804 SDPatternOperator targetoperator, string bopstr> :
805 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
806 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
809 let hasDelaySlot = 1;
810 let DecoderMethod = "DecodeJumpTarget";
814 // Unconditional branch
815 class UncondBranch<Instruction BEQInst> :
816 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
817 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
819 let isTerminator = 1;
821 let hasDelaySlot = 1;
822 let AdditionalPredicates = [RelocPIC];
826 // Base class for indirect branch and return instruction classes.
827 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
828 class JumpFR<string opstr, RegisterOperand RO,
829 SDPatternOperator operator = null_frag>:
830 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
834 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
836 let isIndirectBranch = 1;
839 // Jump and Link (Call)
840 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
841 class JumpLink<string opstr, DAGOperand opnd> :
842 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
843 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
844 let DecoderMethod = "DecodeJumpTarget";
847 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
848 Register RetReg, RegisterOperand ResRO = RO>:
849 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
850 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
852 class JumpLinkReg<string opstr, RegisterOperand RO>:
853 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
856 class BGEZAL_FT<string opstr, DAGOperand opnd,
857 RegisterOperand RO, bit DelaySlot = 1> :
858 InstSE<(outs), (ins RO:$rs, opnd:$offset),
859 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
860 let hasDelaySlot = DelaySlot;
865 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
866 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
867 class TailCall<Instruction JumpInst> :
868 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
869 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
871 class TailCallReg<RegisterOperand RO, Instruction JRInst,
872 RegisterOperand ResRO = RO> :
873 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
874 PseudoInstExpansion<(JRInst ResRO:$rs)>;
877 class BAL_BR_Pseudo<Instruction RealInst> :
878 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
879 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
881 let isTerminator = 1;
883 let hasDelaySlot = 1;
888 class SYS_FT<string opstr> :
889 InstSE<(outs), (ins uimm20:$code_),
890 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
892 class BRK_FT<string opstr> :
893 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
894 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
898 class ER_FT<string opstr> :
899 InstSE<(outs), (ins),
900 opstr, [], NoItinerary, FrmOther, opstr>;
903 class DEI_FT<string opstr, RegisterOperand RO> :
904 InstSE<(outs RO:$rt), (ins),
905 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
908 class WAIT_FT<string opstr> :
909 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
912 let hasSideEffects = 1 in
913 class SYNC_FT<string opstr> :
914 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
915 NoItinerary, FrmOther, opstr>;
917 class SYNCI_FT<string opstr> :
918 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
919 NoItinerary, FrmOther, opstr> {
920 let hasSideEffects = 1;
921 let DecoderMethod = "DecodeSyncI";
924 let hasSideEffects = 1 in
925 class TEQ_FT<string opstr, RegisterOperand RO> :
926 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
927 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
930 class TEQI_FT<string opstr, RegisterOperand RO> :
931 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
932 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
934 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
935 list<Register> DefRegs> :
936 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
938 let isCommutable = 1;
940 let hasSideEffects = 0;
943 // Pseudo multiply/divide instruction with explicit accumulator register
945 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
946 SDPatternOperator OpNode, InstrItinClass Itin,
947 bit IsComm = 1, bit HasSideEffects = 0,
948 bit UsesCustomInserter = 0> :
949 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
950 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
951 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
952 let isCommutable = IsComm;
953 let hasSideEffects = HasSideEffects;
954 let usesCustomInserter = UsesCustomInserter;
957 // Pseudo multiply add/sub instruction with explicit accumulator register
959 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
961 : PseudoSE<(outs ACC64:$ac),
962 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
964 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
966 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
967 string Constraints = "$acin = $ac";
970 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
971 list<Register> DefRegs> :
972 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
973 [], itin, FrmR, opstr> {
978 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
979 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
980 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
982 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
983 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
986 let hasSideEffects = 0;
989 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
990 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
991 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
994 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
995 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
998 let hasSideEffects = 0;
1001 class EffectiveAddress<string opstr, RegisterOperand RO> :
1002 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
1003 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
1004 !strconcat(opstr, "_lea")> {
1005 let isCodeGenOnly = 1;
1006 let DecoderMethod = "DecodeMem";
1009 // Count Leading Ones/Zeros in Word
1010 class CountLeading0<string opstr, RegisterOperand RO>:
1011 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1012 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
1014 class CountLeading1<string opstr, RegisterOperand RO>:
1015 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
1016 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
1018 // Sign Extend in Register.
1019 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
1020 InstrItinClass itin> :
1021 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
1022 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1025 class SubwordSwap<string opstr, RegisterOperand RO>:
1026 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
1027 NoItinerary, FrmR, opstr> {
1028 let hasSideEffects = 0;
1032 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1033 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1034 II_RDHWR, FrmR, "rdhwr">;
1037 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1038 SDPatternOperator Op = null_frag>:
1039 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1040 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1041 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1042 FrmR, opstr>, ISA_MIPS32R2;
1044 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1045 SDPatternOperator Op = null_frag>:
1046 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1047 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1048 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1049 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1050 let Constraints = "$src = $rt";
1053 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1054 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1055 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1056 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1058 // Atomic Compare & Swap.
1059 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1060 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1061 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1063 class LLBase<string opstr, RegisterOperand RO> :
1064 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1065 [], NoItinerary, FrmI> {
1066 let DecoderMethod = "DecodeMem";
1070 class SCBase<string opstr, RegisterOperand RO> :
1071 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1072 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1073 let DecoderMethod = "DecodeMem";
1075 let Constraints = "$rt = $dst";
1078 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1079 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1080 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1082 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1083 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1084 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1086 class TrapBase<Instruction RealInst>
1087 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1088 PseudoInstExpansion<(RealInst 0, 0)> {
1090 let isTerminator = 1;
1091 let isCodeGenOnly = 1;
1094 //===----------------------------------------------------------------------===//
1095 // Pseudo instructions
1096 //===----------------------------------------------------------------------===//
1099 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1100 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1102 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1103 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1104 [(callseq_start timm:$amt)]>;
1105 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1106 [(callseq_end timm:$amt1, timm:$amt2)]>;
1109 let usesCustomInserter = 1 in {
1110 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1111 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1112 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1113 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1114 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1115 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1116 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1117 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1118 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1119 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1120 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1121 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1122 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1123 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1124 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1125 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1126 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1127 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1129 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1130 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1131 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1133 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1134 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1135 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1138 /// Pseudo instructions for loading and storing accumulator registers.
1139 let isPseudo = 1, isCodeGenOnly = 1 in {
1140 def LOAD_ACC64 : Load<"", ACC64>;
1141 def STORE_ACC64 : Store<"", ACC64>;
1144 // We need these two pseudo instructions to avoid offset calculation for long
1145 // branches. See the comment in file MipsLongBranch.cpp for detailed
1148 // Expands to: lui $dst, %hi($tgt - $baltgt)
1149 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1150 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1152 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1153 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1154 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1156 //===----------------------------------------------------------------------===//
1157 // Instruction definition
1158 //===----------------------------------------------------------------------===//
1159 //===----------------------------------------------------------------------===//
1160 // MipsI Instructions
1161 //===----------------------------------------------------------------------===//
1163 /// Arithmetic Instructions (ALU Immediate)
1164 let AdditionalPredicates = [NotInMicroMips] in {
1165 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1166 II_ADDIU, immSExt16, add>,
1167 ADDI_FM<0x9>, IsAsCheapAsAMove;
1169 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1170 ISA_MIPS1_NOT_32R6_64R6;
1171 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1173 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1175 let AdditionalPredicates = [NotInMicroMips] in {
1176 def ANDi : MMRel, StdMMR6Rel,
1177 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1180 def ORi : MMRel, StdMMR6Rel,
1181 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1183 def XORi : MMRel, StdMMR6Rel,
1184 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1186 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1187 let AdditionalPredicates = [NotInMicroMips] in {
1188 /// Arithmetic Instructions (3-Operand, R-Type)
1189 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1191 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1194 let Defs = [HI0, LO0] in
1195 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1196 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1197 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1198 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1199 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1200 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1201 let AdditionalPredicates = [NotInMicroMips] in {
1202 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1204 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1206 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1209 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1211 /// Shift Instructions
1212 let AdditionalPredicates = [NotInMicroMips] in {
1213 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1214 immZExt5>, SRA_FM<0, 0>;
1215 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1216 immZExt5>, SRA_FM<2, 0>;
1218 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1219 immZExt5>, SRA_FM<3, 0>;
1220 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1222 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1224 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1227 // Rotate Instructions
1228 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1230 SRA_FM<2, 1>, ISA_MIPS32R2;
1231 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1232 SRLV_FM<6, 1>, ISA_MIPS32R2;
1234 /// Load and Store Instructions
1236 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1237 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1239 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1241 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1242 let AdditionalPredicates = [NotInMicroMips] in {
1243 def LW : StdMMR6Rel, Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1246 def SB : StdMMR6Rel, Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel,
1248 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1249 let AdditionalPredicates = [NotInMicroMips] in {
1250 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1253 /// load/store left/right
1254 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1255 AdditionalPredicates = [NotInMicroMips] in {
1256 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1257 ISA_MIPS1_NOT_32R6_64R6;
1258 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1259 ISA_MIPS1_NOT_32R6_64R6;
1260 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1261 ISA_MIPS1_NOT_32R6_64R6;
1262 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1263 ISA_MIPS1_NOT_32R6_64R6;
1266 let AdditionalPredicates = [NotInMicroMips] in {
1267 // COP2 Memory Instructions
1268 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1269 ISA_MIPS1_NOT_32R6_64R6;
1270 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1271 ISA_MIPS1_NOT_32R6_64R6;
1272 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1273 ISA_MIPS2_NOT_32R6_64R6;
1274 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1275 ISA_MIPS2_NOT_32R6_64R6;
1277 // COP3 Memory Instructions
1278 let DecoderNamespace = "COP3_" in {
1279 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1280 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1281 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1283 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1288 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1289 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1291 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1292 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1293 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1294 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1295 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1296 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1298 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1299 ISA_MIPS2_NOT_32R6_64R6;
1300 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1301 ISA_MIPS2_NOT_32R6_64R6;
1302 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1303 ISA_MIPS2_NOT_32R6_64R6;
1304 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1305 ISA_MIPS2_NOT_32R6_64R6;
1306 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1307 ISA_MIPS2_NOT_32R6_64R6;
1308 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1309 ISA_MIPS2_NOT_32R6_64R6;
1311 let AdditionalPredicates = [NotInMicroMips] in {
1312 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1314 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1315 def TRAP : TrapBase<BREAK>;
1316 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1318 let AdditionalPredicates = [NotInMicroMips] in {
1319 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18, 0x0>, INSN_MIPS3_32;
1320 def ERETNC : MMRel, ER_FT<"eretnc">, ER_FM<0x18, 0x1>, ISA_MIPS32R5;
1322 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f, 0x0>, ISA_MIPS32;
1324 let AdditionalPredicates = [NotInMicroMips] in {
1325 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1327 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1329 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1330 AdditionalPredicates = [NotInMicroMips] in {
1331 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1333 /// Load-linked, Store-conditional
1334 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1335 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1338 /// Jump and Branch Instructions
1339 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1340 AdditionalRequires<[RelocStatic]>, IsBranch;
1341 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1342 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1343 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1344 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1345 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1346 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1347 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1348 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1350 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1351 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1352 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1354 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1355 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1356 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1358 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1359 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1360 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1362 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1363 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1364 def B : UncondBranch<BEQ>;
1366 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1367 let AdditionalPredicates = [NotInMicroMips] in {
1368 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1369 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1372 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1373 ISA_MIPS32_NOT_32R6_64R6;
1374 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1375 ISA_MIPS1_NOT_32R6_64R6;
1376 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1377 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1378 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1379 ISA_MIPS1_NOT_32R6_64R6;
1380 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1381 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1382 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1383 def TAILCALL : TailCall<J>;
1384 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1386 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1387 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1388 class PseudoIndirectBranchBase<RegisterOperand RO> :
1389 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1392 let hasDelaySlot = 1;
1394 let isIndirectBranch = 1;
1397 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1399 // Return instructions are matched as a RetRA instruction, then ar expanded
1400 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1401 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1403 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1405 let isTerminator = 1;
1407 let hasDelaySlot = 1;
1409 let isCodeGenOnly = 1;
1411 let hasExtraSrcRegAllocReq = 1;
1414 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1416 // Exception handling related node and instructions.
1417 // The conversion sequence is:
1418 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1419 // MIPSeh_return -> (stack change + indirect branch)
1421 // MIPSeh_return takes the place of regular return instruction
1422 // but takes two arguments (V1, V0) which are used for storing
1423 // the offset and return address respectively.
1424 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1426 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1427 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1429 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1430 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1431 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1432 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1434 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1437 /// Multiply and Divide Instructions.
1438 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1439 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1440 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1441 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1442 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1443 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1444 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1445 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1447 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1448 ISA_MIPS1_NOT_32R6_64R6;
1449 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1450 ISA_MIPS1_NOT_32R6_64R6;
1451 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1452 AdditionalPredicates = [NotInMicroMips] in {
1453 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1454 ISA_MIPS1_NOT_32R6_64R6;
1455 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1456 ISA_MIPS1_NOT_32R6_64R6;
1459 /// Sign Ext In Register Instructions.
1460 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1461 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1462 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1463 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1466 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1467 ISA_MIPS32_NOT_32R6_64R6;
1468 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1469 ISA_MIPS32_NOT_32R6_64R6;
1471 /// Word Swap Bytes Within Halfwords
1472 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1475 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1477 // FrameIndexes are legalized when they are operands from load/store
1478 // instructions. The same not happens for stack address copies, so an
1479 // add op with mem ComplexPattern is used and the stack address copy
1480 // can be matched. It's similar to Sparc LEA_ADDRi
1481 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1484 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1485 ISA_MIPS32_NOT_32R6_64R6;
1486 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1487 ISA_MIPS32_NOT_32R6_64R6;
1488 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1489 ISA_MIPS32_NOT_32R6_64R6;
1490 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1491 ISA_MIPS32_NOT_32R6_64R6;
1493 let AdditionalPredicates = [NotDSP] in {
1494 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1495 ISA_MIPS1_NOT_32R6_64R6;
1496 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1497 ISA_MIPS1_NOT_32R6_64R6;
1498 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1499 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1500 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1501 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1502 ISA_MIPS32_NOT_32R6_64R6;
1503 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1504 ISA_MIPS32_NOT_32R6_64R6;
1505 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1506 ISA_MIPS32_NOT_32R6_64R6;
1507 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1508 ISA_MIPS32_NOT_32R6_64R6;
1511 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1512 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1513 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1514 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1516 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1518 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1519 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1521 /// Move Control Registers From/To CPU Registers
1522 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1523 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1524 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1525 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1527 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1529 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1530 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1531 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1533 // JR_HB and JALR_HB are defined here using the new style naming
1534 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1535 // and because of that it doesn't follow the naming convention of the
1536 // rest of the file. To avoid a mixture of old vs new style, the new
1537 // style was chosen.
1538 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1539 dag OutOperandList = (outs);
1540 dag InOperandList = (ins GPROpnd:$rs);
1541 string AsmString = !strconcat(instr_asm, "\t$rs");
1542 list<dag> Pattern = [];
1545 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1546 dag OutOperandList = (outs GPROpnd:$rd);
1547 dag InOperandList = (ins GPROpnd:$rs);
1548 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1549 list<dag> Pattern = [];
1552 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1553 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1555 let isIndirectBranch=1;
1561 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1562 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1563 let isIndirectBranch=1;
1567 class JR_HB_ENC : JR_HB_FM<8>;
1568 class JALR_HB_ENC : JALR_HB_FM<9>;
1570 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1571 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1573 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1575 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1576 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1577 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1578 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1580 class CacheOp<string instr_asm, Operand MemOpnd> :
1581 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1582 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1584 let DecoderMethod = "DecodeCacheOp";
1587 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1588 INSN_MIPS3_32_NOT_32R6_64R6;
1589 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1590 INSN_MIPS3_32_NOT_32R6_64R6;
1592 //===----------------------------------------------------------------------===//
1593 // Instruction aliases
1594 //===----------------------------------------------------------------------===//
1595 def : MipsInstAlias<"move $dst, $src",
1596 (OR GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1598 let AdditionalPredicates = [NotInMicroMips];
1600 def : MipsInstAlias<"move $dst, $src",
1601 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src, ZERO), 1>,
1603 let AdditionalPredicates = [NotInMicroMips];
1605 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1606 ISA_MIPS1_NOT_32R6_64R6;
1607 def : MipsInstAlias<"addu $rs, $rt, $imm",
1608 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1609 def : MipsInstAlias<"addu $rs, $imm",
1610 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1611 def : MipsInstAlias<"add $rs, $rt, $imm",
1612 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1613 ISA_MIPS1_NOT_32R6_64R6;
1614 def : MipsInstAlias<"add $rs, $imm",
1615 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1616 ISA_MIPS1_NOT_32R6_64R6;
1617 def : MipsInstAlias<"and $rs, $rt, $imm",
1618 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1619 def : MipsInstAlias<"and $rs, $imm",
1620 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1621 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1622 let Predicates = [NotInMicroMips] in {
1623 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1625 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1626 def : MipsInstAlias<"not $rt, $rs",
1627 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1628 def : MipsInstAlias<"neg $rt, $rs",
1629 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1630 def : MipsInstAlias<"negu $rt",
1631 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1632 def : MipsInstAlias<"negu $rt, $rs",
1633 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1634 def : MipsInstAlias<"slt $rs, $rt, $imm",
1635 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1636 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1637 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1638 def : MipsInstAlias<"xor $rs, $rt, $imm",
1639 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1640 def : MipsInstAlias<"xor $rs, $imm",
1641 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1642 def : MipsInstAlias<"or $rs, $rt, $imm",
1643 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1644 def : MipsInstAlias<"or $rs, $imm",
1645 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1646 let AdditionalPredicates = [NotInMicroMips] in {
1647 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1649 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1650 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1651 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1652 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1653 let AdditionalPredicates = [NotInMicroMips] in {
1654 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1656 def : MipsInstAlias<"bnez $rs,$offset",
1657 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1658 def : MipsInstAlias<"bnezl $rs,$offset",
1659 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1660 def : MipsInstAlias<"beqz $rs,$offset",
1661 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1662 def : MipsInstAlias<"beqzl $rs,$offset",
1663 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1664 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1666 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1667 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1668 let AdditionalPredicates = [NotInMicroMips] in {
1669 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1671 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1673 def : MipsInstAlias<"teq $rs, $rt",
1674 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1675 def : MipsInstAlias<"tge $rs, $rt",
1676 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1677 def : MipsInstAlias<"tgeu $rs, $rt",
1678 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1679 def : MipsInstAlias<"tlt $rs, $rt",
1680 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1681 def : MipsInstAlias<"tltu $rs, $rt",
1682 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1683 def : MipsInstAlias<"tne $rs, $rt",
1684 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1686 def : MipsInstAlias<"sll $rd, $rt, $rs",
1687 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1688 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1689 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1690 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1691 def : MipsInstAlias<"sub $rs, $imm",
1692 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1693 0>, ISA_MIPS1_NOT_32R6_64R6;
1694 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1695 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1696 InvertedImOperand:$imm), 0>;
1697 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1698 InvertedImOperand:$imm), 0>;
1699 def : MipsInstAlias<"sra $rd, $rt, $rs",
1700 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1701 def : MipsInstAlias<"srl $rd, $rt, $rs",
1702 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1703 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1704 def : MipsInstAlias<"sync",
1705 (SYNC 0), 1>, ISA_MIPS2;
1706 //===----------------------------------------------------------------------===//
1707 // Assembler Pseudo Instructions
1708 //===----------------------------------------------------------------------===//
1710 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1711 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1712 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1713 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1715 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1716 RegisterOperand RO> :
1717 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1718 !strconcat(instr_asm, "\t$rt, $addr")> ;
1719 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1721 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1722 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1723 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1724 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1726 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1728 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1731 let hasDelaySlot = 1 in {
1732 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1733 (ins imm64:$imm64, brtarget:$offset),
1734 "bne\t$rt, $imm64, $offset">;
1735 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1736 (ins imm64:$imm64, brtarget:$offset),
1737 "beq\t$rt, $imm64, $offset">;
1739 class CondBranchPseudo<string instr_asm> :
1740 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1742 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1745 def BLT : CondBranchPseudo<"blt">;
1746 def BLE : CondBranchPseudo<"ble">;
1747 def BGE : CondBranchPseudo<"bge">;
1748 def BGT : CondBranchPseudo<"bgt">;
1749 def BLTU : CondBranchPseudo<"bltu">;
1750 def BLEU : CondBranchPseudo<"bleu">;
1751 def BGEU : CondBranchPseudo<"bgeu">;
1752 def BGTU : CondBranchPseudo<"bgtu">;
1754 def SDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1755 "div\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
1757 def UDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1758 "divu\t$rs, $rt">, ISA_MIPS1_NOT_32R6_64R6;
1760 def DSDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1761 "ddiv\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
1763 def DUDivMacro : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
1764 "ddivu\t$rs, $rt">, ISA_MIPS64_NOT_64R6;
1766 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1767 "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
1769 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1770 "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
1772 //===----------------------------------------------------------------------===//
1773 // Arbitrary patterns that map to one or more instructions
1774 //===----------------------------------------------------------------------===//
1776 // Load/store pattern templates.
1777 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1778 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1780 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1781 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1784 let AdditionalPredicates = [NotInMicroMips] in {
1785 def : MipsPat<(i32 immSExt16:$in),
1786 (ADDiu ZERO, imm:$in)>;
1787 def : MipsPat<(i32 immZExt16:$in),
1788 (ORi ZERO, imm:$in)>;
1790 def : MipsPat<(i32 immLow16Zero:$in),
1791 (LUi (HI16 imm:$in))>;
1793 // Arbitrary immediates
1794 def : MipsPat<(i32 imm:$imm),
1795 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1797 // Carry MipsPatterns
1798 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1799 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1800 let AdditionalPredicates = [NotDSP] in {
1801 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1802 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1803 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1804 (ADDiu GPR32:$src, imm:$imm)>;
1807 // Support multiplication for pre-Mips32 targets that don't have
1808 // the MUL instruction.
1809 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1810 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1811 ISA_MIPS1_NOT_32R6_64R6;
1814 def : MipsPat<(MipsSync (i32 immz)),
1815 (SYNC 0)>, ISA_MIPS2;
1818 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1819 (JAL tglobaladdr:$dst)>;
1820 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1821 (JAL texternalsym:$dst)>;
1822 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1823 // (JALR GPR32:$dst)>;
1826 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1827 (TAILCALL tglobaladdr:$dst)>;
1828 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1829 (TAILCALL texternalsym:$dst)>;
1831 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1832 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1833 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1834 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1835 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1836 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1838 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1839 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1840 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1841 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1842 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1843 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1845 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1846 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1847 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1848 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1849 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1850 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1851 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1852 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1853 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1854 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1857 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1858 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1859 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1860 (ADDiu GPR32:$gp, tconstpool:$in)>;
1863 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1864 MipsPat<(MipsWrapper RC:$gp, node:$in),
1865 (ADDiuOp RC:$gp, node:$in)>;
1867 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1868 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1869 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1870 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1871 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1872 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1874 let AdditionalPredicates = [NotInMicroMips] in {
1875 // Mips does not have "not", so we expand our way
1876 def : MipsPat<(not GPR32:$in),
1877 (NOR GPR32Opnd:$in, ZERO)>;
1881 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1882 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1883 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1886 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1889 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1890 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1891 Instruction SLTiuOp, Register ZEROReg> {
1892 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1893 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1894 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1895 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1897 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1898 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1899 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1900 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1901 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1902 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1903 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1904 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1905 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1906 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1907 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1908 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1910 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1911 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1912 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1913 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1915 def : MipsPat<(brcond RC:$cond, bb:$dst),
1916 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1919 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1921 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1922 (BLEZ i32:$lhs, bb:$dst)>;
1923 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1924 (BGEZ i32:$lhs, bb:$dst)>;
1927 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1928 Instruction SLTuOp, Register ZEROReg> {
1929 def : MipsPat<(seteq RC:$lhs, 0),
1930 (SLTiuOp RC:$lhs, 1)>;
1931 def : MipsPat<(setne RC:$lhs, 0),
1932 (SLTuOp ZEROReg, RC:$lhs)>;
1933 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1934 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1935 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1936 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1939 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1940 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1941 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1942 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1943 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1946 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1947 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1948 (SLTOp RC:$rhs, RC:$lhs)>;
1949 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1950 (SLTuOp RC:$rhs, RC:$lhs)>;
1953 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1954 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1955 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1956 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1957 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1960 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1961 Instruction SLTiuOp> {
1962 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1963 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1964 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1965 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1968 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1969 defm : SetlePats<GPR32, SLT, SLTu>;
1970 defm : SetgtPats<GPR32, SLT, SLTu>;
1971 defm : SetgePats<GPR32, SLT, SLTu>;
1972 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1975 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1977 // Load halfword/word patterns.
1978 let AddedComplexity = 40 in {
1979 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1980 def : LoadRegImmPat<LH, i32, sextloadi16>;
1981 let AdditionalPredicates = [NotInMicroMips] in {
1982 def : LoadRegImmPat<LW, i32, load>;
1986 //===----------------------------------------------------------------------===//
1987 // Floating Point Support
1988 //===----------------------------------------------------------------------===//
1990 include "MipsInstrFPU.td"
1991 include "Mips64InstrInfo.td"
1992 include "MipsCondMov.td"
1994 include "Mips32r6InstrInfo.td"
1995 include "Mips64r6InstrInfo.td"
2000 include "Mips16InstrFormats.td"
2001 include "Mips16InstrInfo.td"
2004 include "MipsDSPInstrFormats.td"
2005 include "MipsDSPInstrInfo.td"
2008 include "MipsMSAInstrFormats.td"
2009 include "MipsMSAInstrInfo.td"
2012 include "MicroMipsInstrFormats.td"
2013 include "MicroMipsInstrInfo.td"
2014 include "MicroMipsInstrFPU.td"
2017 include "MicroMips32r6InstrFormats.td"
2018 include "MicroMips32r6InstrInfo.td"
2021 include "MicroMips64r6InstrFormats.td"
2022 include "MicroMips64r6InstrInfo.td"