1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_ExtractLOHI : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVT<1, untyped>,
28 def SDT_InsertLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
29 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
30 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
32 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
33 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
34 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
35 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
37 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
39 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
41 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
43 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
47 def SDTMipsLoadLR : SDTypeProfile<1, 2,
48 [SDTCisInt<0>, SDTCisPtrTy<1>,
52 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
53 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
58 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
60 // Hi and Lo nodes are used to handle global addresses. Used on
61 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
62 // static model. (nothing to do with Mips Registers Hi and Lo)
63 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
64 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
65 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
67 // TlsGd node is used to handle General Dynamic TLS
68 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
70 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
71 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
72 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
75 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
78 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
79 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
81 // These are target-independent nodes, but have target-specific formats.
82 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
83 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
84 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
85 [SDNPHasChain, SDNPSideEffect,
86 SDNPOptInGlue, SDNPOutGlue]>;
88 // Node used to extract integer from LO/HI register.
89 def ExtractLOHI : SDNode<"MipsISD::ExtractLOHI", SDT_ExtractLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def InsertLOHI : SDNode<"MipsISD::InsertLOHI", SDT_InsertLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16, [SDNPOutGlue]>;
108 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
111 // Target constant nodes that are not part of any isel patterns and remain
112 // unchanged can cause instructions with illegal operands to be emitted.
113 // Wrapper node patterns give the instruction selector a chance to replace
114 // target constant nodes that would otherwise remain unchanged with ADDiu
115 // nodes. Without these wrapper node patterns, the following conditional move
116 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
118 // movn %got(d)($gp), %got(c)($gp), $4
119 // This instruction is illegal since movn can take only register operands.
121 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
123 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
125 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
126 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
128 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
131 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
132 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
135 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
136 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
137 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
138 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
139 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
140 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
141 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
142 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
143 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
145 //===----------------------------------------------------------------------===//
146 // Mips Instruction Predicate Definitions.
147 //===----------------------------------------------------------------------===//
148 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
149 AssemblerPredicate<"FeatureSEInReg">;
150 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
151 AssemblerPredicate<"FeatureBitCount">;
152 def HasSwap : Predicate<"Subtarget.hasSwap()">,
153 AssemblerPredicate<"FeatureSwap">;
154 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
155 AssemblerPredicate<"FeatureCondMov">;
156 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
157 AssemblerPredicate<"FeatureFPIdx">;
158 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
159 AssemblerPredicate<"FeatureMips32">;
160 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
161 AssemblerPredicate<"FeatureMips32r2">;
162 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
163 AssemblerPredicate<"FeatureMips64">;
164 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
165 AssemblerPredicate<"!FeatureMips64">;
166 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
167 AssemblerPredicate<"FeatureMips64r2">;
168 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
169 AssemblerPredicate<"FeatureN64">;
170 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
171 AssemblerPredicate<"!FeatureN64">;
172 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
173 AssemblerPredicate<"FeatureMips16">;
174 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
175 AssemblerPredicate<"FeatureMips32">;
176 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
177 AssemblerPredicate<"FeatureMips32">;
178 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
179 AssemblerPredicate<"FeatureMips32">;
180 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
181 AssemblerPredicate<"!FeatureMips16">;
182 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
185 let Predicates = [HasStdEnc];
189 bit isCommutable = 1;
206 bit isTerminator = 1;
209 bit hasExtraSrcRegAllocReq = 1;
210 bit isCodeGenOnly = 1;
213 class IsAsCheapAsAMove {
214 bit isAsCheapAsAMove = 1;
217 class NeverHasSideEffects {
218 bit neverHasSideEffects = 1;
221 //===----------------------------------------------------------------------===//
222 // Instruction format superclass
223 //===----------------------------------------------------------------------===//
225 include "MipsInstrFormats.td"
227 //===----------------------------------------------------------------------===//
228 // Mips Operand, Complex Patterns and Transformations Definitions.
229 //===----------------------------------------------------------------------===//
231 // Instruction operand types
232 def jmptarget : Operand<OtherVT> {
233 let EncoderMethod = "getJumpTargetOpValue";
235 def brtarget : Operand<OtherVT> {
236 let EncoderMethod = "getBranchTargetOpValue";
237 let OperandType = "OPERAND_PCREL";
238 let DecoderMethod = "DecodeBranchTarget";
240 def calltarget : Operand<iPTR> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def calltarget64: Operand<i64>;
244 def simm16 : Operand<i32> {
245 let DecoderMethod= "DecodeSimm16";
248 def simm20 : Operand<i32> {
251 def simm16_64 : Operand<i64>;
252 def shamt : Operand<i32>;
255 def uimm16 : Operand<i32> {
256 let PrintMethod = "printUnsignedImm";
259 def MipsMemAsmOperand : AsmOperandClass {
261 let ParserMethod = "parseMemOperand";
265 def mem : Operand<i32> {
266 let PrintMethod = "printMemOperand";
267 let MIOperandInfo = (ops CPURegs, simm16);
268 let EncoderMethod = "getMemEncoding";
269 let ParserMatchClass = MipsMemAsmOperand;
270 let OperandType = "OPERAND_MEMORY";
273 def mem64 : Operand<i64> {
274 let PrintMethod = "printMemOperand";
275 let MIOperandInfo = (ops CPU64Regs, simm16_64);
276 let EncoderMethod = "getMemEncoding";
277 let ParserMatchClass = MipsMemAsmOperand;
278 let OperandType = "OPERAND_MEMORY";
281 def mem_ea : Operand<i32> {
282 let PrintMethod = "printMemOperandEA";
283 let MIOperandInfo = (ops CPURegs, simm16);
284 let EncoderMethod = "getMemEncoding";
285 let OperandType = "OPERAND_MEMORY";
288 def mem_ea_64 : Operand<i64> {
289 let PrintMethod = "printMemOperandEA";
290 let MIOperandInfo = (ops CPU64Regs, simm16_64);
291 let EncoderMethod = "getMemEncoding";
292 let OperandType = "OPERAND_MEMORY";
295 // size operand of ext instruction
296 def size_ext : Operand<i32> {
297 let EncoderMethod = "getSizeExtEncoding";
298 let DecoderMethod = "DecodeExtSize";
301 // size operand of ins instruction
302 def size_ins : Operand<i32> {
303 let EncoderMethod = "getSizeInsEncoding";
304 let DecoderMethod = "DecodeInsSize";
307 // Transformation Function - get the lower 16 bits.
308 def LO16 : SDNodeXForm<imm, [{
309 return getImm(N, N->getZExtValue() & 0xFFFF);
312 // Transformation Function - get the higher 16 bits.
313 def HI16 : SDNodeXForm<imm, [{
314 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
318 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
320 // Node immediate fits as 16-bit sign extended on target immediate.
322 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
324 // Node immediate fits as 16-bit sign extended on target immediate.
326 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
328 // Node immediate fits as 15-bit sign extended on target immediate.
330 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
332 // Node immediate fits as 16-bit zero extended on target immediate.
333 // The LO16 param means that only the lower 16 bits of the node
334 // immediate are caught.
336 def immZExt16 : PatLeaf<(imm), [{
337 if (N->getValueType(0) == MVT::i32)
338 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
340 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
343 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
344 def immLow16Zero : PatLeaf<(imm), [{
345 int64_t Val = N->getSExtValue();
346 return isInt<32>(Val) && !(Val & 0xffff);
349 // shamt field must fit in 5 bits.
350 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
352 // True if (N + 1) fits in 16-bit field.
353 def immSExt16Plus1 : PatLeaf<(imm), [{
354 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
357 // Mips Address Mode! SDNode frameindex could possibily be a match
358 // since load and store instructions from stack used it.
360 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
363 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
366 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
368 //===----------------------------------------------------------------------===//
369 // Instructions specific format
370 //===----------------------------------------------------------------------===//
372 // Arithmetic and logical instructions with 3 register operands.
373 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
374 InstrItinClass Itin = NoItinerary,
375 SDPatternOperator OpNode = null_frag>:
376 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
377 !strconcat(opstr, "\t$rd, $rs, $rt"),
378 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
379 let isCommutable = isComm;
380 let isReMaterializable = 1;
383 // Arithmetic and logical instructions with 2 register operands.
384 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
385 SDPatternOperator imm_type = null_frag,
386 SDPatternOperator OpNode = null_frag> :
387 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
388 !strconcat(opstr, "\t$rt, $rs, $imm16"),
389 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
390 IIAlu, FrmI, opstr> {
391 let isReMaterializable = 1;
394 // Arithmetic Multiply ADD/SUB
395 class MArithR<string opstr, bit isComm = 0> :
396 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
397 !strconcat(opstr, "\t$rs, $rt"), [], IIImul, FrmR> {
400 let isCommutable = isComm;
404 class LogicNOR<string opstr, RegisterOperand RC>:
405 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
406 !strconcat(opstr, "\t$rd, $rs, $rt"),
407 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR, opstr> {
408 let isCommutable = 1;
412 class shift_rotate_imm<string opstr, Operand ImmOpnd,
413 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
414 SDPatternOperator PF = null_frag> :
415 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
416 !strconcat(opstr, "\t$rd, $rt, $shamt"),
417 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR, opstr>;
419 class shift_rotate_reg<string opstr, RegisterOperand RC,
420 SDPatternOperator OpNode = null_frag>:
421 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
422 !strconcat(opstr, "\t$rd, $rt, $rs"),
423 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR, opstr>;
425 // Load Upper Imediate
426 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
427 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
428 [], IIAlu, FrmI>, IsAsCheapAsAMove {
429 let neverHasSideEffects = 1;
430 let isReMaterializable = 1;
433 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
434 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
436 let Inst{25-21} = addr{20-16};
437 let Inst{15-0} = addr{15-0};
438 let DecoderMethod = "DecodeMem";
442 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
443 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
444 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
445 [(set RC:$rt, (OpNode Addr:$addr))], NoItinerary, FrmI,
446 !strconcat(opstr, ofsuffix)> {
447 let DecoderMethod = "DecodeMem";
448 let canFoldAsLoad = 1;
452 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
453 Operand MemOpnd, ComplexPattern Addr, string ofsuffix> :
454 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
455 [(OpNode RC:$rt, Addr:$addr)], NoItinerary, FrmI,
456 !strconcat(opstr, ofsuffix)> {
457 let DecoderMethod = "DecodeMem";
461 multiclass LoadM<string opstr, RegisterClass RC,
462 SDPatternOperator OpNode = null_frag,
463 ComplexPattern Addr = addr> {
464 def NAME : Load<opstr, OpNode, RC, mem, Addr, "">,
465 Requires<[NotN64, HasStdEnc]>;
466 def _P8 : Load<opstr, OpNode, RC, mem64, Addr, "_p8">,
467 Requires<[IsN64, HasStdEnc]> {
468 let DecoderNamespace = "Mips64";
469 let isCodeGenOnly = 1;
473 multiclass StoreM<string opstr, RegisterClass RC,
474 SDPatternOperator OpNode = null_frag,
475 ComplexPattern Addr = addr> {
476 def NAME : Store<opstr, OpNode, RC, mem, Addr, "">,
477 Requires<[NotN64, HasStdEnc]>;
478 def _P8 : Store<opstr, OpNode, RC, mem64, Addr, "_p8">,
479 Requires<[IsN64, HasStdEnc]> {
480 let DecoderNamespace = "Mips64";
481 let isCodeGenOnly = 1;
485 // Load/Store Left/Right
486 let canFoldAsLoad = 1 in
487 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
489 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
490 !strconcat(opstr, "\t$rt, $addr"),
491 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
492 let DecoderMethod = "DecodeMem";
493 string Constraints = "$src = $rt";
496 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
498 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
499 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
500 let DecoderMethod = "DecodeMem";
503 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
504 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
505 Requires<[NotN64, HasStdEnc]>;
506 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
507 Requires<[IsN64, HasStdEnc]> {
508 let DecoderNamespace = "Mips64";
509 let isCodeGenOnly = 1;
513 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
514 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
515 Requires<[NotN64, HasStdEnc]>;
516 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
517 Requires<[IsN64, HasStdEnc]> {
518 let DecoderNamespace = "Mips64";
519 let isCodeGenOnly = 1;
523 // Conditional Branch
524 class CBranch<string opstr, PatFrag cond_op, RegisterOperand RC> :
525 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
526 !strconcat(opstr, "\t$rs, $rt, $offset"),
527 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
530 let isTerminator = 1;
531 let hasDelaySlot = 1;
535 class CBranchZero<string opstr, PatFrag cond_op, RegisterOperand RC> :
536 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
537 !strconcat(opstr, "\t$rs, $offset"),
538 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
540 let isTerminator = 1;
541 let hasDelaySlot = 1;
546 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
547 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
548 !strconcat(opstr, "\t$rd, $rs, $rt"),
549 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))],
552 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
554 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
555 !strconcat(opstr, "\t$rt, $rs, $imm16"),
556 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
560 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
561 SDPatternOperator targetoperator> :
562 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
563 [(operator targetoperator:$target)], IIBranch, FrmJ> {
566 let hasDelaySlot = 1;
567 let DecoderMethod = "DecodeJumpTarget";
571 // Unconditional branch
572 class UncondBranch<string opstr> :
573 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
574 [(br bb:$offset)], IIBranch, FrmI> {
576 let isTerminator = 1;
578 let hasDelaySlot = 1;
579 let Predicates = [RelocPIC, HasStdEnc];
583 // Base class for indirect branch and return instruction classes.
584 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
585 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
586 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
589 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
591 let isIndirectBranch = 1;
594 // Return instruction
595 class RetBase<RegisterClass RC>: JumpFR<RC> {
597 let isCodeGenOnly = 1;
599 let hasExtraSrcRegAllocReq = 1;
602 // Jump and Link (Call)
603 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
604 class JumpLink<string opstr> :
605 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
606 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
607 let DecoderMethod = "DecodeJumpTarget";
610 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
612 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
613 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
615 class JumpLinkReg<string opstr, RegisterClass RC>:
616 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
619 class BGEZAL_FT<string opstr, RegisterOperand RO> :
620 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
621 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
626 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
628 let isTerminator = 1;
630 let hasDelaySlot = 1;
635 let hasSideEffects = 1 in
637 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
638 NoItinerary, FrmOther>;
641 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
642 list<Register> DefRegs> :
643 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
645 let isCommutable = 1;
647 let neverHasSideEffects = 1;
650 // Pseudo multiply/divide instruction with explicit accumulator register
652 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
653 SDPatternOperator OpNode, InstrItinClass Itin,
654 bit IsComm = 1, bit HasSideEffects = 0> :
655 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
656 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
657 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
658 let isCommutable = IsComm;
659 let hasSideEffects = HasSideEffects;
662 // Pseudo multiply add/sub instruction with explicit accumulator register
664 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
665 : PseudoSE<(outs ACRegs:$ac),
666 (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin),
668 (OpNode CPURegsOpnd:$rs, CPURegsOpnd:$rt, ACRegs:$acin))],
670 PseudoInstExpansion<(RealInst CPURegsOpnd:$rs, CPURegsOpnd:$rt)> {
671 string Constraints = "$acin = $ac";
674 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
675 list<Register> DefRegs> :
676 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
682 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
683 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
685 let neverHasSideEffects = 1;
688 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
689 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
691 let neverHasSideEffects = 1;
694 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
695 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
696 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
697 let isCodeGenOnly = 1;
698 let DecoderMethod = "DecodeMem";
701 // Count Leading Ones/Zeros in Word
702 class CountLeading0<string opstr, RegisterOperand RO>:
703 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
704 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
705 Requires<[HasBitCount, HasStdEnc]>;
707 class CountLeading1<string opstr, RegisterOperand RO>:
708 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
709 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
710 Requires<[HasBitCount, HasStdEnc]>;
713 // Sign Extend in Register.
714 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
715 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
716 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
717 let Predicates = [HasSEInReg, HasStdEnc];
721 class SubwordSwap<string opstr, RegisterOperand RO>:
722 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
724 let Predicates = [HasSwap, HasStdEnc];
725 let neverHasSideEffects = 1;
729 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
730 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
734 class ExtBase<string opstr, RegisterOperand RO>:
735 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
736 !strconcat(opstr, " $rt, $rs, $pos, $size"),
737 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
739 let Predicates = [HasMips32r2, HasStdEnc];
742 class InsBase<string opstr, RegisterOperand RO>:
743 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
744 !strconcat(opstr, " $rt, $rs, $pos, $size"),
745 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
747 let Predicates = [HasMips32r2, HasStdEnc];
748 let Constraints = "$src = $rt";
751 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
752 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
753 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
754 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
756 multiclass Atomic2Ops32<PatFrag Op> {
757 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
758 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
759 Requires<[IsN64, HasStdEnc]> {
760 let DecoderNamespace = "Mips64";
764 // Atomic Compare & Swap.
765 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
766 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
767 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
769 multiclass AtomicCmpSwap32<PatFrag Op> {
770 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
771 Requires<[NotN64, HasStdEnc]>;
772 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
773 Requires<[IsN64, HasStdEnc]> {
774 let DecoderNamespace = "Mips64";
778 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
779 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
780 [], NoItinerary, FrmI> {
781 let DecoderMethod = "DecodeMem";
785 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
786 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
787 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
788 let DecoderMethod = "DecodeMem";
790 let Constraints = "$rt = $dst";
793 class MFC3OP<dag outs, dag ins, string asmstr> :
794 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
796 //===----------------------------------------------------------------------===//
797 // Pseudo instructions
798 //===----------------------------------------------------------------------===//
801 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
802 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
804 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
805 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
806 [(callseq_start timm:$amt)]>;
807 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
808 [(callseq_end timm:$amt1, timm:$amt2)]>;
811 let usesCustomInserter = 1 in {
812 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
813 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
814 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
815 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
816 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
817 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
818 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
819 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
820 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
821 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
822 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
823 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
824 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
825 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
826 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
827 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
828 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
829 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
831 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
832 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
833 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
835 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
836 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
837 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
840 /// Pseudo instructions for loading and storing accumulator registers.
841 let isPseudo = 1 in {
842 defm LOAD_AC64 : LoadM<"load_ac64", ACRegs>;
843 defm STORE_AC64 : StoreM<"store_ac64", ACRegs>;
846 //===----------------------------------------------------------------------===//
847 // Instruction definition
848 //===----------------------------------------------------------------------===//
849 //===----------------------------------------------------------------------===//
850 // MipsI Instructions
851 //===----------------------------------------------------------------------===//
853 /// Arithmetic Instructions (ALU Immediate)
854 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
855 ADDI_FM<0x9>, IsAsCheapAsAMove;
856 def ADDi : MMRel, ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
857 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>,
859 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>,
861 def ANDi : MMRel, ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
863 def ORi : MMRel, ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
865 def XORi : MMRel, ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
867 def LUi : MMRel, LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
869 /// Arithmetic Instructions (3-Operand, R-Type)
870 def ADDu : MMRel, ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>,
872 def SUBu : MMRel, ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>,
874 def MUL : MMRel, ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>,
876 def ADD : MMRel, ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
877 def SUB : MMRel, ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
878 def SLT : MMRel, SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
879 def SLTu : MMRel, SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
880 def AND : MMRel, ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>,
882 def OR : MMRel, ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>,
884 def XOR : MMRel, ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>,
886 def NOR : MMRel, LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
888 /// Shift Instructions
889 def SLL : MMRel, shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
891 def SRL : MMRel, shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
893 def SRA : MMRel, shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
895 def SLLV : MMRel, shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
896 def SRLV : MMRel, shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
897 def SRAV : MMRel, shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
899 // Rotate Instructions
900 let Predicates = [HasMips32r2, HasStdEnc] in {
901 def ROTR : MMRel, shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr,
904 def ROTRV : MMRel, shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>,
908 /// Load and Store Instructions
910 defm LB : LoadM<"lb", CPURegs, sextloadi8>, MMRel, LW_FM<0x20>;
911 defm LBu : LoadM<"lbu", CPURegs, zextloadi8, addrDefault>, MMRel, LW_FM<0x24>;
912 defm LH : LoadM<"lh", CPURegs, sextloadi16, addrDefault>, MMRel, LW_FM<0x21>;
913 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, MMRel, LW_FM<0x25>;
914 defm LW : LoadM<"lw", CPURegs, load, addrDefault>, MMRel, LW_FM<0x23>;
915 defm SB : StoreM<"sb", CPURegs, truncstorei8>, MMRel, LW_FM<0x28>;
916 defm SH : StoreM<"sh", CPURegs, truncstorei16>, MMRel, LW_FM<0x29>;
917 defm SW : StoreM<"sw", CPURegs, store>, MMRel, LW_FM<0x2b>;
919 /// load/store left/right
920 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
921 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
922 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
923 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
925 def SYNC : SYNC_FT, SYNC_FM;
927 /// Load-linked, Store-conditional
928 let Predicates = [NotN64, HasStdEnc] in {
929 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
930 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
933 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
934 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
935 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
938 /// Jump and Branch Instructions
939 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
940 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
941 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
942 def B : UncondBranch<"b">, B_FM;
943 def BEQ : CBranch<"beq", seteq, CPURegsOpnd>, BEQ_FM<4>;
944 def BNE : CBranch<"bne", setne, CPURegsOpnd>, BEQ_FM<5>;
945 def BGEZ : CBranchZero<"bgez", setge, CPURegsOpnd>, BGEZ_FM<1, 1>;
946 def BGTZ : CBranchZero<"bgtz", setgt, CPURegsOpnd>, BGEZ_FM<7, 0>;
947 def BLEZ : CBranchZero<"blez", setle, CPURegsOpnd>, BGEZ_FM<6, 0>;
948 def BLTZ : CBranchZero<"bltz", setlt, CPURegsOpnd>, BGEZ_FM<1, 0>;
950 def BAL_BR: BAL_FT, BAL_FM;
952 def JAL : JumpLink<"jal">, FJ<3>;
953 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
954 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
955 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
956 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
957 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
958 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
960 def RET : RetBase<CPURegs>, MTLO_FM<8>;
962 // Exception handling related node and instructions.
963 // The conversion sequence is:
964 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
965 // MIPSeh_return -> (stack change + indirect branch)
967 // MIPSeh_return takes the place of regular return instruction
968 // but takes two arguments (V1, V0) which are used for storing
969 // the offset and return address respectively.
970 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
972 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
973 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
975 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
976 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
977 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
978 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
980 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
983 /// Multiply and Divide Instructions.
984 def MULT : MMRel, Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>,
986 def MULTu : MMRel, Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>,
988 def PseudoMULT : MultDivPseudo<MULT, ACRegs, CPURegsOpnd, MipsMult, IIImul>;
989 def PseudoMULTu : MultDivPseudo<MULTu, ACRegs, CPURegsOpnd, MipsMultu, IIImul>;
990 def SDIV : Div<"div", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1a>;
991 def UDIV : Div<"divu", IIIdiv, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x1b>;
992 def PseudoSDIV : MultDivPseudo<SDIV, ACRegs, CPURegsOpnd, MipsDivRem, IIIdiv, 0>;
993 def PseudoUDIV : MultDivPseudo<UDIV, ACRegs, CPURegsOpnd, MipsDivRemU, IIIdiv,
996 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
997 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
998 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
999 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
1001 /// Sign Ext In Register Instructions.
1002 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
1003 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
1006 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
1007 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
1009 /// Word Swap Bytes Within Halfwords
1010 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
1013 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1015 // FrameIndexes are legalized when they are operands from load/store
1016 // instructions. The same not happens for stack address copies, so an
1017 // add op with mem ComplexPattern is used and the stack address copy
1018 // can be matched. It's similar to Sparc LEA_ADDRi
1019 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
1022 def MADD : MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1023 def MADDU : MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1024 def MSUB : MArithR<"msub">, MULT_FM<0x1c, 4>;
1025 def MSUBU : MArithR<"msubu">, MULT_FM<0x1c, 5>;
1026 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1027 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1028 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1029 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1031 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
1033 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
1034 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
1036 /// Move Control Registers From/To CPU Registers
1037 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1038 (ins CPURegsOpnd:$rd, uimm16:$sel),
1039 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
1041 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1042 (ins CPURegsOpnd:$rt),
1043 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
1045 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
1046 (ins CPURegsOpnd:$rd, uimm16:$sel),
1047 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
1049 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
1050 (ins CPURegsOpnd:$rt),
1051 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
1053 //===----------------------------------------------------------------------===//
1054 // Instruction aliases
1055 //===----------------------------------------------------------------------===//
1056 def : InstAlias<"move $dst, $src",
1057 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1058 Requires<[NotMips64]>;
1059 def : InstAlias<"move $dst, $src",
1060 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
1061 Requires<[NotMips64]>;
1062 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
1063 def : InstAlias<"addu $rs, $rt, $imm",
1064 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1065 def : InstAlias<"add $rs, $rt, $imm",
1066 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1067 def : InstAlias<"and $rs, $rt, $imm",
1068 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
1069 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
1070 Requires<[NotMips64]>;
1071 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
1072 def : InstAlias<"jal $rs", (JALR RA, CPURegs:$rs), 0>, Requires<[NotMips64]>;
1073 def : InstAlias<"jal $rd,$rs", (JALR CPURegs:$rd, CPURegs:$rs), 0>,
1074 Requires<[NotMips64]>;
1075 def : InstAlias<"not $rt, $rs",
1076 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1077 def : InstAlias<"neg $rt, $rs",
1078 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1079 def : InstAlias<"negu $rt, $rs",
1080 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1081 def : InstAlias<"slt $rs, $rt, $imm",
1082 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
1083 def : InstAlias<"xor $rs, $rt, $imm",
1084 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1085 Requires<[NotMips64]>;
1086 def : InstAlias<"or $rs, $rt, $imm",
1087 (ORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, uimm16:$imm), 1>,
1088 Requires<[NotMips64]>;
1089 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1090 def : InstAlias<"mfc0 $rt, $rd",
1091 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1092 def : InstAlias<"mtc0 $rt, $rd",
1093 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1094 def : InstAlias<"mfc2 $rt, $rd",
1095 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1096 def : InstAlias<"mtc2 $rt, $rd",
1097 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1098 def : InstAlias<"addiu $rs, $imm",
1099 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rs, simm16:$imm), 0>;
1100 def : InstAlias<"bnez $rs,$offset",
1101 (BNE CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1102 Requires<[NotMips64]>;
1103 def : InstAlias<"beqz $rs,$offset",
1104 (BEQ CPURegsOpnd:$rs, ZERO, brtarget:$offset), 1>,
1105 Requires<[NotMips64]>;
1106 //===----------------------------------------------------------------------===//
1107 // Assembler Pseudo Instructions
1108 //===----------------------------------------------------------------------===//
1110 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1111 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1112 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1113 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1115 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1116 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1117 !strconcat(instr_asm, "\t$rt, $addr")> ;
1118 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1120 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1121 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1122 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1123 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1127 //===----------------------------------------------------------------------===//
1128 // Arbitrary patterns that map to one or more instructions
1129 //===----------------------------------------------------------------------===//
1131 // Load/store pattern templates.
1132 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1133 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1135 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1136 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1139 def : MipsPat<(i32 immSExt16:$in),
1140 (ADDiu ZERO, imm:$in)>;
1141 def : MipsPat<(i32 immZExt16:$in),
1142 (ORi ZERO, imm:$in)>;
1143 def : MipsPat<(i32 immLow16Zero:$in),
1144 (LUi (HI16 imm:$in))>;
1146 // Arbitrary immediates
1147 def : MipsPat<(i32 imm:$imm),
1148 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1150 // Carry MipsPatterns
1151 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1152 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1153 let Predicates = [HasStdEnc, NotDSP] in {
1154 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1155 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1156 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1157 (ADDiu CPURegs:$src, imm:$imm)>;
1161 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1162 (JAL tglobaladdr:$dst)>;
1163 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1164 (JAL texternalsym:$dst)>;
1165 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1166 // (JALR CPURegs:$dst)>;
1169 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1170 (TAILCALL tglobaladdr:$dst)>;
1171 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1172 (TAILCALL texternalsym:$dst)>;
1174 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1175 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1176 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1177 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1178 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1179 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1181 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1182 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1183 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1184 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1185 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1186 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1188 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1189 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1190 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1191 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1192 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1193 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1194 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1195 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1196 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1197 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1200 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1201 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1202 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1203 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1206 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1207 MipsPat<(MipsWrapper RC:$gp, node:$in),
1208 (ADDiuOp RC:$gp, node:$in)>;
1210 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1211 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1212 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1213 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1214 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1215 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1217 // Mips does not have "not", so we expand our way
1218 def : MipsPat<(not CPURegs:$in),
1219 (NOR CPURegsOpnd:$in, ZERO)>;
1222 let Predicates = [NotN64, HasStdEnc] in {
1223 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1224 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1225 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1227 let Predicates = [IsN64, HasStdEnc] in {
1228 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1229 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1230 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1234 let Predicates = [NotN64, HasStdEnc] in {
1235 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1237 let Predicates = [IsN64, HasStdEnc] in {
1238 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1242 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1243 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1244 Instruction SLTiuOp, Register ZEROReg> {
1245 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1246 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1247 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1248 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1250 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1251 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1252 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1253 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1254 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1255 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1256 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1257 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1259 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1260 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1261 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1262 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1264 def : MipsPat<(brcond RC:$cond, bb:$dst),
1265 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1268 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1271 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1272 Instruction SLTuOp, Register ZEROReg> {
1273 def : MipsPat<(seteq RC:$lhs, 0),
1274 (SLTiuOp RC:$lhs, 1)>;
1275 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1276 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1277 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1278 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1281 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1282 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1283 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1284 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1285 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1288 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1289 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1290 (SLTOp RC:$rhs, RC:$lhs)>;
1291 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1292 (SLTuOp RC:$rhs, RC:$lhs)>;
1295 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1296 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1297 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1298 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1299 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1302 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1303 Instruction SLTiuOp> {
1304 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1305 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1306 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1307 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1310 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1311 defm : SetlePats<CPURegs, SLT, SLTu>;
1312 defm : SetgtPats<CPURegs, SLT, SLTu>;
1313 defm : SetgePats<CPURegs, SLT, SLTu>;
1314 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1317 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1319 // mflo/hi patterns.
1320 def : MipsPat<(i32 (ExtractLOHI ACRegs:$ac, imm:$lohi_idx)),
1321 (EXTRACT_SUBREG ACRegs:$ac, imm:$lohi_idx)>;
1323 // Load halfword/word patterns.
1324 let AddedComplexity = 40 in {
1325 let Predicates = [NotN64, HasStdEnc] in {
1326 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1327 def : LoadRegImmPat<LH, i32, sextloadi16>;
1328 def : LoadRegImmPat<LW, i32, load>;
1330 let Predicates = [IsN64, HasStdEnc] in {
1331 def : LoadRegImmPat<LBu_P8, i32, zextloadi8>;
1332 def : LoadRegImmPat<LH_P8, i32, sextloadi16>;
1333 def : LoadRegImmPat<LW_P8, i32, load>;
1337 //===----------------------------------------------------------------------===//
1338 // Floating Point Support
1339 //===----------------------------------------------------------------------===//
1341 include "MipsInstrFPU.td"
1342 include "Mips64InstrInfo.td"
1343 include "MipsCondMov.td"
1348 include "Mips16InstrFormats.td"
1349 include "Mips16InstrInfo.td"
1352 include "MipsDSPInstrFormats.td"
1353 include "MipsDSPInstrInfo.td"
1356 include "MicroMipsInstrFormats.td"
1357 include "MicroMipsInstrInfo.td"