1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
20 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
21 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
25 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
26 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
27 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
28 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
31 def SDT_MipsDivRem : SDTypeProfile<0, 2,
35 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
37 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, iPTR>,
39 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
41 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
42 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
43 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
44 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
48 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
49 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
52 // Hi and Lo nodes are used to handle global addresses. Used on
53 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
54 // static model. (nothing to do with Mips Registers Hi and Lo)
55 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
56 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
57 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
59 // TlsGd node is used to handle General Dynamic TLS
60 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
62 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
63 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
64 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
67 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
70 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
73 // These are target-independent nodes, but have target-specific formats.
74 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
75 [SDNPHasChain, SDNPOutGlue]>;
76 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
77 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
80 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
81 [SDNPOptInGlue, SDNPOutGlue]>;
82 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
83 [SDNPOptInGlue, SDNPOutGlue]>;
84 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
85 [SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
90 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
92 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
95 // Target constant nodes that are not part of any isel patterns and remain
96 // unchanged can cause instructions with illegal operands to be emitted.
97 // Wrapper node patterns give the instruction selector a chance to replace
98 // target constant nodes that would otherwise remain unchanged with ADDiu
99 // nodes. Without these wrapper node patterns, the following conditional move
100 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
102 // movn %got(d)($gp), %got(c)($gp), $4
103 // This instruction is illegal since movn can take only register operands.
105 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
107 // Pointer to dynamically allocated stack area.
108 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
109 [SDNPHasChain, SDNPInGlue]>;
111 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
113 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
114 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
116 //===----------------------------------------------------------------------===//
117 // Mips Instruction Predicate Definitions.
118 //===----------------------------------------------------------------------===//
119 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
120 AssemblerPredicate<"FeatureSEInReg">;
121 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
122 AssemblerPredicate<"FeatureBitCount">;
123 def HasSwap : Predicate<"Subtarget.hasSwap()">,
124 AssemblerPredicate<"FeatureSwap">;
125 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
126 AssemblerPredicate<"FeatureCondMov">;
127 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
128 AssemblerPredicate<"FeatureMips32">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
130 AssemblerPredicate<"FeatureMips32r2">;
131 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
132 AssemblerPredicate<"FeatureMips64">;
133 def HasMips32r2Or64 : Predicate<"Subtarget.hasMips32r2Or64()">,
134 AssemblerPredicate<"FeatureMips32r2,FeatureMips64">;
135 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
136 AssemblerPredicate<"!FeatureMips64">;
137 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
138 AssemblerPredicate<"FeatureMips64r2">;
139 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
140 AssemblerPredicate<"FeatureN64">;
141 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
142 AssemblerPredicate<"!FeatureN64">;
143 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
144 AssemblerPredicate<"FeatureMips16">;
145 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
146 AssemblerPredicate<"FeatureMips32">;
147 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
148 AssemblerPredicate<"FeatureMips32">;
149 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
150 AssemblerPredicate<"FeatureMips32">;
151 def HasStandardEncoding : Predicate<"Subtarget.hasStandardEncoding()">,
152 AssemblerPredicate<"!FeatureMips16">;
154 //===----------------------------------------------------------------------===//
155 // Instruction format superclass
156 //===----------------------------------------------------------------------===//
158 include "MipsInstrFormats.td"
160 //===----------------------------------------------------------------------===//
161 // Mips Operand, Complex Patterns and Transformations Definitions.
162 //===----------------------------------------------------------------------===//
164 // Instruction operand types
165 def jmptarget : Operand<OtherVT> {
166 let EncoderMethod = "getJumpTargetOpValue";
168 def brtarget : Operand<OtherVT> {
169 let EncoderMethod = "getBranchTargetOpValue";
170 let OperandType = "OPERAND_PCREL";
171 let DecoderMethod = "DecodeBranchTarget";
173 def calltarget : Operand<iPTR> {
174 let EncoderMethod = "getJumpTargetOpValue";
176 def calltarget64: Operand<i64>;
177 def simm16 : Operand<i32> {
178 let DecoderMethod= "DecodeSimm16";
180 def simm16_64 : Operand<i64>;
181 def shamt : Operand<i32>;
184 def uimm16 : Operand<i32> {
185 let PrintMethod = "printUnsignedImm";
189 def mem : Operand<i32> {
190 let PrintMethod = "printMemOperand";
191 let MIOperandInfo = (ops CPURegs, simm16);
192 let EncoderMethod = "getMemEncoding";
195 def mem64 : Operand<i64> {
196 let PrintMethod = "printMemOperand";
197 let MIOperandInfo = (ops CPU64Regs, simm16_64);
200 def mem_ea : Operand<i32> {
201 let PrintMethod = "printMemOperandEA";
202 let MIOperandInfo = (ops CPURegs, simm16);
203 let EncoderMethod = "getMemEncoding";
206 def mem_ea_64 : Operand<i64> {
207 let PrintMethod = "printMemOperandEA";
208 let MIOperandInfo = (ops CPU64Regs, simm16_64);
209 let EncoderMethod = "getMemEncoding";
212 // size operand of ext instruction
213 def size_ext : Operand<i32> {
214 let EncoderMethod = "getSizeExtEncoding";
215 let DecoderMethod = "DecodeExtSize";
218 // size operand of ins instruction
219 def size_ins : Operand<i32> {
220 let EncoderMethod = "getSizeInsEncoding";
221 let DecoderMethod = "DecodeInsSize";
224 // Transformation Function - get the lower 16 bits.
225 def LO16 : SDNodeXForm<imm, [{
226 return getImm(N, N->getZExtValue() & 0xFFFF);
229 // Transformation Function - get the higher 16 bits.
230 def HI16 : SDNodeXForm<imm, [{
231 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
234 // Node immediate fits as 16-bit sign extended on target immediate.
236 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
238 // Node immediate fits as 16-bit zero extended on target immediate.
239 // The LO16 param means that only the lower 16 bits of the node
240 // immediate are caught.
242 def immZExt16 : PatLeaf<(imm), [{
243 if (N->getValueType(0) == MVT::i32)
244 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
246 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
249 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
250 def immLow16Zero : PatLeaf<(imm), [{
251 int64_t Val = N->getSExtValue();
252 return isInt<32>(Val) && !(Val & 0xffff);
255 // shamt field must fit in 5 bits.
256 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
258 // Mips Address Mode! SDNode frameindex could possibily be a match
259 // since load and store instructions from stack used it.
261 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
263 //===----------------------------------------------------------------------===//
264 // Pattern fragment for load/store
265 //===----------------------------------------------------------------------===//
266 class UnalignedLoad<PatFrag Node> :
267 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
268 LoadSDNode *LD = cast<LoadSDNode>(N);
269 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
272 class AlignedLoad<PatFrag Node> :
273 PatFrag<(ops node:$ptr), (Node node:$ptr), [{
274 LoadSDNode *LD = cast<LoadSDNode>(N);
275 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
278 class UnalignedStore<PatFrag Node> :
279 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
280 StoreSDNode *SD = cast<StoreSDNode>(N);
281 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
284 class AlignedStore<PatFrag Node> :
285 PatFrag<(ops node:$val, node:$ptr), (Node node:$val, node:$ptr), [{
286 StoreSDNode *SD = cast<StoreSDNode>(N);
287 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
290 // Load/Store PatFrags.
291 def sextloadi16_a : AlignedLoad<sextloadi16>;
292 def zextloadi16_a : AlignedLoad<zextloadi16>;
293 def extloadi16_a : AlignedLoad<extloadi16>;
294 def load_a : AlignedLoad<load>;
295 def sextloadi32_a : AlignedLoad<sextloadi32>;
296 def zextloadi32_a : AlignedLoad<zextloadi32>;
297 def extloadi32_a : AlignedLoad<extloadi32>;
298 def truncstorei16_a : AlignedStore<truncstorei16>;
299 def store_a : AlignedStore<store>;
300 def truncstorei32_a : AlignedStore<truncstorei32>;
301 def sextloadi16_u : UnalignedLoad<sextloadi16>;
302 def zextloadi16_u : UnalignedLoad<zextloadi16>;
303 def extloadi16_u : UnalignedLoad<extloadi16>;
304 def load_u : UnalignedLoad<load>;
305 def sextloadi32_u : UnalignedLoad<sextloadi32>;
306 def zextloadi32_u : UnalignedLoad<zextloadi32>;
307 def extloadi32_u : UnalignedLoad<extloadi32>;
308 def truncstorei16_u : UnalignedStore<truncstorei16>;
309 def store_u : UnalignedStore<store>;
310 def truncstorei32_u : UnalignedStore<truncstorei32>;
312 //===----------------------------------------------------------------------===//
313 // Instructions specific format
314 //===----------------------------------------------------------------------===//
316 // Arithmetic and logical instructions with 3 register operands.
317 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
318 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
319 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
320 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
321 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
323 let isCommutable = isComm;
324 let isReMaterializable = 1;
327 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
328 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
329 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
330 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
332 let isCommutable = isComm;
335 // Arithmetic and logical instructions with 2 register operands.
336 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
337 Operand Od, PatLeaf imm_type, RegisterClass RC> :
338 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
339 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
340 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu> {
341 let isReMaterializable = 1;
344 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
345 Operand Od, PatLeaf imm_type, RegisterClass RC> :
346 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$imm16),
347 !strconcat(instr_asm, "\t$rt, $rs, $imm16"), [], IIAlu>;
349 // Arithmetic Multiply ADD/SUB
350 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
351 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
352 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
353 !strconcat(instr_asm, "\t$rs, $rt"),
354 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
357 let isCommutable = isComm;
361 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
362 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
363 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
364 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
366 let isCommutable = 1;
370 class shift_rotate_imm<bits<6> func, bits<5> isRotate, string instr_asm,
371 SDNode OpNode, PatFrag PF, Operand ImmOpnd,
373 FR<0x00, func, (outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
374 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
375 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu> {
379 // 32-bit shift instructions.
380 class shift_rotate_imm32<bits<6> func, bits<5> isRotate, string instr_asm,
382 shift_rotate_imm<func, isRotate, instr_asm, OpNode, immZExt5, shamt, CPURegs>;
384 class shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
385 SDNode OpNode, RegisterClass RC>:
386 FR<0x00, func, (outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
387 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
388 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu> {
389 let shamt = isRotate;
392 // Load Upper Imediate
393 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
394 FI<op, (outs RC:$rt), (ins Imm:$imm16),
395 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu> {
397 let neverHasSideEffects = 1;
398 let isReMaterializable = 1;
401 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
402 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
404 let Inst{25-21} = addr{20-16};
405 let Inst{15-0} = addr{15-0};
406 let DecoderMethod = "DecodeMem";
410 let canFoldAsLoad = 1 in
411 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
412 Operand MemOpnd, bit Pseudo>:
413 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
414 !strconcat(instr_asm, "\t$rt, $addr"),
415 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
416 let isPseudo = Pseudo;
419 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
420 Operand MemOpnd, bit Pseudo>:
421 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
422 !strconcat(instr_asm, "\t$rt, $addr"),
423 [(OpNode RC:$rt, addr:$addr)], IIStore> {
424 let isPseudo = Pseudo;
427 // Unaligned Memory Load/Store
428 let canFoldAsLoad = 1 in
429 class LoadUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
430 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr), "", [], IILoad> {}
432 class StoreUnAlign<bits<6> op, RegisterClass RC, Operand MemOpnd>:
433 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr), "", [], IIStore> {}
436 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
438 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
439 Requires<[NotN64, HasStandardEncoding]>;
440 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
441 Requires<[IsN64, HasStandardEncoding]> {
442 let DecoderNamespace = "Mips64";
443 let isCodeGenOnly = 1;
448 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
450 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
451 Requires<[NotN64, HasStandardEncoding]>;
452 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
453 Requires<[IsN64, HasStandardEncoding]> {
454 let DecoderNamespace = "Mips64";
455 let isCodeGenOnly = 1;
460 multiclass LoadUnAlign32<bits<6> op> {
461 def #NAME# : LoadUnAlign<op, CPURegs, mem>,
462 Requires<[NotN64, HasStandardEncoding]>;
463 def _P8 : LoadUnAlign<op, CPURegs, mem64>,
464 Requires<[IsN64, HasStandardEncoding]> {
465 let DecoderNamespace = "Mips64";
466 let isCodeGenOnly = 1;
470 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
472 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
473 Requires<[NotN64, HasStandardEncoding]>;
474 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
475 Requires<[IsN64, HasStandardEncoding]> {
476 let DecoderNamespace = "Mips64";
477 let isCodeGenOnly = 1;
482 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
484 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
485 Requires<[NotN64, HasStandardEncoding]>;
486 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
487 Requires<[IsN64, HasStandardEncoding]> {
488 let DecoderNamespace = "Mips64";
489 let isCodeGenOnly = 1;
494 multiclass StoreUnAlign32<bits<6> op> {
495 def #NAME# : StoreUnAlign<op, CPURegs, mem>,
496 Requires<[NotN64, HasStandardEncoding]>;
497 def _P8 : StoreUnAlign<op, CPURegs, mem64>,
498 Requires<[IsN64, HasStandardEncoding]> {
499 let DecoderNamespace = "Mips64";
500 let isCodeGenOnly = 1;
504 // Conditional Branch
505 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
506 BranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$imm16),
507 !strconcat(instr_asm, "\t$rs, $rt, $imm16"),
508 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$imm16)], IIBranch> {
510 let isTerminator = 1;
511 let hasDelaySlot = 1;
514 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
516 BranchBase<op, (outs), (ins RC:$rs, brtarget:$imm16),
517 !strconcat(instr_asm, "\t$rs, $imm16"),
518 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$imm16)], IIBranch> {
521 let isTerminator = 1;
522 let hasDelaySlot = 1;
526 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
528 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
529 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
530 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
535 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
536 PatLeaf imm_type, RegisterClass RC>:
537 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
538 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
539 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
543 class JumpFJ<bits<6> op, string instr_asm>:
544 FJ<op, (outs), (ins jmptarget:$target),
545 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch> {
549 let hasDelaySlot = 1;
550 let Predicates = [RelocStatic, HasStandardEncoding];
551 let DecoderMethod = "DecodeJumpTarget";
554 // Unconditional branch
555 class UncondBranch<bits<6> op, string instr_asm>:
556 BranchBase<op, (outs), (ins brtarget:$imm16),
557 !strconcat(instr_asm, "\t$imm16"), [(br bb:$imm16)], IIBranch> {
561 let isTerminator = 1;
563 let hasDelaySlot = 1;
564 let Predicates = [RelocPIC, HasStandardEncoding];
567 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1,
568 isIndirectBranch = 1 in
569 class JumpFR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
570 FR<op, func, (outs), (ins RC:$rs),
571 !strconcat(instr_asm, "\t$rs"), [(brind RC:$rs)], IIBranch> {
577 // Jump and Link (Call)
578 let isCall=1, hasDelaySlot=1 in {
579 class JumpLink<bits<6> op, string instr_asm>:
580 FJ<op, (outs), (ins calltarget:$target, variable_ops),
581 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
583 let DecoderMethod = "DecodeJumpTarget";
586 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
588 FR<op, func, (outs), (ins RC:$rs, variable_ops),
589 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
595 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
596 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16, variable_ops),
597 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
603 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
604 RegisterClass RC, list<Register> DefRegs>:
605 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
606 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
609 let isCommutable = 1;
611 let neverHasSideEffects = 1;
614 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
615 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
617 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
618 RegisterClass RC, list<Register> DefRegs>:
619 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
620 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
621 [(op RC:$rs, RC:$rt)], itin> {
627 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
628 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
631 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
632 list<Register> UseRegs>:
633 FR<0x00, func, (outs RC:$rd), (ins),
634 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
639 let neverHasSideEffects = 1;
642 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
643 list<Register> DefRegs>:
644 FR<0x00, func, (outs), (ins RC:$rs),
645 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
650 let neverHasSideEffects = 1;
653 class EffectiveAddress<string instr_asm, RegisterClass RC, Operand Mem> :
654 FMem<0x09, (outs RC:$rt), (ins Mem:$addr),
655 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu>;
657 // Count Leading Ones/Zeros in Word
658 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
659 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
660 !strconcat(instr_asm, "\t$rd, $rs"),
661 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
662 Requires<[HasBitCount, HasStandardEncoding]> {
667 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
668 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
669 !strconcat(instr_asm, "\t$rd, $rs"),
670 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
671 Requires<[HasBitCount, HasStandardEncoding]> {
676 // Sign Extend in Register.
677 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
679 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
680 !strconcat(instr_asm, "\t$rd, $rt"),
681 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
684 let Predicates = [HasSEInReg, HasStandardEncoding];
688 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
689 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
690 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
693 let Predicates = [HasSwap, HasStandardEncoding];
694 let neverHasSideEffects = 1;
698 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
699 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
700 "rdhwr\t$rt, $rd", [], IIAlu> {
706 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
707 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
708 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
709 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
714 let Predicates = [HasMips32r2, HasStandardEncoding];
717 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
718 FR<0x1f, _funct, (outs RC:$rt),
719 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
720 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
721 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
727 let Predicates = [HasMips32r2, HasStandardEncoding];
728 let Constraints = "$src = $rt";
731 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
732 class Atomic2Ops<PatFrag Op, string Opstr, RegisterClass DRC,
734 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
735 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
736 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
738 multiclass Atomic2Ops32<PatFrag Op, string Opstr> {
739 def #NAME# : Atomic2Ops<Op, Opstr, CPURegs, CPURegs>,
740 Requires<[NotN64, HasStandardEncoding]>;
741 def _P8 : Atomic2Ops<Op, Opstr, CPURegs, CPU64Regs>,
742 Requires<[IsN64, HasStandardEncoding]> {
743 let DecoderNamespace = "Mips64";
747 // Atomic Compare & Swap.
748 class AtomicCmpSwap<PatFrag Op, string Width, RegisterClass DRC,
750 MipsPseudo<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
751 !strconcat("atomic_cmp_swap_", Width, "\t$dst, $ptr, $cmp, $swap"),
752 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
754 multiclass AtomicCmpSwap32<PatFrag Op, string Width> {
755 def #NAME# : AtomicCmpSwap<Op, Width, CPURegs, CPURegs>,
756 Requires<[NotN64, HasStandardEncoding]>;
757 def _P8 : AtomicCmpSwap<Op, Width, CPURegs, CPU64Regs>,
758 Requires<[IsN64, HasStandardEncoding]> {
759 let DecoderNamespace = "Mips64";
763 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
764 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
765 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
769 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
770 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
771 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
773 let Constraints = "$rt = $dst";
776 //===----------------------------------------------------------------------===//
777 // Pseudo instructions
778 //===----------------------------------------------------------------------===//
780 // As stack alignment is always done with addiu, we need a 16-bit immediate
781 let Defs = [SP], Uses = [SP] in {
782 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
783 "!ADJCALLSTACKDOWN $amt",
784 [(callseq_start timm:$amt)]>;
785 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
786 "!ADJCALLSTACKUP $amt1",
787 [(callseq_end timm:$amt1, timm:$amt2)]>;
790 // When handling PIC code the assembler needs .cpload and .cprestore
791 // directives. If the real instructions corresponding these directives
792 // are used, we have the same behavior, but get also a bunch of warnings
793 // from the assembler.
794 let neverHasSideEffects = 1 in
795 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc, CPURegs:$gp),
796 ".cprestore\t$loc", []>;
798 let usesCustomInserter = 1 in {
799 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8, "load_add_8">;
800 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16, "load_add_16">;
801 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32, "load_add_32">;
802 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8, "load_sub_8">;
803 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16, "load_sub_16">;
804 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32, "load_sub_32">;
805 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8, "load_and_8">;
806 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16, "load_and_16">;
807 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32, "load_and_32">;
808 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8, "load_or_8">;
809 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16, "load_or_16">;
810 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32, "load_or_32">;
811 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8, "load_xor_8">;
812 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16, "load_xor_16">;
813 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32, "load_xor_32">;
814 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8, "load_nand_8">;
815 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16, "load_nand_16">;
816 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32, "load_nand_32">;
818 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8, "swap_8">;
819 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16, "swap_16">;
820 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32, "swap_32">;
822 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8, "8">;
823 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16, "16">;
824 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32, "32">;
827 //===----------------------------------------------------------------------===//
828 // Instruction definition
829 //===----------------------------------------------------------------------===//
831 //===----------------------------------------------------------------------===//
832 // MipsI Instructions
833 //===----------------------------------------------------------------------===//
835 /// Arithmetic Instructions (ALU Immediate)
836 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
837 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
838 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
839 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
840 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
841 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
842 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
843 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
845 /// Arithmetic Instructions (3-Operand, R-Type)
846 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
847 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
848 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
849 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
850 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
851 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
852 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
853 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
854 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
855 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
857 /// Shift Instructions
858 def SLL : shift_rotate_imm32<0x00, 0x00, "sll", shl>;
859 def SRL : shift_rotate_imm32<0x02, 0x00, "srl", srl>;
860 def SRA : shift_rotate_imm32<0x03, 0x00, "sra", sra>;
861 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
862 def SRLV : shift_rotate_reg<0x06, 0x00, "srlv", srl, CPURegs>;
863 def SRAV : shift_rotate_reg<0x07, 0x00, "srav", sra, CPURegs>;
865 // Rotate Instructions
866 let Predicates = [HasMips32r2, HasStandardEncoding] in {
867 def ROTR : shift_rotate_imm32<0x02, 0x01, "rotr", rotr>;
868 def ROTRV : shift_rotate_reg<0x06, 0x01, "rotrv", rotr, CPURegs>;
871 /// Load and Store Instructions
873 defm LB : LoadM32<0x20, "lb", sextloadi8>;
874 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
875 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
876 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
877 defm LW : LoadM32<0x23, "lw", load_a>;
878 defm SB : StoreM32<0x28, "sb", truncstorei8>;
879 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
880 defm SW : StoreM32<0x2b, "sw", store_a>;
883 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
884 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
885 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
886 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
887 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
889 /// Primitives for unaligned
890 defm LWL : LoadUnAlign32<0x22>;
891 defm LWR : LoadUnAlign32<0x26>;
892 defm SWL : StoreUnAlign32<0x2A>;
893 defm SWR : StoreUnAlign32<0x2E>;
895 let hasSideEffects = 1 in
896 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
897 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
902 let Inst{10-6} = stype;
906 /// Load-linked, Store-conditional
907 def LL : LLBase<0x30, "ll", CPURegs, mem>,
908 Requires<[NotN64, HasStandardEncoding]>;
909 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
910 Requires<[IsN64, HasStandardEncoding]> {
911 let DecoderNamespace = "Mips64";
914 def SC : SCBase<0x38, "sc", CPURegs, mem>,
915 Requires<[NotN64, HasStandardEncoding]>;
916 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
917 Requires<[IsN64, HasStandardEncoding]> {
918 let DecoderNamespace = "Mips64";
921 /// Jump and Branch Instructions
922 def J : JumpFJ<0x02, "j">;
923 def JR : JumpFR<0x00, 0x08, "jr", CPURegs>;
924 def B : UncondBranch<0x04, "b">;
925 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
926 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
927 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
928 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
929 def BLEZ : CBranchZero<0x06, 0, "blez", setle, CPURegs>;
930 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
932 def JAL : JumpLink<0x03, "jal">;
933 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
934 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
935 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
937 let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
938 isBarrier=1, hasCtrlDep=1, rd=0, rt=0, shamt=0 in
939 def RET : FR <0x00, 0x08, (outs), (ins CPURegs:$target),
940 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
942 /// Multiply and Divide Instructions.
943 def MULT : Mult32<0x18, "mult", IIImul>;
944 def MULTu : Mult32<0x19, "multu", IIImul>;
945 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
946 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
948 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
949 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
950 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
951 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
953 /// Sign Ext In Register Instructions.
954 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
955 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
958 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
959 def CLO : CountLeading1<0x21, "clo", CPURegs>;
961 /// Word Swap Bytes Within Halfwords
962 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
966 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
968 // FrameIndexes are legalized when they are operands from load/store
969 // instructions. The same not happens for stack address copies, so an
970 // add op with mem ComplexPattern is used and the stack address copy
971 // can be matched. It's similar to Sparc LEA_ADDRi
972 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
973 let isCodeGenOnly = 1;
976 // DynAlloc node points to dynamically allocated stack space.
977 // $sp is added to the list of implicitly used registers to prevent dead code
978 // elimination from removing instructions that modify $sp.
980 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr", CPURegs, mem_ea> {
981 let isCodeGenOnly = 1;
985 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
986 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
987 def MSUB : MArithR<4, "msub", MipsMSub>;
988 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
990 // MUL is a assembly macro in the current used ISAs. In recent ISA's
991 // it is a real instruction.
992 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
993 Requires<[HasMips32, HasStandardEncoding]>;
995 def RDHWR : ReadHardware<CPURegs, HWRegs>;
997 def EXT : ExtBase<0, "ext", CPURegs>;
998 def INS : InsBase<4, "ins", CPURegs>;
1000 //===----------------------------------------------------------------------===//
1001 // Arbitrary patterns that map to one or more instructions
1002 //===----------------------------------------------------------------------===//
1005 def : Pat<(i32 immSExt16:$in),
1006 (ADDiu ZERO, imm:$in)>;
1007 def : Pat<(i32 immZExt16:$in),
1008 (ORi ZERO, imm:$in)>;
1009 def : Pat<(i32 immLow16Zero:$in),
1010 (LUi (HI16 imm:$in))>;
1012 // Arbitrary immediates
1013 def : Pat<(i32 imm:$imm),
1014 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1017 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
1018 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1019 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
1020 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1021 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
1022 (ADDiu CPURegs:$src, imm:$imm)>;
1025 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1026 (JAL tglobaladdr:$dst)>;
1027 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
1028 (JAL texternalsym:$dst)>;
1029 //def : Pat<(MipsJmpLink CPURegs:$dst),
1030 // (JALR CPURegs:$dst)>;
1033 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1034 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1035 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1036 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1037 def : Pat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1039 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1040 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1041 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1042 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1043 def : Pat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1045 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1046 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1047 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1048 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1049 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1050 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1051 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1052 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1053 def : Pat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1054 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1057 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1058 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1059 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1060 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1063 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1064 Pat<(MipsWrapper RC:$gp, node:$in),
1065 (ADDiuOp RC:$gp, node:$in)>;
1067 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1068 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1069 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1070 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1071 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1072 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1074 // Mips does not have "not", so we expand our way
1075 def : Pat<(not CPURegs:$in),
1076 (NOR CPURegs:$in, ZERO)>;
1079 let Predicates = [NotN64, HasStandardEncoding] in {
1080 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1081 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1082 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu addr:$src)>;
1083 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu addr:$src)>;
1085 let Predicates = [IsN64, HasStandardEncoding] in {
1086 def : Pat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1087 def : Pat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1088 def : Pat<(i32 (extloadi16_a addr:$src)), (LHu_P8 addr:$src)>;
1089 def : Pat<(i32 (extloadi16_u addr:$src)), (ULHu_P8 addr:$src)>;
1093 let Predicates = [NotN64, HasStandardEncoding] in {
1094 def : Pat<(store_a (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1095 def : Pat<(store_u (i32 0), addr:$dst), (USW ZERO, addr:$dst)>;
1097 let Predicates = [IsN64, HasStandardEncoding] in {
1098 def : Pat<(store_a (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1099 def : Pat<(store_u (i32 0), addr:$dst), (USW_P8 ZERO, addr:$dst)>;
1103 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1104 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1105 Instruction SLTiuOp, Register ZEROReg> {
1106 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1107 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1108 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1109 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1111 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1112 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1113 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1114 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1115 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1116 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1117 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1118 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1120 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1121 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1122 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1123 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1125 def : Pat<(brcond RC:$cond, bb:$dst),
1126 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1129 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1132 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1133 Instruction SLTuOp, Register ZEROReg> {
1134 def : Pat<(seteq RC:$lhs, RC:$rhs),
1135 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1136 def : Pat<(setne RC:$lhs, RC:$rhs),
1137 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1140 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1141 def : Pat<(setle RC:$lhs, RC:$rhs),
1142 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1143 def : Pat<(setule RC:$lhs, RC:$rhs),
1144 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1147 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1148 def : Pat<(setgt RC:$lhs, RC:$rhs),
1149 (SLTOp RC:$rhs, RC:$lhs)>;
1150 def : Pat<(setugt RC:$lhs, RC:$rhs),
1151 (SLTuOp RC:$rhs, RC:$lhs)>;
1154 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1155 def : Pat<(setge RC:$lhs, RC:$rhs),
1156 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1157 def : Pat<(setuge RC:$lhs, RC:$rhs),
1158 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1161 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1162 Instruction SLTiuOp> {
1163 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
1164 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1165 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
1166 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1169 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1170 defm : SetlePats<CPURegs, SLT, SLTu>;
1171 defm : SetgtPats<CPURegs, SLT, SLTu>;
1172 defm : SetgePats<CPURegs, SLT, SLTu>;
1173 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1175 // select MipsDynAlloc
1176 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1179 def : Pat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1181 //===----------------------------------------------------------------------===//
1182 // Floating Point Support
1183 //===----------------------------------------------------------------------===//
1185 include "MipsInstrFPU.td"
1186 include "Mips64InstrInfo.td"
1187 include "MipsCondMov.td"
1192 include "Mips16InstrFormats.td"
1193 include "Mips16InstrInfo.td"