1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
136 //===----------------------------------------------------------------------===//
137 // Mips Operand, Complex Patterns and Transformations Definitions.
138 //===----------------------------------------------------------------------===//
140 // Instruction operand types
141 def brtarget : Operand<OtherVT>;
142 def calltarget : Operand<i32>;
143 def simm16 : Operand<i32>;
144 def simm16_64 : Operand<i64>;
145 def shamt : Operand<i32>;
148 def uimm16 : Operand<i32> {
149 let PrintMethod = "printUnsignedImm";
153 def mem : Operand<i32> {
154 let PrintMethod = "printMemOperand";
155 let MIOperandInfo = (ops CPURegs, simm16);
158 def mem64 : Operand<i64> {
159 let PrintMethod = "printMemOperand";
160 let MIOperandInfo = (ops CPU64Regs, simm16_64);
163 def mem_ea : Operand<i32> {
164 let PrintMethod = "printMemOperandEA";
165 let MIOperandInfo = (ops CPURegs, simm16);
168 // Transformation Function - get the lower 16 bits.
169 def LO16 : SDNodeXForm<imm, [{
170 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
173 // Transformation Function - get the higher 16 bits.
174 def HI16 : SDNodeXForm<imm, [{
175 return getI32Imm((unsigned)N->getZExtValue() >> 16);
178 // Node immediate fits as 16-bit sign extended on target immediate.
180 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
182 // Node immediate fits as 16-bit zero extended on target immediate.
183 // The LO16 param means that only the lower 16 bits of the node
184 // immediate are caught.
186 def immZExt16 : PatLeaf<(imm), [{
187 if (N->getValueType(0) == MVT::i32)
188 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
190 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
193 // shamt field must fit in 5 bits.
194 def immZExt5 : PatLeaf<(imm), [{
195 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
198 // Mips Address Mode! SDNode frameindex could possibily be a match
199 // since load and store instructions from stack used it.
200 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
202 //===----------------------------------------------------------------------===//
203 // Pattern fragment for load/store
204 //===----------------------------------------------------------------------===//
205 class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
206 LoadSDNode *LD = cast<LoadSDNode>(N);
207 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
210 class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
211 LoadSDNode *LD = cast<LoadSDNode>(N);
212 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
215 class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
216 (Node node:$val, node:$ptr), [{
217 StoreSDNode *SD = cast<StoreSDNode>(N);
218 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
221 class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
222 (Node node:$val, node:$ptr), [{
223 StoreSDNode *SD = cast<StoreSDNode>(N);
224 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
227 // Load/Store PatFrags.
228 def sextloadi16_a : AlignedLoad<sextloadi16>;
229 def zextloadi16_a : AlignedLoad<zextloadi16>;
230 def extloadi16_a : AlignedLoad<extloadi16>;
231 def load_a : AlignedLoad<load>;
232 def sextloadi32_a : AlignedLoad<sextloadi32>;
233 def zextloadi32_a : AlignedLoad<zextloadi32>;
234 def extloadi32_a : AlignedLoad<extloadi32>;
235 def truncstorei16_a : AlignedStore<truncstorei16>;
236 def store_a : AlignedStore<store>;
237 def truncstorei32_a : AlignedStore<truncstorei32>;
238 def sextloadi16_u : UnalignedLoad<sextloadi16>;
239 def zextloadi16_u : UnalignedLoad<zextloadi16>;
240 def extloadi16_u : UnalignedLoad<extloadi16>;
241 def load_u : UnalignedLoad<load>;
242 def sextloadi32_u : UnalignedLoad<sextloadi32>;
243 def zextloadi32_u : UnalignedLoad<zextloadi32>;
244 def extloadi32_u : UnalignedLoad<extloadi32>;
245 def truncstorei16_u : UnalignedStore<truncstorei16>;
246 def store_u : UnalignedStore<store>;
247 def truncstorei32_u : UnalignedStore<truncstorei32>;
249 //===----------------------------------------------------------------------===//
250 // Instructions specific format
251 //===----------------------------------------------------------------------===//
253 // Arithmetic and logical instructions with 3 register operands.
254 class ArithLogicR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
255 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
256 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
257 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
258 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], itin> {
260 let isCommutable = isComm;
263 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
264 InstrItinClass itin, RegisterClass RC, bit isComm = 0>:
265 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
266 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], itin> {
268 let isCommutable = isComm;
271 // Arithmetic and logical instructions with 2 register operands.
272 class ArithLogicI<bits<6> op, string instr_asm, SDNode OpNode,
273 Operand Od, PatLeaf imm_type, RegisterClass RC> :
274 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
275 !strconcat(instr_asm, "\t$rt, $rs, $i"),
276 [(set RC:$rt, (OpNode RC:$rs, imm_type:$i))], IIAlu>;
278 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
279 Operand Od, PatLeaf imm_type, RegisterClass RC> :
280 FI<op, (outs RC:$rt), (ins RC:$rs, Od:$i),
281 !strconcat(instr_asm, "\t$rt, $rs, $i"), [], IIAlu>;
283 // Arithmetic Multiply ADD/SUB
284 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
285 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
286 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
287 !strconcat(instr_asm, "\t$rs, $rt"),
288 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
291 let isCommutable = isComm;
295 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
296 FR<op, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
297 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
298 [(set CPURegs:$rd, (not (or CPURegs:$rs, CPURegs:$rt)))], IIAlu> {
300 let isCommutable = 1;
304 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
306 FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rt, shamt:$shamt),
307 !strconcat(instr_asm, "\t$rd, $rt, $shamt"),
308 [(set CPURegs:$rd, (OpNode CPURegs:$rt, (i32 immZExt5:$shamt)))], IIAlu> {
312 class LogicR_shift_rotate_reg<bits<6> func, bits<5> isRotate, string instr_asm,
314 FR<0x00, func, (outs CPURegs:$rd), (ins CPURegs:$rs, CPURegs:$rt),
315 !strconcat(instr_asm, "\t$rd, $rt, $rs"),
316 [(set CPURegs:$rd, (OpNode CPURegs:$rt, CPURegs:$rs))], IIAlu> {
317 let shamt = isRotate;
320 // Load Upper Imediate
321 class LoadUpper<bits<6> op, string instr_asm>:
322 FI<op, (outs CPURegs:$rt), (ins uimm16:$imm),
323 !strconcat(instr_asm, "\t$rt, $imm"), [], IIAlu> {
328 let canFoldAsLoad = 1 in
329 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
330 Operand MemOpnd, bit Pseudo>:
331 FI<op, (outs RC:$rt), (ins MemOpnd:$addr),
332 !strconcat(instr_asm, "\t$rt, $addr"),
333 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
334 let isPseudo = Pseudo;
337 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
338 Operand MemOpnd, bit Pseudo>:
339 FI<op, (outs), (ins RC:$rt, MemOpnd:$addr),
340 !strconcat(instr_asm, "\t$rt, $addr"),
341 [(OpNode RC:$rt, addr:$addr)], IIStore> {
342 let isPseudo = Pseudo;
346 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
348 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
350 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
355 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
357 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
359 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
364 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
366 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
368 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
373 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
375 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
377 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
381 // Conditional Branch
382 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
383 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
384 !strconcat(instr_asm, "\t$rs, $rt, $offset"),
385 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch> {
387 let isTerminator = 1;
388 let hasDelaySlot = 1;
391 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
393 CBranchBase<op, (outs), (ins RC:$rs, brtarget:$offset),
394 !strconcat(instr_asm, "\t$rs, $offset"),
395 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch> {
398 let isTerminator = 1;
399 let hasDelaySlot = 1;
403 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
405 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
406 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
407 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
412 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
413 PatLeaf imm_type, RegisterClass RC>:
414 FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
415 !strconcat(instr_asm, "\t$rd, $rs, $i"),
416 [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
419 // Unconditional branch
420 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
421 class JumpFJ<bits<6> op, string instr_asm>:
422 FJ<op, (outs), (ins brtarget:$target),
423 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
425 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
426 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
427 FR<op, func, (outs), (ins CPURegs:$rs),
428 !strconcat(instr_asm, "\t$rs"), [(brind CPURegs:$rs)], IIBranch> {
434 // Jump and Link (Call)
435 let isCall=1, hasDelaySlot=1,
436 // All calls clobber the non-callee saved registers...
437 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
438 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
439 class JumpLink<bits<6> op, string instr_asm>:
440 FJ<op, (outs), (ins calltarget:$target, variable_ops),
441 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
444 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
445 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
446 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch> {
452 class BranchLink<string instr_asm>:
453 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
454 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch> {
460 class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
461 FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
462 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
465 let isCommutable = 1;
469 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
470 FR<0x00, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
471 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
472 [(op CPURegs:$rs, CPURegs:$rt)], itin> {
479 class MoveFromLOHI<bits<6> func, string instr_asm>:
480 FR<0x00, func, (outs CPURegs:$rd), (ins),
481 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
487 class MoveToLOHI<bits<6> func, string instr_asm>:
488 FR<0x00, func, (outs), (ins CPURegs:$rs),
489 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
495 class EffectiveAddress<string instr_asm> :
496 FI<0x09, (outs CPURegs:$rt), (ins mem_ea:$addr),
497 instr_asm, [(set CPURegs:$rt, addr:$addr)], IIAlu>;
499 // Count Leading Ones/Zeros in Word
500 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
501 FR<0x1c, func, (outs CPURegs:$rd), (ins CPURegs:$rs),
502 !strconcat(instr_asm, "\t$rd, $rs"), pattern, IIAlu>,
503 Requires<[HasBitCount]> {
508 // Sign Extend in Register.
509 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt>:
510 FR<0x3f, 0x20, (outs CPURegs:$rd), (ins CPURegs:$rt),
511 !strconcat(instr_asm, "\t$rd, $rt"),
512 [(set CPURegs:$rd, (sext_inreg CPURegs:$rt, vt))], NoItinerary> {
515 let Predicates = [HasSEInReg];
519 class ByteSwap<bits<6> func, bits<5> sa, string instr_asm>:
520 FR<0x1f, func, (outs CPURegs:$rd), (ins CPURegs:$rt),
521 !strconcat(instr_asm, "\t$rd, $rt"),
522 [(set CPURegs:$rd, (bswap CPURegs:$rt))], NoItinerary> {
525 let Predicates = [HasSwap];
529 class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$rt), (ins HWRegs:$rd),
530 "rdhwr\t$rt, $rd", [], IIAlu> {
536 class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
537 list<dag> pattern, InstrItinClass itin>:
538 FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
539 pattern, itin>, Requires<[HasMips32r2]> {
546 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
547 class Atomic2Ops<PatFrag Op, string Opstr> :
548 MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
549 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
551 (Op CPURegs:$ptr, CPURegs:$incr))]>;
553 // Atomic Compare & Swap.
554 class AtomicCmpSwap<PatFrag Op, string Width> :
555 MipsPseudo<(outs CPURegs:$dst),
556 (ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
557 !strconcat("atomic_cmp_swap_", Width,
558 "\t$dst, $ptr, $cmp, $swap"),
560 (Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
562 //===----------------------------------------------------------------------===//
563 // Pseudo instructions
564 //===----------------------------------------------------------------------===//
566 // As stack alignment is always done with addiu, we need a 16-bit immediate
567 let Defs = [SP], Uses = [SP] in {
568 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
569 "!ADJCALLSTACKDOWN $amt",
570 [(callseq_start timm:$amt)]>;
571 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
572 "!ADJCALLSTACKUP $amt1",
573 [(callseq_end timm:$amt1, timm:$amt2)]>;
576 // Some assembly macros need to avoid pseudoinstructions and assembler
577 // automatic reodering, we should reorder ourselves.
578 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
579 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
580 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
581 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
583 // These macros are inserted to prevent GAS from complaining
584 // when using the AT register.
585 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
586 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
588 // When handling PIC code the assembler needs .cpload and .cprestore
589 // directives. If the real instructions corresponding these directives
590 // are used, we have the same behavior, but get also a bunch of warnings
591 // from the assembler.
592 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
593 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
595 let usesCustomInserter = 1 in {
596 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, "load_add_8">;
597 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, "load_add_16">;
598 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, "load_add_32">;
599 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, "load_sub_8">;
600 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, "load_sub_16">;
601 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, "load_sub_32">;
602 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, "load_and_8">;
603 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, "load_and_16">;
604 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, "load_and_32">;
605 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, "load_or_8">;
606 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, "load_or_16">;
607 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, "load_or_32">;
608 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, "load_xor_8">;
609 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, "load_xor_16">;
610 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, "load_xor_32">;
611 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, "load_nand_8">;
612 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, "load_nand_16">;
613 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, "load_nand_32">;
615 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, "swap_8">;
616 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, "swap_16">;
617 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, "swap_32">;
619 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
620 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
621 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
624 //===----------------------------------------------------------------------===//
625 // Instruction definition
626 //===----------------------------------------------------------------------===//
628 //===----------------------------------------------------------------------===//
629 // MipsI Instructions
630 //===----------------------------------------------------------------------===//
632 /// Arithmetic Instructions (ALU Immediate)
633 def ADDiu : ArithLogicI<0x09, "addiu", add, simm16, immSExt16, CPURegs>;
634 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16, CPURegs>;
635 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
636 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
637 def ANDi : ArithLogicI<0x0c, "andi", and, uimm16, immZExt16, CPURegs>;
638 def ORi : ArithLogicI<0x0d, "ori", or, uimm16, immZExt16, CPURegs>;
639 def XORi : ArithLogicI<0x0e, "xori", xor, uimm16, immZExt16, CPURegs>;
640 def LUi : LoadUpper<0x0f, "lui">;
642 /// Arithmetic Instructions (3-Operand, R-Type)
643 def ADDu : ArithLogicR<0x00, 0x21, "addu", add, IIAlu, CPURegs, 1>;
644 def SUBu : ArithLogicR<0x00, 0x23, "subu", sub, IIAlu, CPURegs>;
645 def ADD : ArithOverflowR<0x00, 0x20, "add", IIAlu, CPURegs, 1>;
646 def SUB : ArithOverflowR<0x00, 0x22, "sub", IIAlu, CPURegs>;
647 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
648 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
649 def AND : ArithLogicR<0x00, 0x24, "and", and, IIAlu, CPURegs, 1>;
650 def OR : ArithLogicR<0x00, 0x25, "or", or, IIAlu, CPURegs, 1>;
651 def XOR : ArithLogicR<0x00, 0x26, "xor", xor, IIAlu, CPURegs, 1>;
652 def NOR : LogicNOR<0x00, 0x27, "nor">;
654 /// Shift Instructions
655 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
656 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
657 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
658 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
659 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
660 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
662 // Rotate Instructions
663 let Predicates = [HasMips32r2] in {
664 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
665 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
668 /// Load and Store Instructions
670 defm LB : LoadM32<0x20, "lb", sextloadi8>;
671 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
672 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
673 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
674 defm LW : LoadM32<0x23, "lw", load_a>;
675 defm SB : StoreM32<0x28, "sb", truncstorei8>;
676 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
677 defm SW : StoreM32<0x2b, "sw", store_a>;
680 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
681 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
682 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
683 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
684 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
686 let hasSideEffects = 1 in
687 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
688 [(MipsSync imm:$stype)], NoItinerary>
695 /// Load-linked, Store-conditional
697 def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
698 "ll\t$dst, $addr", [], IILoad>;
699 let mayStore = 1, Constraints = "$src = $dst" in
700 def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
701 "sc\t$src, $addr", [], IIStore>;
703 /// Jump and Branch Instructions
704 def J : JumpFJ<0x02, "j">;
705 let isIndirectBranch = 1 in
706 def JR : JumpFR<0x00, 0x08, "jr">;
707 def JAL : JumpLink<0x03, "jal">;
708 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
709 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
710 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
711 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
712 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
713 def BLEZ : CBranchZero<0x07, 0, "blez", setle, CPURegs>;
714 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
716 def BGEZAL : BranchLink<"bgezal">;
717 def BLTZAL : BranchLink<"bltzal">;
719 let isReturn=1, isTerminator=1, hasDelaySlot=1,
720 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
721 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
722 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
724 /// Multiply and Divide Instructions.
725 def MULT : Mul<0x18, "mult", IIImul>;
726 def MULTu : Mul<0x19, "multu", IIImul>;
727 def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
728 def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
731 def MTHI : MoveToLOHI<0x11, "mthi">;
733 def MTLO : MoveToLOHI<0x13, "mtlo">;
736 def MFHI : MoveFromLOHI<0x10, "mfhi">;
738 def MFLO : MoveFromLOHI<0x12, "mflo">;
740 /// Sign Ext In Register Instructions.
741 def SEB : SignExtInReg<0x10, "seb", i8>;
742 def SEH : SignExtInReg<0x18, "seh", i16>;
745 def CLZ : CountLeading<0x20, "clz",
746 [(set CPURegs:$rd, (ctlz CPURegs:$rs))]>;
747 def CLO : CountLeading<0x21, "clo",
748 [(set CPURegs:$rd, (ctlz (not CPURegs:$rs)))]>;
751 def WSBW : ByteSwap<0x20, 0x2, "wsbw">;
753 // Conditional moves:
754 // These instructions are expanded in
755 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
756 // conditional move instructions.
757 // flag:int, data:int
758 class CondMovIntInt<bits<6> funct, string instr_asm> :
759 FR<0, funct, (outs CPURegs:$rd),
760 (ins CPURegs:$rs, CPURegs:$rt, CPURegs:$F),
761 !strconcat(instr_asm, "\t$rd, $rs, $rt"), [], NoItinerary> {
763 let usesCustomInserter = 1;
764 let Constraints = "$F = $rd";
767 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
768 def MOVN_I : CondMovIntInt<0x0b, "movn">;
772 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
774 // FrameIndexes are legalized when they are operands from load/store
775 // instructions. The same not happens for stack address copies, so an
776 // add op with mem ComplexPattern is used and the stack address copy
777 // can be matched. It's similar to Sparc LEA_ADDRi
778 def LEA_ADDiu : EffectiveAddress<"addiu\t$rt, $addr">;
780 // DynAlloc node points to dynamically allocated stack space.
781 // $sp is added to the list of implicitly used registers to prevent dead code
782 // elimination from removing instructions that modify $sp.
784 def DynAlloc : EffectiveAddress<"addiu\t$rt, $addr">;
787 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
788 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
789 def MSUB : MArithR<4, "msub", MipsMSub>;
790 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
792 // MUL is a assembly macro in the current used ISAs. In recent ISA's
793 // it is a real instruction.
794 def MUL : ArithLogicR<0x1c, 0x02, "mul", mul, IIImul, CPURegs, 1>,
795 Requires<[HasMips32]>;
797 def RDHWR : ReadHardware;
799 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
800 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
802 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
805 let Constraints = "$src = $rt" in
806 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
807 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
809 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
813 //===----------------------------------------------------------------------===//
814 // Arbitrary patterns that map to one or more instructions
815 //===----------------------------------------------------------------------===//
818 def : Pat<(i32 immSExt16:$in),
819 (ADDiu ZERO, imm:$in)>;
820 def : Pat<(i32 immZExt16:$in),
821 (ORi ZERO, imm:$in)>;
823 // Arbitrary immediates
824 def : Pat<(i32 imm:$imm),
825 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
828 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
829 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
830 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
831 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
832 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
833 (ADDiu CPURegs:$src, imm:$imm)>;
836 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
837 (JAL tglobaladdr:$dst)>;
838 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
839 (JAL texternalsym:$dst)>;
840 //def : Pat<(MipsJmpLink CPURegs:$dst),
841 // (JALR CPURegs:$dst)>;
844 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
845 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
846 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
847 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
848 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
849 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
850 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
851 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
853 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
854 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
855 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
856 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
858 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
859 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
860 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
861 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
864 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
865 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
866 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
867 (ADDiu CPURegs:$gp, tconstpool:$in)>;
870 def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
871 (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
874 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
875 def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
876 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
877 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
880 class WrapperPICPat<SDNode node>:
881 Pat<(MipsWrapperPIC node:$in),
882 (ADDiu GP, node:$in)>;
884 def : WrapperPICPat<tglobaladdr>;
885 def : WrapperPICPat<tconstpool>;
886 def : WrapperPICPat<texternalsym>;
887 def : WrapperPICPat<tblockaddress>;
888 def : WrapperPICPat<tjumptable>;
890 // Mips does not have "not", so we expand our way
891 def : Pat<(not CPURegs:$in),
892 (NOR CPURegs:$in, ZERO)>;
894 // extended load and stores
895 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
896 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
897 def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>;
898 def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
901 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
904 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
905 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
906 Instruction SLTiuOp, Register ZEROReg> {
907 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
908 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
909 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
910 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
912 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
913 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
914 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
915 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
916 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
917 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
918 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
919 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
921 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
922 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
923 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
924 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
926 def : Pat<(brcond RC:$cond, bb:$dst),
927 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
930 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
933 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
934 def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
935 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
936 def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
937 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
938 def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
939 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
940 def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
941 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
942 def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
943 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
944 def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
945 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
946 def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
947 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
948 def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
949 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
952 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
953 def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
954 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
955 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
956 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
957 def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
958 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
961 defm : MovzPats<CPURegs, MOVZ_I>;
962 defm : MovnPats<CPURegs, MOVN_I>;
965 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
966 Instruction SLTuOp, Register ZEROReg> {
967 def : Pat<(seteq RC:$lhs, RC:$rhs),
968 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
969 def : Pat<(setne RC:$lhs, RC:$rhs),
970 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
973 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
974 def : Pat<(setle RC:$lhs, RC:$rhs),
975 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
976 def : Pat<(setule RC:$lhs, RC:$rhs),
977 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
980 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
981 def : Pat<(setgt RC:$lhs, RC:$rhs),
982 (SLTOp RC:$rhs, RC:$lhs)>;
983 def : Pat<(setugt RC:$lhs, RC:$rhs),
984 (SLTuOp RC:$rhs, RC:$lhs)>;
987 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
988 def : Pat<(setge RC:$lhs, RC:$rhs),
989 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
990 def : Pat<(setuge RC:$lhs, RC:$rhs),
991 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
994 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
995 Instruction SLTiuOp> {
996 def : Pat<(setge RC:$lhs, immSExt16:$rhs),
997 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
998 def : Pat<(setuge RC:$lhs, immSExt16:$rhs),
999 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1002 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1003 defm : SetlePats<CPURegs, SLT, SLTu>;
1004 defm : SetgtPats<CPURegs, SLT, SLTu>;
1005 defm : SetgePats<CPURegs, SLT, SLTu>;
1006 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1008 // select MipsDynAlloc
1009 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
1011 //===----------------------------------------------------------------------===//
1012 // Floating Point Support
1013 //===----------------------------------------------------------------------===//
1015 include "MipsInstrFPU.td"
1016 include "Mips64InstrInfo.td"