1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget.hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget.hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget.hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget.hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget.hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget.hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget.hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget.hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget.hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget.hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget.hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget.isLittle()">;
202 def IsBE : Predicate<"!Subtarget.isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
244 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
245 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
247 // The portions of MIPS-III that were also added to MIPS32
248 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
253 // The portions of MIPS-IV that were also added to MIPS32
254 class INSN_MIPS4_32 { list<Predicate> InsnPredicates = [HasMips4_32]; }
256 // The portions of MIPS-IV that were also added to MIPS32R2
257 class INSN_MIPS4_32R2 { list<Predicate> InsnPredicates = [HasMips4_32r2]; }
259 // The portions of MIPS-V that were also added to MIPS32R2
260 class INSN_MIPS5_32R2 { list<Predicate> InsnPredicates = [HasMips5_32r2]; }
262 //===----------------------------------------------------------------------===//
264 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
265 let EncodingPredicates = [HasStdEnc];
268 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
269 InstAlias<Asm, Result, Emit>, PredicateControl;
272 bit isCommutable = 1;
289 bit isTerminator = 1;
292 bit hasExtraSrcRegAllocReq = 1;
293 bit isCodeGenOnly = 1;
296 class IsAsCheapAsAMove {
297 bit isAsCheapAsAMove = 1;
300 class NeverHasSideEffects {
301 bit neverHasSideEffects = 1;
304 //===----------------------------------------------------------------------===//
305 // Instruction format superclass
306 //===----------------------------------------------------------------------===//
308 include "MipsInstrFormats.td"
310 //===----------------------------------------------------------------------===//
311 // Mips Operand, Complex Patterns and Transformations Definitions.
312 //===----------------------------------------------------------------------===//
314 def MipsJumpTargetAsmOperand : AsmOperandClass {
315 let Name = "JumpTarget";
316 let ParserMethod = "ParseJumpTarget";
317 let PredicateMethod = "isImm";
318 let RenderMethod = "addImmOperands";
321 // Instruction operand types
322 def jmptarget : Operand<OtherVT> {
323 let EncoderMethod = "getJumpTargetOpValue";
324 let ParserMatchClass = MipsJumpTargetAsmOperand;
326 def brtarget : Operand<OtherVT> {
327 let EncoderMethod = "getBranchTargetOpValue";
328 let OperandType = "OPERAND_PCREL";
329 let DecoderMethod = "DecodeBranchTarget";
330 let ParserMatchClass = MipsJumpTargetAsmOperand;
332 def calltarget : Operand<iPTR> {
333 let EncoderMethod = "getJumpTargetOpValue";
334 let ParserMatchClass = MipsJumpTargetAsmOperand;
337 def simm10 : Operand<i32>;
339 def simm16 : Operand<i32> {
340 let DecoderMethod= "DecodeSimm16";
343 def simm19_lsl2 : Operand<i32> {
344 let EncoderMethod = "getSimm19Lsl2Encoding";
345 let DecoderMethod = "DecodeSimm19Lsl2";
346 let ParserMatchClass = MipsJumpTargetAsmOperand;
349 def simm18_lsl3 : Operand<i32> {
350 let EncoderMethod = "getSimm18Lsl3Encoding";
351 let DecoderMethod = "DecodeSimm18Lsl3";
354 def simm20 : Operand<i32> {
357 def uimm20 : Operand<i32> {
360 def uimm10 : Operand<i32> {
363 def simm16_64 : Operand<i64> {
364 let DecoderMethod = "DecodeSimm16";
368 def uimmz : Operand<i32> {
369 let PrintMethod = "printUnsignedImm";
373 def uimm2 : Operand<i32> {
374 let PrintMethod = "printUnsignedImm";
377 def uimm3 : Operand<i32> {
378 let PrintMethod = "printUnsignedImm";
381 def uimm5 : Operand<i32> {
382 let PrintMethod = "printUnsignedImm";
385 def uimm6 : Operand<i32> {
386 let PrintMethod = "printUnsignedImm";
389 def uimm16 : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
393 def pcrel16 : Operand<i32> {
396 def MipsMemAsmOperand : AsmOperandClass {
398 let ParserMethod = "parseMemOperand";
401 def MipsInvertedImmoperand : AsmOperandClass {
403 let RenderMethod = "addImmOperands";
404 let ParserMethod = "parseInvNum";
407 def InvertedImOperand : Operand<i32> {
408 let ParserMatchClass = MipsInvertedImmoperand;
411 def InvertedImOperand64 : Operand<i64> {
412 let ParserMatchClass = MipsInvertedImmoperand;
415 class mem_generic : Operand<iPTR> {
416 let PrintMethod = "printMemOperand";
417 let MIOperandInfo = (ops ptr_rc, simm16);
418 let EncoderMethod = "getMemEncoding";
419 let ParserMatchClass = MipsMemAsmOperand;
420 let OperandType = "OPERAND_MEMORY";
424 def mem : mem_generic;
426 // MSA specific address operand
427 def mem_msa : mem_generic {
428 let MIOperandInfo = (ops ptr_rc, simm10);
429 let EncoderMethod = "getMSAMemEncoding";
432 def mem_ea : Operand<iPTR> {
433 let PrintMethod = "printMemOperandEA";
434 let MIOperandInfo = (ops ptr_rc, simm16);
435 let EncoderMethod = "getMemEncoding";
436 let OperandType = "OPERAND_MEMORY";
439 def PtrRC : Operand<iPTR> {
440 let MIOperandInfo = (ops ptr_rc);
441 let DecoderMethod = "DecodePtrRegisterClass";
442 let ParserMatchClass = GPR32AsmOperand;
445 // size operand of ext instruction
446 def size_ext : Operand<i32> {
447 let EncoderMethod = "getSizeExtEncoding";
448 let DecoderMethod = "DecodeExtSize";
451 // size operand of ins instruction
452 def size_ins : Operand<i32> {
453 let EncoderMethod = "getSizeInsEncoding";
454 let DecoderMethod = "DecodeInsSize";
457 // Transformation Function - get the lower 16 bits.
458 def LO16 : SDNodeXForm<imm, [{
459 return getImm(N, N->getZExtValue() & 0xFFFF);
462 // Transformation Function - get the higher 16 bits.
463 def HI16 : SDNodeXForm<imm, [{
464 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
468 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
470 // Node immediate is zero (e.g. insve.d)
471 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
473 // Node immediate fits as 16-bit sign extended on target immediate.
475 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
477 // Node immediate fits as 16-bit sign extended on target immediate.
479 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
481 // Node immediate fits as 15-bit sign extended on target immediate.
483 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
485 // Node immediate fits as 16-bit zero extended on target immediate.
486 // The LO16 param means that only the lower 16 bits of the node
487 // immediate are caught.
489 def immZExt16 : PatLeaf<(imm), [{
490 if (N->getValueType(0) == MVT::i32)
491 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
493 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
496 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
497 def immLow16Zero : PatLeaf<(imm), [{
498 int64_t Val = N->getSExtValue();
499 return isInt<32>(Val) && !(Val & 0xffff);
502 // shamt field must fit in 5 bits.
503 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
505 // True if (N + 1) fits in 16-bit field.
506 def immSExt16Plus1 : PatLeaf<(imm), [{
507 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
510 // Mips Address Mode! SDNode frameindex could possibily be a match
511 // since load and store instructions from stack used it.
513 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
516 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
519 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
522 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
524 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
526 //===----------------------------------------------------------------------===//
527 // Instructions specific format
528 //===----------------------------------------------------------------------===//
530 // Arithmetic and logical instructions with 3 register operands.
531 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
532 InstrItinClass Itin = NoItinerary,
533 SDPatternOperator OpNode = null_frag>:
534 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
535 !strconcat(opstr, "\t$rd, $rs, $rt"),
536 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
537 let isCommutable = isComm;
538 let isReMaterializable = 1;
539 let TwoOperandAliasConstraint = "$rd = $rs";
542 // Arithmetic and logical instructions with 2 register operands.
543 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
544 InstrItinClass Itin = NoItinerary,
545 SDPatternOperator imm_type = null_frag,
546 SDPatternOperator OpNode = null_frag> :
547 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
548 !strconcat(opstr, "\t$rt, $rs, $imm16"),
549 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
551 let isReMaterializable = 1;
552 let TwoOperandAliasConstraint = "$rs = $rt";
555 // Arithmetic Multiply ADD/SUB
556 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
557 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
558 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
559 let Defs = [HI0, LO0];
560 let Uses = [HI0, LO0];
561 let isCommutable = isComm;
565 class LogicNOR<string opstr, RegisterOperand RO>:
566 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
567 !strconcat(opstr, "\t$rd, $rs, $rt"),
568 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
569 let isCommutable = 1;
573 class shift_rotate_imm<string opstr, Operand ImmOpnd,
574 RegisterOperand RO, InstrItinClass itin,
575 SDPatternOperator OpNode = null_frag,
576 SDPatternOperator PF = null_frag> :
577 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
578 !strconcat(opstr, "\t$rd, $rt, $shamt"),
579 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
580 let TwoOperandAliasConstraint = "$rt = $rd";
583 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
584 SDPatternOperator OpNode = null_frag>:
585 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
586 !strconcat(opstr, "\t$rd, $rt, $rs"),
587 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
590 // Load Upper Imediate
591 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
592 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
593 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
594 let neverHasSideEffects = 1;
595 let isReMaterializable = 1;
599 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
600 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
601 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
602 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
603 let DecoderMethod = "DecodeMem";
604 let canFoldAsLoad = 1;
608 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
609 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
610 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
611 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
612 let DecoderMethod = "DecodeMem";
616 // Load/Store Left/Right
617 let canFoldAsLoad = 1 in
618 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
619 InstrItinClass Itin> :
620 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
621 !strconcat(opstr, "\t$rt, $addr"),
622 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
623 let DecoderMethod = "DecodeMem";
624 string Constraints = "$src = $rt";
627 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
628 InstrItinClass Itin> :
629 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
630 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
631 let DecoderMethod = "DecodeMem";
634 // Conditional Branch
635 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
636 RegisterOperand RO> :
637 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
638 !strconcat(opstr, "\t$rs, $rt, $offset"),
639 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
642 let isTerminator = 1;
643 let hasDelaySlot = 1;
647 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
648 RegisterOperand RO> :
649 InstSE<(outs), (ins RO:$rs, opnd:$offset),
650 !strconcat(opstr, "\t$rs, $offset"),
651 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
654 let isTerminator = 1;
655 let hasDelaySlot = 1;
660 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
661 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
662 !strconcat(opstr, "\t$rd, $rs, $rt"),
663 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
664 II_SLT_SLTU, FrmR, opstr>;
666 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
668 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
669 !strconcat(opstr, "\t$rt, $rs, $imm16"),
670 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
671 II_SLTI_SLTIU, FrmI, opstr>;
674 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
675 SDPatternOperator targetoperator, string bopstr> :
676 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
677 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
680 let hasDelaySlot = 1;
681 let DecoderMethod = "DecodeJumpTarget";
685 // Unconditional branch
686 class UncondBranch<Instruction BEQInst> :
687 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
688 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
690 let isTerminator = 1;
692 let hasDelaySlot = 1;
693 let AdditionalPredicates = [RelocPIC];
697 // Base class for indirect branch and return instruction classes.
698 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
699 class JumpFR<string opstr, RegisterOperand RO,
700 SDPatternOperator operator = null_frag>:
701 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
705 class IndirectBranch<string opstr, RegisterOperand RO> :
706 JumpFR<opstr, RO, brind> {
708 let isIndirectBranch = 1;
711 // Return instruction
712 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
714 let isCodeGenOnly = 1;
716 let hasExtraSrcRegAllocReq = 1;
719 // Jump and Link (Call)
720 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
721 class JumpLink<string opstr, DAGOperand opnd> :
722 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
723 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
724 let DecoderMethod = "DecodeJumpTarget";
727 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
728 Register RetReg, RegisterOperand ResRO = RO>:
729 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
730 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
732 class JumpLinkReg<string opstr, RegisterOperand RO>:
733 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
736 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
737 InstSE<(outs), (ins RO:$rs, opnd:$offset),
738 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
742 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
743 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
744 class TailCall<Instruction JumpInst> :
745 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
746 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
748 class TailCallReg<RegisterOperand RO, Instruction JRInst,
749 RegisterOperand ResRO = RO> :
750 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
751 PseudoInstExpansion<(JRInst ResRO:$rs)>;
754 class BAL_BR_Pseudo<Instruction RealInst> :
755 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
756 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
758 let isTerminator = 1;
760 let hasDelaySlot = 1;
765 class SYS_FT<string opstr> :
766 InstSE<(outs), (ins uimm20:$code_),
767 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
769 class BRK_FT<string opstr> :
770 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
771 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
775 class ER_FT<string opstr> :
776 InstSE<(outs), (ins),
777 opstr, [], NoItinerary, FrmOther, opstr>;
780 class DEI_FT<string opstr, RegisterOperand RO> :
781 InstSE<(outs RO:$rt), (ins),
782 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
785 class WAIT_FT<string opstr> :
786 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
789 let hasSideEffects = 1 in
790 class SYNC_FT<string opstr> :
791 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
792 NoItinerary, FrmOther, opstr>;
794 let hasSideEffects = 1 in
795 class TEQ_FT<string opstr, RegisterOperand RO> :
796 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
797 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
800 class TEQI_FT<string opstr, RegisterOperand RO> :
801 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
802 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
804 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
805 list<Register> DefRegs> :
806 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
808 let isCommutable = 1;
810 let neverHasSideEffects = 1;
813 // Pseudo multiply/divide instruction with explicit accumulator register
815 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
816 SDPatternOperator OpNode, InstrItinClass Itin,
817 bit IsComm = 1, bit HasSideEffects = 0,
818 bit UsesCustomInserter = 0> :
819 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
820 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
821 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
822 let isCommutable = IsComm;
823 let hasSideEffects = HasSideEffects;
824 let usesCustomInserter = UsesCustomInserter;
827 // Pseudo multiply add/sub instruction with explicit accumulator register
829 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
831 : PseudoSE<(outs ACC64:$ac),
832 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
834 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
836 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
837 string Constraints = "$acin = $ac";
840 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
841 list<Register> DefRegs> :
842 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
843 [], itin, FrmR, opstr> {
848 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
849 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
850 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
852 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
853 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
856 let neverHasSideEffects = 1;
859 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
860 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
861 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
864 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
865 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
868 let neverHasSideEffects = 1;
871 class EffectiveAddress<string opstr, RegisterOperand RO> :
872 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
873 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
874 !strconcat(opstr, "_lea")> {
875 let isCodeGenOnly = 1;
876 let DecoderMethod = "DecodeMem";
879 // Count Leading Ones/Zeros in Word
880 class CountLeading0<string opstr, RegisterOperand RO>:
881 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
882 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
884 class CountLeading1<string opstr, RegisterOperand RO>:
885 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
886 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
888 // Sign Extend in Register.
889 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
890 InstrItinClass itin> :
891 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
892 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
895 class SubwordSwap<string opstr, RegisterOperand RO>:
896 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
897 NoItinerary, FrmR, opstr> {
898 let neverHasSideEffects = 1;
902 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
903 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
907 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
908 SDPatternOperator Op = null_frag>:
909 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
910 !strconcat(opstr, " $rt, $rs, $pos, $size"),
911 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
912 FrmR, opstr>, ISA_MIPS32R2;
914 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
915 SDPatternOperator Op = null_frag>:
916 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
917 !strconcat(opstr, " $rt, $rs, $pos, $size"),
918 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
919 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
920 let Constraints = "$src = $rt";
923 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
924 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
925 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
926 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
928 // Atomic Compare & Swap.
929 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
930 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
931 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
933 class LLBase<string opstr, RegisterOperand RO> :
934 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
935 [], NoItinerary, FrmI> {
936 let DecoderMethod = "DecodeMem";
940 class SCBase<string opstr, RegisterOperand RO> :
941 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
942 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
943 let DecoderMethod = "DecodeMem";
945 let Constraints = "$rt = $dst";
948 class MFC3OP<string asmstr, RegisterOperand RO> :
949 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
950 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
952 class TrapBase<Instruction RealInst>
953 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
954 PseudoInstExpansion<(RealInst 0, 0)> {
956 let isTerminator = 1;
957 let isCodeGenOnly = 1;
960 //===----------------------------------------------------------------------===//
961 // Pseudo instructions
962 //===----------------------------------------------------------------------===//
965 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
966 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
968 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
969 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
970 [(callseq_start timm:$amt)]>;
971 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
972 [(callseq_end timm:$amt1, timm:$amt2)]>;
975 let usesCustomInserter = 1 in {
976 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
977 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
978 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
979 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
980 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
981 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
982 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
983 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
984 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
985 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
986 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
987 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
988 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
989 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
990 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
991 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
992 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
993 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
995 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
996 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
997 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
999 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1000 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1001 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1004 /// Pseudo instructions for loading and storing accumulator registers.
1005 let isPseudo = 1, isCodeGenOnly = 1 in {
1006 def LOAD_ACC64 : Load<"", ACC64>;
1007 def STORE_ACC64 : Store<"", ACC64>;
1010 // We need these two pseudo instructions to avoid offset calculation for long
1011 // branches. See the comment in file MipsLongBranch.cpp for detailed
1014 // Expands to: lui $dst, %hi($tgt - $baltgt)
1015 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1016 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1018 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1019 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1020 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1022 //===----------------------------------------------------------------------===//
1023 // Instruction definition
1024 //===----------------------------------------------------------------------===//
1025 //===----------------------------------------------------------------------===//
1026 // MipsI Instructions
1027 //===----------------------------------------------------------------------===//
1029 /// Arithmetic Instructions (ALU Immediate)
1030 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1032 ADDI_FM<0x9>, IsAsCheapAsAMove;
1033 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1034 ISA_MIPS1_NOT_32R6_64R6;
1035 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1037 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1039 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1042 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1045 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1048 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1050 /// Arithmetic Instructions (3-Operand, R-Type)
1051 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1053 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1055 let Defs = [HI0, LO0] in
1056 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1057 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1058 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1059 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1060 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1061 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1062 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1064 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1066 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1068 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1070 /// Shift Instructions
1071 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1072 immZExt5>, SRA_FM<0, 0>;
1073 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1074 immZExt5>, SRA_FM<2, 0>;
1075 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1076 immZExt5>, SRA_FM<3, 0>;
1077 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1079 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1081 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1084 // Rotate Instructions
1085 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1087 SRA_FM<2, 1>, ISA_MIPS32R2;
1088 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1089 SRLV_FM<6, 1>, ISA_MIPS32R2;
1091 /// Load and Store Instructions
1093 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1094 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1096 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1098 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1099 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1101 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1102 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1103 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1105 /// load/store left/right
1106 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1107 AdditionalPredicates = [NotInMicroMips] in {
1108 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1109 ISA_MIPS1_NOT_32R6_64R6;
1110 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1111 ISA_MIPS1_NOT_32R6_64R6;
1112 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1113 ISA_MIPS1_NOT_32R6_64R6;
1114 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1115 ISA_MIPS1_NOT_32R6_64R6;
1118 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1119 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1120 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1121 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1122 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1123 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1124 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1126 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1127 ISA_MIPS2_NOT_32R6_64R6;
1128 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1129 ISA_MIPS2_NOT_32R6_64R6;
1130 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1131 ISA_MIPS2_NOT_32R6_64R6;
1132 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1133 ISA_MIPS2_NOT_32R6_64R6;
1134 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1135 ISA_MIPS2_NOT_32R6_64R6;
1136 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1137 ISA_MIPS2_NOT_32R6_64R6;
1139 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1140 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1141 def TRAP : TrapBase<BREAK>;
1143 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1144 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1146 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1147 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1149 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1150 AdditionalPredicates = [NotInMicroMips] in {
1151 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1153 /// Load-linked, Store-conditional
1154 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2;
1155 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2;
1158 /// Jump and Branch Instructions
1159 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1160 AdditionalRequires<[RelocStatic]>, IsBranch;
1161 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1162 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1163 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1164 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1166 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1168 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1170 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1172 def B : UncondBranch<BEQ>;
1174 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1175 let AdditionalPredicates = [NotInMicroMips] in {
1176 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1177 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1180 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1181 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1182 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1183 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1184 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1185 def TAILCALL : TailCall<J>;
1186 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1188 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1190 // Exception handling related node and instructions.
1191 // The conversion sequence is:
1192 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1193 // MIPSeh_return -> (stack change + indirect branch)
1195 // MIPSeh_return takes the place of regular return instruction
1196 // but takes two arguments (V1, V0) which are used for storing
1197 // the offset and return address respectively.
1198 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1200 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1201 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1203 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1204 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1205 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1206 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1208 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1211 /// Multiply and Divide Instructions.
1212 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1213 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1214 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1215 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1216 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1217 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1218 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1219 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1221 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1222 ISA_MIPS1_NOT_32R6_64R6;
1223 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1224 ISA_MIPS1_NOT_32R6_64R6;
1225 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1226 AdditionalPredicates = [NotInMicroMips] in {
1227 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1228 ISA_MIPS1_NOT_32R6_64R6;
1229 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1230 ISA_MIPS1_NOT_32R6_64R6;
1233 /// Sign Ext In Register Instructions.
1234 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1235 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1236 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1237 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1240 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>, ISA_MIPS32;
1241 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>, ISA_MIPS32;
1243 /// Word Swap Bytes Within Halfwords
1244 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1247 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1249 // FrameIndexes are legalized when they are operands from load/store
1250 // instructions. The same not happens for stack address copies, so an
1251 // add op with mem ComplexPattern is used and the stack address copy
1252 // can be matched. It's similar to Sparc LEA_ADDRi
1253 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1256 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1257 ISA_MIPS32_NOT_32R6_64R6;
1258 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1259 ISA_MIPS32_NOT_32R6_64R6;
1260 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1261 ISA_MIPS32_NOT_32R6_64R6;
1262 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1263 ISA_MIPS32_NOT_32R6_64R6;
1265 let AdditionalPredicates = [NotDSP] in {
1266 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1267 ISA_MIPS1_NOT_32R6_64R6;
1268 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1269 ISA_MIPS1_NOT_32R6_64R6;
1270 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1271 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1272 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1273 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1274 ISA_MIPS32_NOT_32R6_64R6;
1275 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1276 ISA_MIPS32_NOT_32R6_64R6;
1277 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1278 ISA_MIPS32_NOT_32R6_64R6;
1279 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1280 ISA_MIPS32_NOT_32R6_64R6;
1283 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1284 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1285 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1286 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1288 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1290 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1291 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1293 /// Move Control Registers From/To CPU Registers
1294 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1295 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1296 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1297 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1299 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1301 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1302 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1303 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1305 // JR_HB and JALR_HB are defined here using the new style naming
1306 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1307 // and because of that it doesn't follow the naming convention of the
1308 // rest of the file. To avoid a mixture of old vs new style, the new
1309 // style was chosen.
1310 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1311 dag OutOperandList = (outs);
1312 dag InOperandList = (ins GPROpnd:$rs);
1313 string AsmString = !strconcat(instr_asm, "\t$rs");
1314 list<dag> Pattern = [];
1317 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1318 dag OutOperandList = (outs GPROpnd:$rd);
1319 dag InOperandList = (ins GPROpnd:$rs);
1320 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1321 list<dag> Pattern = [];
1324 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1325 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1327 let isIndirectBranch=1;
1333 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1334 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1335 let isIndirectBranch=1;
1339 class JR_HB_ENC : JR_HB_FM<8>;
1340 class JALR_HB_ENC : JALR_HB_FM<9>;
1342 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1343 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1345 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1347 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1348 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1349 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1350 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1352 //===----------------------------------------------------------------------===//
1353 // Instruction aliases
1354 //===----------------------------------------------------------------------===//
1355 def : MipsInstAlias<"move $dst, $src",
1356 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1358 let AdditionalPredicates = [NotInMicroMips];
1360 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1361 def : MipsInstAlias<"addu $rs, $rt, $imm",
1362 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1363 def : MipsInstAlias<"add $rs, $rt, $imm",
1364 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1365 def : MipsInstAlias<"and $rs, $rt, $imm",
1366 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1367 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1368 let Predicates = [NotInMicroMips] in {
1369 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1371 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1372 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1373 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1374 def : MipsInstAlias<"not $rt, $rs",
1375 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1376 def : MipsInstAlias<"neg $rt, $rs",
1377 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1378 def : MipsInstAlias<"negu $rt",
1379 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1380 def : MipsInstAlias<"negu $rt, $rs",
1381 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1382 def : MipsInstAlias<"slt $rs, $rt, $imm",
1383 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1384 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1385 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1386 def : MipsInstAlias<"xor $rs, $rt, $imm",
1387 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1388 def : MipsInstAlias<"or $rs, $rt, $imm",
1389 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1390 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1391 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1392 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1393 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1394 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1395 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1396 def : MipsInstAlias<"bnez $rs,$offset",
1397 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1398 def : MipsInstAlias<"beqz $rs,$offset",
1399 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1400 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1402 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1403 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1404 def : MipsInstAlias<"ei", (EI ZERO), 1>;
1405 def : MipsInstAlias<"di", (DI ZERO), 1>;
1407 def : MipsInstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1408 def : MipsInstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1409 def : MipsInstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1411 def : MipsInstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1412 def : MipsInstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0),
1414 def : MipsInstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1415 def : MipsInstAlias<"sll $rd, $rt, $rs",
1416 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1417 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1418 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1419 InvertedImOperand:$imm), 0>;
1420 def : MipsInstAlias<"sub $rs, $imm",
1421 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1423 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1424 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1425 InvertedImOperand:$imm), 0>;
1426 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1427 InvertedImOperand:$imm), 0>;
1428 def : MipsInstAlias<"sra $rd, $rt, $rs",
1429 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1430 def : MipsInstAlias<"srl $rd, $rt, $rs",
1431 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1432 //===----------------------------------------------------------------------===//
1433 // Assembler Pseudo Instructions
1434 //===----------------------------------------------------------------------===//
1436 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1437 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1438 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1439 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1441 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1442 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1443 !strconcat(instr_asm, "\t$rt, $addr")> ;
1444 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1446 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1447 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1448 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1449 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1451 //===----------------------------------------------------------------------===//
1452 // Arbitrary patterns that map to one or more instructions
1453 //===----------------------------------------------------------------------===//
1455 // Load/store pattern templates.
1456 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1457 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1459 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1460 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1463 def : MipsPat<(i32 immSExt16:$in),
1464 (ADDiu ZERO, imm:$in)>;
1465 def : MipsPat<(i32 immZExt16:$in),
1466 (ORi ZERO, imm:$in)>;
1467 def : MipsPat<(i32 immLow16Zero:$in),
1468 (LUi (HI16 imm:$in))>;
1470 // Arbitrary immediates
1471 def : MipsPat<(i32 imm:$imm),
1472 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1474 // Carry MipsPatterns
1475 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1476 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1477 let AdditionalPredicates = [NotDSP] in {
1478 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1479 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1480 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1481 (ADDiu GPR32:$src, imm:$imm)>;
1485 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1486 (JAL tglobaladdr:$dst)>;
1487 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1488 (JAL texternalsym:$dst)>;
1489 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1490 // (JALR GPR32:$dst)>;
1493 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1494 (TAILCALL tglobaladdr:$dst)>;
1495 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1496 (TAILCALL texternalsym:$dst)>;
1498 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1499 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1500 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1501 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1502 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1503 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1505 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1506 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1507 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1508 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1509 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1510 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1512 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1513 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1514 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1515 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1516 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1517 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1518 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1519 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1520 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1521 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1524 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1525 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1526 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1527 (ADDiu GPR32:$gp, tconstpool:$in)>;
1530 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1531 MipsPat<(MipsWrapper RC:$gp, node:$in),
1532 (ADDiuOp RC:$gp, node:$in)>;
1534 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1535 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1536 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1537 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1538 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1539 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1541 // Mips does not have "not", so we expand our way
1542 def : MipsPat<(not GPR32:$in),
1543 (NOR GPR32Opnd:$in, ZERO)>;
1546 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1547 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1548 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1551 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1554 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1555 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1556 Instruction SLTiuOp, Register ZEROReg> {
1557 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1558 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1559 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1560 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1562 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1563 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1564 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1565 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1566 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1567 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1568 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1569 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1570 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1571 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1572 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1573 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1575 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1576 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1577 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1578 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1580 def : MipsPat<(brcond RC:$cond, bb:$dst),
1581 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1584 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1586 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1587 (BLEZ i32:$lhs, bb:$dst)>;
1588 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1589 (BGEZ i32:$lhs, bb:$dst)>;
1592 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1593 Instruction SLTuOp, Register ZEROReg> {
1594 def : MipsPat<(seteq RC:$lhs, 0),
1595 (SLTiuOp RC:$lhs, 1)>;
1596 def : MipsPat<(setne RC:$lhs, 0),
1597 (SLTuOp ZEROReg, RC:$lhs)>;
1598 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1599 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1600 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1601 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1604 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1605 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1606 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1607 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1608 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1611 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1612 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1613 (SLTOp RC:$rhs, RC:$lhs)>;
1614 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1615 (SLTuOp RC:$rhs, RC:$lhs)>;
1618 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1619 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1620 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1621 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1622 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1625 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1626 Instruction SLTiuOp> {
1627 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1628 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1629 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1630 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1633 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1634 defm : SetlePats<GPR32, SLT, SLTu>;
1635 defm : SetgtPats<GPR32, SLT, SLTu>;
1636 defm : SetgePats<GPR32, SLT, SLTu>;
1637 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1640 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1642 // Load halfword/word patterns.
1643 let AddedComplexity = 40 in {
1644 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1645 def : LoadRegImmPat<LH, i32, sextloadi16>;
1646 def : LoadRegImmPat<LW, i32, load>;
1649 //===----------------------------------------------------------------------===//
1650 // Floating Point Support
1651 //===----------------------------------------------------------------------===//
1653 include "MipsInstrFPU.td"
1654 include "Mips64InstrInfo.td"
1655 include "MipsCondMov.td"
1657 include "Mips32r6InstrInfo.td"
1658 include "Mips64r6InstrInfo.td"
1663 include "Mips16InstrFormats.td"
1664 include "Mips16InstrInfo.td"
1667 include "MipsDSPInstrFormats.td"
1668 include "MipsDSPInstrInfo.td"
1671 include "MipsMSAInstrFormats.td"
1672 include "MipsMSAInstrInfo.td"
1675 include "MicroMipsInstrFormats.td"
1676 include "MicroMipsInstrInfo.td"
1677 include "MicroMipsInstrFPU.td"