1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"FeatureMips32r6">;
171 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"!FeatureMips32r6">;
173 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
176 AssemblerPredicate<"!FeatureGP64Bit">;
177 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
178 AssemblerPredicate<"FeatureMips64">;
179 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
180 AssemblerPredicate<"FeatureMips64r2">;
181 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"FeatureMips64r6">;
183 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"!FeatureMips64r6">;
185 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
186 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
187 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
188 AssemblerPredicate<"FeatureMips16">;
189 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
190 AssemblerPredicate<"FeatureCnMips">;
191 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
192 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_4_32 {
224 list<Predicate> InsnPredicates = [NotMips4_32];
226 class ISA_MIPS1_NOT_32R6_64R6 {
227 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
229 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
230 class ISA_MIPS2_NOT_32R6_64R6 {
231 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
233 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
234 class ISA_MIPS3_NOT_32R6_64R6 {
235 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
237 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
238 class ISA_MIPS32_NOT_32R6_64R6 {
239 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
241 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
242 class ISA_MIPS32R2_NOT_32R6_64R6 {
243 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
245 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
246 class ISA_MIPS64_NOT_64R6 {
247 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
249 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
250 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
251 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
252 class ISA_MICROMIPS32R6 {
253 list<Predicate> InsnPredicates = [HasMicroMips32r6];
256 // The portions of MIPS-III that were also added to MIPS32
257 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
259 // The portions of MIPS-III that were also added to MIPS32 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS3_32_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-III that were also added to MIPS32
266 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
268 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
280 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
281 // MIPS32r6 and MIPS64r6.
282 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
283 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
286 //===----------------------------------------------------------------------===//
288 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
289 let EncodingPredicates = [HasStdEnc];
292 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
293 InstAlias<Asm, Result, Emit>, PredicateControl;
296 bit isCommutable = 1;
313 bit isTerminator = 1;
316 bit hasExtraSrcRegAllocReq = 1;
317 bit isCodeGenOnly = 1;
320 class IsAsCheapAsAMove {
321 bit isAsCheapAsAMove = 1;
324 class NeverHasSideEffects {
325 bit hasSideEffects = 0;
328 //===----------------------------------------------------------------------===//
329 // Instruction format superclass
330 //===----------------------------------------------------------------------===//
332 include "MipsInstrFormats.td"
334 //===----------------------------------------------------------------------===//
335 // Mips Operand, Complex Patterns and Transformations Definitions.
336 //===----------------------------------------------------------------------===//
338 def MipsJumpTargetAsmOperand : AsmOperandClass {
339 let Name = "JumpTarget";
340 let ParserMethod = "parseJumpTarget";
341 let PredicateMethod = "isImm";
342 let RenderMethod = "addImmOperands";
345 // Instruction operand types
346 def jmptarget : Operand<OtherVT> {
347 let EncoderMethod = "getJumpTargetOpValue";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def brtarget : Operand<OtherVT> {
351 let EncoderMethod = "getBranchTargetOpValue";
352 let OperandType = "OPERAND_PCREL";
353 let DecoderMethod = "DecodeBranchTarget";
354 let ParserMatchClass = MipsJumpTargetAsmOperand;
356 def calltarget : Operand<iPTR> {
357 let EncoderMethod = "getJumpTargetOpValue";
358 let ParserMatchClass = MipsJumpTargetAsmOperand;
361 def imm64: Operand<i64>;
363 def simm9 : Operand<i32>;
364 def simm10 : Operand<i32>;
365 def simm11 : Operand<i32>;
367 def simm16 : Operand<i32> {
368 let DecoderMethod= "DecodeSimm16";
371 def simm19_lsl2 : Operand<i32> {
372 let EncoderMethod = "getSimm19Lsl2Encoding";
373 let DecoderMethod = "DecodeSimm19Lsl2";
374 let ParserMatchClass = MipsJumpTargetAsmOperand;
377 def simm18_lsl3 : Operand<i32> {
378 let EncoderMethod = "getSimm18Lsl3Encoding";
379 let DecoderMethod = "DecodeSimm18Lsl3";
380 let ParserMatchClass = MipsJumpTargetAsmOperand;
383 def simm20 : Operand<i32> {
386 def uimm20 : Operand<i32> {
389 def MipsUImm10AsmOperand : AsmOperandClass {
391 let RenderMethod = "addImmOperands";
392 let ParserMethod = "parseImm";
393 let PredicateMethod = "isUImm<10>";
396 def uimm10 : Operand<i32> {
397 let ParserMatchClass = MipsUImm10AsmOperand;
400 def simm16_64 : Operand<i64> {
401 let DecoderMethod = "DecodeSimm16";
405 def uimmz : Operand<i32> {
406 let PrintMethod = "printUnsignedImm";
410 def uimm2 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def uimm3 : Operand<i32> {
415 let PrintMethod = "printUnsignedImm";
418 def uimm5 : Operand<i32> {
419 let PrintMethod = "printUnsignedImm";
422 def uimm6 : Operand<i32> {
423 let PrintMethod = "printUnsignedImm";
426 def uimm16 : Operand<i32> {
427 let PrintMethod = "printUnsignedImm";
430 def pcrel16 : Operand<i32> {
433 def MipsMemAsmOperand : AsmOperandClass {
435 let ParserMethod = "parseMemOperand";
438 def MipsMemSimm11AsmOperand : AsmOperandClass {
439 let Name = "MemOffsetSimm11";
440 let SuperClasses = [MipsMemAsmOperand];
441 let RenderMethod = "addMemOperands";
442 let ParserMethod = "parseMemOperand";
443 let PredicateMethod = "isMemWithSimmOffset<11>";
446 def MipsMemSimm16AsmOperand : AsmOperandClass {
447 let Name = "MemOffsetSimm16";
448 let SuperClasses = [MipsMemAsmOperand];
449 let RenderMethod = "addMemOperands";
450 let ParserMethod = "parseMemOperand";
451 let PredicateMethod = "isMemWithSimmOffset<16>";
454 def MipsInvertedImmoperand : AsmOperandClass {
456 let RenderMethod = "addImmOperands";
457 let ParserMethod = "parseInvNum";
460 def InvertedImOperand : Operand<i32> {
461 let ParserMatchClass = MipsInvertedImmoperand;
464 def InvertedImOperand64 : Operand<i64> {
465 let ParserMatchClass = MipsInvertedImmoperand;
468 class mem_generic : Operand<iPTR> {
469 let PrintMethod = "printMemOperand";
470 let MIOperandInfo = (ops ptr_rc, simm16);
471 let EncoderMethod = "getMemEncoding";
472 let ParserMatchClass = MipsMemAsmOperand;
473 let OperandType = "OPERAND_MEMORY";
477 def mem : mem_generic;
479 // MSA specific address operand
480 def mem_msa : mem_generic {
481 let MIOperandInfo = (ops ptr_rc, simm10);
482 let EncoderMethod = "getMSAMemEncoding";
485 def mem_simm9 : mem_generic {
486 let MIOperandInfo = (ops ptr_rc, simm9);
487 let EncoderMethod = "getMemEncoding";
490 def mem_simm11 : mem_generic {
491 let MIOperandInfo = (ops ptr_rc, simm11);
492 let EncoderMethod = "getMemEncoding";
493 let ParserMatchClass = MipsMemSimm11AsmOperand;
496 def mem_simm16 : mem_generic {
497 let MIOperandInfo = (ops ptr_rc, simm16);
498 let EncoderMethod = "getMemEncoding";
499 let ParserMatchClass = MipsMemSimm16AsmOperand;
502 def mem_ea : Operand<iPTR> {
503 let PrintMethod = "printMemOperandEA";
504 let MIOperandInfo = (ops ptr_rc, simm16);
505 let EncoderMethod = "getMemEncoding";
506 let OperandType = "OPERAND_MEMORY";
509 def PtrRC : Operand<iPTR> {
510 let MIOperandInfo = (ops ptr_rc);
511 let DecoderMethod = "DecodePtrRegisterClass";
512 let ParserMatchClass = GPR32AsmOperand;
515 // size operand of ext instruction
516 def size_ext : Operand<i32> {
517 let EncoderMethod = "getSizeExtEncoding";
518 let DecoderMethod = "DecodeExtSize";
521 // size operand of ins instruction
522 def size_ins : Operand<i32> {
523 let EncoderMethod = "getSizeInsEncoding";
524 let DecoderMethod = "DecodeInsSize";
527 // Transformation Function - get the lower 16 bits.
528 def LO16 : SDNodeXForm<imm, [{
529 return getImm(N, N->getZExtValue() & 0xFFFF);
532 // Transformation Function - get the higher 16 bits.
533 def HI16 : SDNodeXForm<imm, [{
534 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
538 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
540 // Node immediate is zero (e.g. insve.d)
541 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
543 // Node immediate fits as 16-bit sign extended on target immediate.
545 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
547 // Node immediate fits as 16-bit sign extended on target immediate.
549 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
551 // Node immediate fits as 15-bit sign extended on target immediate.
553 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
555 // Node immediate fits as 16-bit zero extended on target immediate.
556 // The LO16 param means that only the lower 16 bits of the node
557 // immediate are caught.
559 def immZExt16 : PatLeaf<(imm), [{
560 if (N->getValueType(0) == MVT::i32)
561 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
563 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
566 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
567 def immLow16Zero : PatLeaf<(imm), [{
568 int64_t Val = N->getSExtValue();
569 return isInt<32>(Val) && !(Val & 0xffff);
572 // shamt field must fit in 5 bits.
573 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
575 // True if (N + 1) fits in 16-bit field.
576 def immSExt16Plus1 : PatLeaf<(imm), [{
577 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
580 // Mips Address Mode! SDNode frameindex could possibily be a match
581 // since load and store instructions from stack used it.
583 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
586 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
589 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
592 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
594 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
596 //===----------------------------------------------------------------------===//
597 // Instructions specific format
598 //===----------------------------------------------------------------------===//
600 // Arithmetic and logical instructions with 3 register operands.
601 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
602 InstrItinClass Itin = NoItinerary,
603 SDPatternOperator OpNode = null_frag>:
604 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
605 !strconcat(opstr, "\t$rd, $rs, $rt"),
606 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
607 let isCommutable = isComm;
608 let isReMaterializable = 1;
609 let TwoOperandAliasConstraint = "$rd = $rs";
612 // Arithmetic and logical instructions with 2 register operands.
613 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
614 InstrItinClass Itin = NoItinerary,
615 SDPatternOperator imm_type = null_frag,
616 SDPatternOperator OpNode = null_frag> :
617 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
618 !strconcat(opstr, "\t$rt, $rs, $imm16"),
619 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
621 let isReMaterializable = 1;
622 let TwoOperandAliasConstraint = "$rs = $rt";
625 // Arithmetic Multiply ADD/SUB
626 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
627 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
628 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
629 let Defs = [HI0, LO0];
630 let Uses = [HI0, LO0];
631 let isCommutable = isComm;
635 class LogicNOR<string opstr, RegisterOperand RO>:
636 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
637 !strconcat(opstr, "\t$rd, $rs, $rt"),
638 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
639 let isCommutable = 1;
643 class shift_rotate_imm<string opstr, Operand ImmOpnd,
644 RegisterOperand RO, InstrItinClass itin,
645 SDPatternOperator OpNode = null_frag,
646 SDPatternOperator PF = null_frag> :
647 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
648 !strconcat(opstr, "\t$rd, $rt, $shamt"),
649 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
650 let TwoOperandAliasConstraint = "$rt = $rd";
653 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
654 SDPatternOperator OpNode = null_frag>:
655 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
656 !strconcat(opstr, "\t$rd, $rt, $rs"),
657 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
660 // Load Upper Imediate
661 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
662 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
663 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
664 let hasSideEffects = 0;
665 let isReMaterializable = 1;
669 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
670 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
671 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
672 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
673 let DecoderMethod = "DecodeMem";
674 let canFoldAsLoad = 1;
678 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
679 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
680 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
681 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
682 let DecoderMethod = "DecodeMem";
686 // Load/Store Left/Right
687 let canFoldAsLoad = 1 in
688 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
689 InstrItinClass Itin> :
690 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
691 !strconcat(opstr, "\t$rt, $addr"),
692 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
693 let DecoderMethod = "DecodeMem";
694 string Constraints = "$src = $rt";
697 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
698 InstrItinClass Itin> :
699 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
700 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
701 let DecoderMethod = "DecodeMem";
705 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
706 SDPatternOperator OpNode= null_frag> :
707 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
708 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
709 let DecoderMethod = "DecodeFMem2";
713 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
714 SDPatternOperator OpNode= null_frag> :
715 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
716 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
717 let DecoderMethod = "DecodeFMem2";
722 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
723 SDPatternOperator OpNode= null_frag> :
724 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
725 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
726 let DecoderMethod = "DecodeFMem3";
730 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
731 SDPatternOperator OpNode= null_frag> :
732 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
733 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
734 let DecoderMethod = "DecodeFMem3";
738 // Conditional Branch
739 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
740 RegisterOperand RO, bit DelaySlot = 1> :
741 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
742 !strconcat(opstr, "\t$rs, $rt, $offset"),
743 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
746 let isTerminator = 1;
747 let hasDelaySlot = DelaySlot;
751 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
752 RegisterOperand RO, bit DelaySlot = 1> :
753 InstSE<(outs), (ins RO:$rs, opnd:$offset),
754 !strconcat(opstr, "\t$rs, $offset"),
755 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
758 let isTerminator = 1;
759 let hasDelaySlot = DelaySlot;
764 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
765 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
766 !strconcat(opstr, "\t$rd, $rs, $rt"),
767 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
768 II_SLT_SLTU, FrmR, opstr>;
770 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
772 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
773 !strconcat(opstr, "\t$rt, $rs, $imm16"),
774 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
775 II_SLTI_SLTIU, FrmI, opstr>;
778 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
779 SDPatternOperator targetoperator, string bopstr> :
780 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
781 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
784 let hasDelaySlot = 1;
785 let DecoderMethod = "DecodeJumpTarget";
789 // Unconditional branch
790 class UncondBranch<Instruction BEQInst> :
791 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
792 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
794 let isTerminator = 1;
796 let hasDelaySlot = 1;
797 let AdditionalPredicates = [RelocPIC];
801 // Base class for indirect branch and return instruction classes.
802 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
803 class JumpFR<string opstr, RegisterOperand RO,
804 SDPatternOperator operator = null_frag>:
805 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
809 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
811 let isIndirectBranch = 1;
814 // Jump and Link (Call)
815 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
816 class JumpLink<string opstr, DAGOperand opnd> :
817 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
818 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
819 let DecoderMethod = "DecodeJumpTarget";
822 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
823 Register RetReg, RegisterOperand ResRO = RO>:
824 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
825 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
827 class JumpLinkReg<string opstr, RegisterOperand RO>:
828 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
831 class BGEZAL_FT<string opstr, DAGOperand opnd,
832 RegisterOperand RO, bit DelaySlot = 1> :
833 InstSE<(outs), (ins RO:$rs, opnd:$offset),
834 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
835 let hasDelaySlot = DelaySlot;
840 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
841 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
842 class TailCall<Instruction JumpInst> :
843 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
844 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
846 class TailCallReg<RegisterOperand RO, Instruction JRInst,
847 RegisterOperand ResRO = RO> :
848 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
849 PseudoInstExpansion<(JRInst ResRO:$rs)>;
852 class BAL_BR_Pseudo<Instruction RealInst> :
853 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
854 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
856 let isTerminator = 1;
858 let hasDelaySlot = 1;
863 class SYS_FT<string opstr> :
864 InstSE<(outs), (ins uimm20:$code_),
865 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
867 class BRK_FT<string opstr> :
868 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
869 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
873 class ER_FT<string opstr> :
874 InstSE<(outs), (ins),
875 opstr, [], NoItinerary, FrmOther, opstr>;
878 class DEI_FT<string opstr, RegisterOperand RO> :
879 InstSE<(outs RO:$rt), (ins),
880 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
883 class WAIT_FT<string opstr> :
884 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
887 let hasSideEffects = 1 in
888 class SYNC_FT<string opstr> :
889 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
890 NoItinerary, FrmOther, opstr>;
892 class SYNCI_FT<string opstr> :
893 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
894 NoItinerary, FrmOther, opstr> {
895 let hasSideEffects = 1;
896 let DecoderMethod = "DecodeSyncI";
899 let hasSideEffects = 1 in
900 class TEQ_FT<string opstr, RegisterOperand RO> :
901 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
902 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
905 class TEQI_FT<string opstr, RegisterOperand RO> :
906 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
907 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
909 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
910 list<Register> DefRegs> :
911 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
913 let isCommutable = 1;
915 let hasSideEffects = 0;
918 // Pseudo multiply/divide instruction with explicit accumulator register
920 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
921 SDPatternOperator OpNode, InstrItinClass Itin,
922 bit IsComm = 1, bit HasSideEffects = 0,
923 bit UsesCustomInserter = 0> :
924 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
925 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
926 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
927 let isCommutable = IsComm;
928 let hasSideEffects = HasSideEffects;
929 let usesCustomInserter = UsesCustomInserter;
932 // Pseudo multiply add/sub instruction with explicit accumulator register
934 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
936 : PseudoSE<(outs ACC64:$ac),
937 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
939 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
941 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
942 string Constraints = "$acin = $ac";
945 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
946 list<Register> DefRegs> :
947 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
948 [], itin, FrmR, opstr> {
953 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
954 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
955 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
957 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
958 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
961 let hasSideEffects = 0;
964 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
965 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
966 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
969 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
970 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
973 let hasSideEffects = 0;
976 class EffectiveAddress<string opstr, RegisterOperand RO> :
977 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
978 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
979 !strconcat(opstr, "_lea")> {
980 let isCodeGenOnly = 1;
981 let DecoderMethod = "DecodeMem";
984 // Count Leading Ones/Zeros in Word
985 class CountLeading0<string opstr, RegisterOperand RO>:
986 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
987 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
989 class CountLeading1<string opstr, RegisterOperand RO>:
990 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
991 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
993 // Sign Extend in Register.
994 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
995 InstrItinClass itin> :
996 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
997 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
1000 class SubwordSwap<string opstr, RegisterOperand RO>:
1001 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
1002 NoItinerary, FrmR, opstr> {
1003 let hasSideEffects = 0;
1007 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
1008 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
1009 II_RDHWR, FrmR, "rdhwr">;
1012 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1013 SDPatternOperator Op = null_frag>:
1014 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1015 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1016 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1017 FrmR, opstr>, ISA_MIPS32R2;
1019 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1020 SDPatternOperator Op = null_frag>:
1021 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1022 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1023 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1024 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1025 let Constraints = "$src = $rt";
1028 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1029 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1030 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1031 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1033 // Atomic Compare & Swap.
1034 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1035 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1036 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1038 class LLBase<string opstr, RegisterOperand RO> :
1039 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1040 [], NoItinerary, FrmI> {
1041 let DecoderMethod = "DecodeMem";
1045 class SCBase<string opstr, RegisterOperand RO> :
1046 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1047 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1048 let DecoderMethod = "DecodeMem";
1050 let Constraints = "$rt = $dst";
1053 class MFC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1054 InstSE<(outs RO:$rt), (ins RD:$rd, uimm16:$sel),
1055 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1057 class MTC3OP<string asmstr, RegisterOperand RO, RegisterOperand RD> :
1058 InstSE<(outs RO:$rd), (ins RD:$rt, uimm16:$sel),
1059 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1061 class TrapBase<Instruction RealInst>
1062 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1063 PseudoInstExpansion<(RealInst 0, 0)> {
1065 let isTerminator = 1;
1066 let isCodeGenOnly = 1;
1069 //===----------------------------------------------------------------------===//
1070 // Pseudo instructions
1071 //===----------------------------------------------------------------------===//
1074 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1075 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1077 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1078 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1079 [(callseq_start timm:$amt)]>;
1080 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1081 [(callseq_end timm:$amt1, timm:$amt2)]>;
1084 let usesCustomInserter = 1 in {
1085 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1086 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1087 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1088 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1089 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1090 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1091 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1092 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1093 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1094 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1095 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1096 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1097 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1098 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1099 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1100 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1101 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1102 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1104 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1105 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1106 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1108 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1109 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1110 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1113 /// Pseudo instructions for loading and storing accumulator registers.
1114 let isPseudo = 1, isCodeGenOnly = 1 in {
1115 def LOAD_ACC64 : Load<"", ACC64>;
1116 def STORE_ACC64 : Store<"", ACC64>;
1119 // We need these two pseudo instructions to avoid offset calculation for long
1120 // branches. See the comment in file MipsLongBranch.cpp for detailed
1123 // Expands to: lui $dst, %hi($tgt - $baltgt)
1124 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1125 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1127 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1128 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1129 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1131 //===----------------------------------------------------------------------===//
1132 // Instruction definition
1133 //===----------------------------------------------------------------------===//
1134 //===----------------------------------------------------------------------===//
1135 // MipsI Instructions
1136 //===----------------------------------------------------------------------===//
1138 /// Arithmetic Instructions (ALU Immediate)
1139 let AdditionalPredicates = [NotInMicroMips] in {
1140 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1141 II_ADDIU, immSExt16, add>,
1142 ADDI_FM<0x9>, IsAsCheapAsAMove;
1144 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1145 ISA_MIPS1_NOT_32R6_64R6;
1146 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1148 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1150 let AdditionalPredicates = [NotInMicroMips] in {
1151 def ANDi : MMRel, StdMMR6Rel,
1152 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1155 def ORi : MMRel, StdMMR6Rel,
1156 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1158 def XORi : MMRel, StdMMR6Rel,
1159 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1161 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1162 let AdditionalPredicates = [NotInMicroMips] in {
1163 /// Arithmetic Instructions (3-Operand, R-Type)
1164 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1166 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1169 let Defs = [HI0, LO0] in
1170 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1171 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1172 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1173 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1174 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1175 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1176 let AdditionalPredicates = [NotInMicroMips] in {
1177 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1179 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1181 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1184 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1186 /// Shift Instructions
1187 let AdditionalPredicates = [NotInMicroMips] in {
1188 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1189 immZExt5>, SRA_FM<0, 0>;
1190 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1191 immZExt5>, SRA_FM<2, 0>;
1193 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1194 immZExt5>, SRA_FM<3, 0>;
1195 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1197 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1199 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1202 // Rotate Instructions
1203 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1205 SRA_FM<2, 1>, ISA_MIPS32R2;
1206 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1207 SRLV_FM<6, 1>, ISA_MIPS32R2;
1209 /// Load and Store Instructions
1211 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1212 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1214 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1216 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1217 let AdditionalPredicates = [NotInMicroMips] in {
1218 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1221 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1222 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1223 let AdditionalPredicates = [NotInMicroMips] in {
1224 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1227 /// load/store left/right
1228 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1229 AdditionalPredicates = [NotInMicroMips] in {
1230 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1231 ISA_MIPS1_NOT_32R6_64R6;
1232 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1233 ISA_MIPS1_NOT_32R6_64R6;
1234 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1235 ISA_MIPS1_NOT_32R6_64R6;
1236 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1237 ISA_MIPS1_NOT_32R6_64R6;
1240 let AdditionalPredicates = [NotInMicroMips] in {
1241 // COP2 Memory Instructions
1242 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1243 ISA_MIPS1_NOT_32R6_64R6;
1244 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1245 ISA_MIPS1_NOT_32R6_64R6;
1246 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1247 ISA_MIPS2_NOT_32R6_64R6;
1248 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1249 ISA_MIPS2_NOT_32R6_64R6;
1251 // COP3 Memory Instructions
1252 let DecoderNamespace = "COP3_" in {
1253 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1254 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1255 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1257 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1262 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1263 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1265 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1266 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1267 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1268 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1269 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1270 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1272 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1273 ISA_MIPS2_NOT_32R6_64R6;
1274 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1275 ISA_MIPS2_NOT_32R6_64R6;
1276 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1277 ISA_MIPS2_NOT_32R6_64R6;
1278 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1279 ISA_MIPS2_NOT_32R6_64R6;
1280 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1281 ISA_MIPS2_NOT_32R6_64R6;
1282 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1283 ISA_MIPS2_NOT_32R6_64R6;
1285 let AdditionalPredicates = [NotInMicroMips] in {
1286 def BREAK : MMRel, StdMMR6Rel, BRK_FT<"break">, BRK_FM<0xd>;
1288 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1289 def TRAP : TrapBase<BREAK>;
1290 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1292 let AdditionalPredicates = [NotInMicroMips] in {
1293 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1295 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1297 let AdditionalPredicates = [NotInMicroMips] in {
1298 def EI : MMRel, StdMMR6Rel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1300 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1302 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1303 AdditionalPredicates = [NotInMicroMips] in {
1304 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1306 /// Load-linked, Store-conditional
1307 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1308 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1311 /// Jump and Branch Instructions
1312 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1313 AdditionalRequires<[RelocStatic]>, IsBranch;
1314 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1315 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1316 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1317 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1318 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1319 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1320 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1321 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1323 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1324 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1325 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1327 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1328 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1329 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1331 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1332 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1333 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1335 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1336 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1337 def B : UncondBranch<BEQ>;
1339 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1340 let AdditionalPredicates = [NotInMicroMips] in {
1341 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1342 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1345 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1346 ISA_MIPS32_NOT_32R6_64R6;
1347 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1348 ISA_MIPS1_NOT_32R6_64R6;
1349 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1350 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1351 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1352 ISA_MIPS1_NOT_32R6_64R6;
1353 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1354 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1355 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1356 def TAILCALL : TailCall<J>;
1357 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1359 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1360 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1361 class PseudoIndirectBranchBase<RegisterOperand RO> :
1362 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1365 let hasDelaySlot = 1;
1367 let isIndirectBranch = 1;
1370 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1372 // Return instructions are matched as a RetRA instruction, then ar expanded
1373 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1374 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1376 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1378 let isTerminator = 1;
1380 let hasDelaySlot = 1;
1382 let isCodeGenOnly = 1;
1384 let hasExtraSrcRegAllocReq = 1;
1387 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1389 // Exception handling related node and instructions.
1390 // The conversion sequence is:
1391 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1392 // MIPSeh_return -> (stack change + indirect branch)
1394 // MIPSeh_return takes the place of regular return instruction
1395 // but takes two arguments (V1, V0) which are used for storing
1396 // the offset and return address respectively.
1397 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1399 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1400 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1402 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1403 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1404 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1405 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1407 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1410 /// Multiply and Divide Instructions.
1411 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1412 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1413 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1414 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1415 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1416 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1417 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1418 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1420 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1421 ISA_MIPS1_NOT_32R6_64R6;
1422 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1423 ISA_MIPS1_NOT_32R6_64R6;
1424 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1425 AdditionalPredicates = [NotInMicroMips] in {
1426 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1427 ISA_MIPS1_NOT_32R6_64R6;
1428 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1429 ISA_MIPS1_NOT_32R6_64R6;
1432 /// Sign Ext In Register Instructions.
1433 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1434 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1435 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1436 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1439 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1440 ISA_MIPS32_NOT_32R6_64R6;
1441 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1442 ISA_MIPS32_NOT_32R6_64R6;
1444 /// Word Swap Bytes Within Halfwords
1445 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1448 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1450 // FrameIndexes are legalized when they are operands from load/store
1451 // instructions. The same not happens for stack address copies, so an
1452 // add op with mem ComplexPattern is used and the stack address copy
1453 // can be matched. It's similar to Sparc LEA_ADDRi
1454 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1457 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1458 ISA_MIPS32_NOT_32R6_64R6;
1459 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1460 ISA_MIPS32_NOT_32R6_64R6;
1461 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1462 ISA_MIPS32_NOT_32R6_64R6;
1463 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1464 ISA_MIPS32_NOT_32R6_64R6;
1466 let AdditionalPredicates = [NotDSP] in {
1467 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1468 ISA_MIPS1_NOT_32R6_64R6;
1469 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1470 ISA_MIPS1_NOT_32R6_64R6;
1471 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1472 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1473 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1474 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1475 ISA_MIPS32_NOT_32R6_64R6;
1476 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1477 ISA_MIPS32_NOT_32R6_64R6;
1478 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1479 ISA_MIPS32_NOT_32R6_64R6;
1480 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1481 ISA_MIPS32_NOT_32R6_64R6;
1484 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1485 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1486 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1487 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1489 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1491 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1492 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1494 /// Move Control Registers From/To CPU Registers
1495 def MFC0 : MFC3OP<"mfc0", GPR32Opnd, COP0Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1496 def MTC0 : MTC3OP<"mtc0", COP0Opnd, GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1497 def MFC2 : MFC3OP<"mfc2", GPR32Opnd, COP2Opnd>, MFC3OP_FM<0x12, 0>;
1498 def MTC2 : MTC3OP<"mtc2", COP2Opnd, GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1500 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1502 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1503 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1504 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1506 // JR_HB and JALR_HB are defined here using the new style naming
1507 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1508 // and because of that it doesn't follow the naming convention of the
1509 // rest of the file. To avoid a mixture of old vs new style, the new
1510 // style was chosen.
1511 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1512 dag OutOperandList = (outs);
1513 dag InOperandList = (ins GPROpnd:$rs);
1514 string AsmString = !strconcat(instr_asm, "\t$rs");
1515 list<dag> Pattern = [];
1518 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1519 dag OutOperandList = (outs GPROpnd:$rd);
1520 dag InOperandList = (ins GPROpnd:$rs);
1521 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1522 list<dag> Pattern = [];
1525 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1526 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1528 let isIndirectBranch=1;
1534 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1535 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1536 let isIndirectBranch=1;
1540 class JR_HB_ENC : JR_HB_FM<8>;
1541 class JALR_HB_ENC : JALR_HB_FM<9>;
1543 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1544 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1546 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1548 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1549 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1550 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1551 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1553 class CacheOp<string instr_asm, Operand MemOpnd> :
1554 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1555 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1557 let DecoderMethod = "DecodeCacheOp";
1560 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1561 INSN_MIPS3_32_NOT_32R6_64R6;
1562 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1563 INSN_MIPS3_32_NOT_32R6_64R6;
1565 //===----------------------------------------------------------------------===//
1566 // Instruction aliases
1567 //===----------------------------------------------------------------------===//
1568 def : MipsInstAlias<"move $dst, $src",
1569 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1571 let AdditionalPredicates = [NotInMicroMips];
1573 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1574 ISA_MIPS1_NOT_32R6_64R6;
1575 def : MipsInstAlias<"addu $rs, $rt, $imm",
1576 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1577 def : MipsInstAlias<"addu $rs, $imm",
1578 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1579 def : MipsInstAlias<"add $rs, $rt, $imm",
1580 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1581 ISA_MIPS1_NOT_32R6_64R6;
1582 def : MipsInstAlias<"add $rs, $imm",
1583 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1584 ISA_MIPS1_NOT_32R6_64R6;
1585 def : MipsInstAlias<"and $rs, $rt, $imm",
1586 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1587 def : MipsInstAlias<"and $rs, $imm",
1588 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1589 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1590 let Predicates = [NotInMicroMips] in {
1591 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1593 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1594 def : MipsInstAlias<"not $rt, $rs",
1595 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1596 def : MipsInstAlias<"neg $rt, $rs",
1597 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1598 def : MipsInstAlias<"negu $rt",
1599 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1600 def : MipsInstAlias<"negu $rt, $rs",
1601 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1602 def : MipsInstAlias<"slt $rs, $rt, $imm",
1603 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1604 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1605 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1606 def : MipsInstAlias<"xor $rs, $rt, $imm",
1607 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1608 def : MipsInstAlias<"xor $rs, $imm",
1609 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1610 def : MipsInstAlias<"or $rs, $rt, $imm",
1611 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1612 def : MipsInstAlias<"or $rs, $imm",
1613 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1614 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1615 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, COP0Opnd:$rd, 0), 0>;
1616 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 COP0Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1617 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, COP2Opnd:$rd, 0), 0>;
1618 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 COP2Opnd:$rd, GPR32Opnd:$rt, 0), 0>;
1619 let AdditionalPredicates = [NotInMicroMips] in {
1620 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1622 def : MipsInstAlias<"bnez $rs,$offset",
1623 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1624 def : MipsInstAlias<"bnezl $rs,$offset",
1625 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1626 def : MipsInstAlias<"beqz $rs,$offset",
1627 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1628 def : MipsInstAlias<"beqzl $rs,$offset",
1629 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1630 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1632 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1633 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1634 let AdditionalPredicates = [NotInMicroMips] in {
1635 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1637 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1639 def : MipsInstAlias<"teq $rs, $rt",
1640 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1641 def : MipsInstAlias<"tge $rs, $rt",
1642 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1643 def : MipsInstAlias<"tgeu $rs, $rt",
1644 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1645 def : MipsInstAlias<"tlt $rs, $rt",
1646 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1647 def : MipsInstAlias<"tltu $rs, $rt",
1648 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1649 def : MipsInstAlias<"tne $rs, $rt",
1650 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1652 def : MipsInstAlias<"sll $rd, $rt, $rs",
1653 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1654 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1655 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1656 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1657 def : MipsInstAlias<"sub $rs, $imm",
1658 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1659 0>, ISA_MIPS1_NOT_32R6_64R6;
1660 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1661 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1662 InvertedImOperand:$imm), 0>;
1663 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1664 InvertedImOperand:$imm), 0>;
1665 def : MipsInstAlias<"sra $rd, $rt, $rs",
1666 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1667 def : MipsInstAlias<"srl $rd, $rt, $rs",
1668 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1669 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1670 def : MipsInstAlias<"sync",
1671 (SYNC 0), 1>, ISA_MIPS2;
1672 //===----------------------------------------------------------------------===//
1673 // Assembler Pseudo Instructions
1674 //===----------------------------------------------------------------------===//
1676 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1677 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1678 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1679 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1681 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1682 RegisterOperand RO> :
1683 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1684 !strconcat(instr_asm, "\t$rt, $addr")> ;
1685 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1687 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1688 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1689 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1690 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1692 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1694 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1697 let hasDelaySlot = 1 in {
1698 def BneImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1699 (ins imm64:$imm64, brtarget:$offset),
1700 "bne\t$rt, $imm64, $offset">;
1701 def BeqImm : MipsAsmPseudoInst<(outs GPR32Opnd:$rt),
1702 (ins imm64:$imm64, brtarget:$offset),
1703 "beq\t$rt, $imm64, $offset">;
1705 class CondBranchPseudo<string instr_asm> :
1706 MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt,
1708 !strconcat(instr_asm, "\t$rs, $rt, $offset")>;
1711 def BLT : CondBranchPseudo<"blt">;
1712 def BLE : CondBranchPseudo<"ble">;
1713 def BGE : CondBranchPseudo<"bge">;
1714 def BGT : CondBranchPseudo<"bgt">;
1715 def BLTU : CondBranchPseudo<"bltu">;
1716 def BLEU : CondBranchPseudo<"bleu">;
1717 def BGEU : CondBranchPseudo<"bgeu">;
1718 def BGTU : CondBranchPseudo<"bgtu">;
1720 def Ulhu : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1721 "ulhu\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
1723 def Ulw : MipsAsmPseudoInst<(outs GPR32Opnd:$rt), (ins mem:$addr),
1724 "ulw\t$rt, $addr">, ISA_MIPS1_NOT_32R6_64R6;
1726 //===----------------------------------------------------------------------===//
1727 // Arbitrary patterns that map to one or more instructions
1728 //===----------------------------------------------------------------------===//
1730 // Load/store pattern templates.
1731 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1732 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1734 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1735 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1738 let AdditionalPredicates = [NotInMicroMips] in {
1739 def : MipsPat<(i32 immSExt16:$in),
1740 (ADDiu ZERO, imm:$in)>;
1741 def : MipsPat<(i32 immZExt16:$in),
1742 (ORi ZERO, imm:$in)>;
1744 def : MipsPat<(i32 immLow16Zero:$in),
1745 (LUi (HI16 imm:$in))>;
1747 // Arbitrary immediates
1748 def : MipsPat<(i32 imm:$imm),
1749 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1751 // Carry MipsPatterns
1752 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1753 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1754 let AdditionalPredicates = [NotDSP] in {
1755 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1756 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1757 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1758 (ADDiu GPR32:$src, imm:$imm)>;
1761 // Support multiplication for pre-Mips32 targets that don't have
1762 // the MUL instruction.
1763 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1764 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1765 ISA_MIPS1_NOT_32R6_64R6;
1768 def : MipsPat<(MipsSync (i32 immz)),
1769 (SYNC 0)>, ISA_MIPS2;
1772 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1773 (JAL tglobaladdr:$dst)>;
1774 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1775 (JAL texternalsym:$dst)>;
1776 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1777 // (JALR GPR32:$dst)>;
1780 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1781 (TAILCALL tglobaladdr:$dst)>;
1782 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1783 (TAILCALL texternalsym:$dst)>;
1785 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1786 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1787 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1788 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1789 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1790 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1792 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1793 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1794 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1795 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1796 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1797 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1799 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1800 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1801 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1802 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1803 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1804 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1805 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1806 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1807 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1808 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1811 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1812 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1813 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1814 (ADDiu GPR32:$gp, tconstpool:$in)>;
1817 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1818 MipsPat<(MipsWrapper RC:$gp, node:$in),
1819 (ADDiuOp RC:$gp, node:$in)>;
1821 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1822 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1823 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1824 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1825 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1826 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1828 let AdditionalPredicates = [NotInMicroMips] in {
1829 // Mips does not have "not", so we expand our way
1830 def : MipsPat<(not GPR32:$in),
1831 (NOR GPR32Opnd:$in, ZERO)>;
1835 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1836 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1837 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1840 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1843 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1844 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1845 Instruction SLTiuOp, Register ZEROReg> {
1846 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1847 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1848 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1849 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1851 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1852 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1853 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1854 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1855 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1856 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1857 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1858 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1859 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1860 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1861 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1862 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1864 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1865 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1866 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1867 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1869 def : MipsPat<(brcond RC:$cond, bb:$dst),
1870 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1873 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1875 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1876 (BLEZ i32:$lhs, bb:$dst)>;
1877 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1878 (BGEZ i32:$lhs, bb:$dst)>;
1881 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1882 Instruction SLTuOp, Register ZEROReg> {
1883 def : MipsPat<(seteq RC:$lhs, 0),
1884 (SLTiuOp RC:$lhs, 1)>;
1885 def : MipsPat<(setne RC:$lhs, 0),
1886 (SLTuOp ZEROReg, RC:$lhs)>;
1887 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1888 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1889 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1890 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1893 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1894 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1895 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1896 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1897 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1900 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1901 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1902 (SLTOp RC:$rhs, RC:$lhs)>;
1903 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1904 (SLTuOp RC:$rhs, RC:$lhs)>;
1907 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1908 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1909 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1910 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1911 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1914 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1915 Instruction SLTiuOp> {
1916 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1917 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1918 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1919 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1922 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1923 defm : SetlePats<GPR32, SLT, SLTu>;
1924 defm : SetgtPats<GPR32, SLT, SLTu>;
1925 defm : SetgePats<GPR32, SLT, SLTu>;
1926 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1929 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1931 // Load halfword/word patterns.
1932 let AddedComplexity = 40 in {
1933 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1934 def : LoadRegImmPat<LH, i32, sextloadi16>;
1935 let AdditionalPredicates = [NotInMicroMips] in {
1936 def : LoadRegImmPat<LW, i32, load>;
1940 //===----------------------------------------------------------------------===//
1941 // Floating Point Support
1942 //===----------------------------------------------------------------------===//
1944 include "MipsInstrFPU.td"
1945 include "Mips64InstrInfo.td"
1946 include "MipsCondMov.td"
1948 include "Mips32r6InstrInfo.td"
1949 include "Mips64r6InstrInfo.td"
1954 include "Mips16InstrFormats.td"
1955 include "Mips16InstrInfo.td"
1958 include "MipsDSPInstrFormats.td"
1959 include "MipsDSPInstrInfo.td"
1962 include "MipsMSAInstrFormats.td"
1963 include "MipsMSAInstrInfo.td"
1966 include "MicroMipsInstrFormats.td"
1967 include "MicroMipsInstrInfo.td"
1968 include "MicroMipsInstrFPU.td"
1971 include "MicroMips32r6InstrFormats.td"
1972 include "MicroMips32r6InstrInfo.td"