1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
164 AssemblerPredicate<"FeatureGP64Bit">;
165 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
166 AssemblerPredicate<"!FeatureGP64Bit">;
167 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
168 AssemblerPredicate<"FeatureMips64">;
169 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def IsGP64 : Predicate<"Subtarget.isGP64()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
174 AssemblerPredicate<"FeatureMips64r2">;
175 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
176 AssemblerPredicate<"FeatureN64">;
177 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
178 AssemblerPredicate<"FeatureMips16">;
179 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
180 AssemblerPredicate<"FeatureCnMips">;
181 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
182 AssemblerPredicate<"FeatureMips32">;
183 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
184 AssemblerPredicate<"FeatureMips32">;
185 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
186 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
187 AssemblerPredicate<"!FeatureMips16">;
188 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
189 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
190 AssemblerPredicate<"FeatureMicroMips">;
191 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
192 AssemblerPredicate<"!FeatureMicroMips">;
193 def IsLE : Predicate<"Subtarget.isLittle()">;
194 def IsBE : Predicate<"!Subtarget.isLittle()">;
195 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
197 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
198 let Predicates = [HasStdEnc];
202 bit isCommutable = 1;
219 bit isTerminator = 1;
222 bit hasExtraSrcRegAllocReq = 1;
223 bit isCodeGenOnly = 1;
226 class IsAsCheapAsAMove {
227 bit isAsCheapAsAMove = 1;
230 class NeverHasSideEffects {
231 bit neverHasSideEffects = 1;
234 //===----------------------------------------------------------------------===//
235 // Instruction format superclass
236 //===----------------------------------------------------------------------===//
238 include "MipsInstrFormats.td"
240 //===----------------------------------------------------------------------===//
241 // Mips Operand, Complex Patterns and Transformations Definitions.
242 //===----------------------------------------------------------------------===//
244 def MipsJumpTargetAsmOperand : AsmOperandClass {
245 let Name = "JumpTarget";
246 let ParserMethod = "ParseJumpTarget";
247 let PredicateMethod = "isImm";
248 let RenderMethod = "addImmOperands";
251 // Instruction operand types
252 def jmptarget : Operand<OtherVT> {
253 let EncoderMethod = "getJumpTargetOpValue";
254 let ParserMatchClass = MipsJumpTargetAsmOperand;
256 def brtarget : Operand<OtherVT> {
257 let EncoderMethod = "getBranchTargetOpValue";
258 let OperandType = "OPERAND_PCREL";
259 let DecoderMethod = "DecodeBranchTarget";
260 let ParserMatchClass = MipsJumpTargetAsmOperand;
262 def calltarget : Operand<iPTR> {
263 let EncoderMethod = "getJumpTargetOpValue";
264 let ParserMatchClass = MipsJumpTargetAsmOperand;
267 def simm10 : Operand<i32>;
269 def simm16 : Operand<i32> {
270 let DecoderMethod= "DecodeSimm16";
273 def simm20 : Operand<i32> {
276 def uimm20 : Operand<i32> {
279 def uimm10 : Operand<i32> {
282 def simm16_64 : Operand<i64> {
283 let DecoderMethod = "DecodeSimm16";
287 def uimmz : Operand<i32> {
288 let PrintMethod = "printUnsignedImm";
292 def uimm5 : Operand<i32> {
293 let PrintMethod = "printUnsignedImm";
296 def uimm6 : Operand<i32> {
297 let PrintMethod = "printUnsignedImm";
300 def uimm16 : Operand<i32> {
301 let PrintMethod = "printUnsignedImm";
304 def pcrel16 : Operand<i32> {
307 def MipsMemAsmOperand : AsmOperandClass {
309 let ParserMethod = "parseMemOperand";
312 def MipsInvertedImmoperand : AsmOperandClass {
314 let RenderMethod = "addImmOperands";
315 let ParserMethod = "parseInvNum";
318 def InvertedImOperand : Operand<i32> {
319 let ParserMatchClass = MipsInvertedImmoperand;
322 def InvertedImOperand64 : Operand<i64> {
323 let ParserMatchClass = MipsInvertedImmoperand;
326 class mem_generic : Operand<iPTR> {
327 let PrintMethod = "printMemOperand";
328 let MIOperandInfo = (ops ptr_rc, simm16);
329 let EncoderMethod = "getMemEncoding";
330 let ParserMatchClass = MipsMemAsmOperand;
331 let OperandType = "OPERAND_MEMORY";
335 def mem : mem_generic;
337 // MSA specific address operand
338 def mem_msa : mem_generic {
339 let MIOperandInfo = (ops ptr_rc, simm10);
340 let EncoderMethod = "getMSAMemEncoding";
343 def mem_ea : Operand<iPTR> {
344 let PrintMethod = "printMemOperandEA";
345 let MIOperandInfo = (ops ptr_rc, simm16);
346 let EncoderMethod = "getMemEncoding";
347 let OperandType = "OPERAND_MEMORY";
350 def PtrRC : Operand<iPTR> {
351 let MIOperandInfo = (ops ptr_rc);
352 let DecoderMethod = "DecodePtrRegisterClass";
353 let ParserMatchClass = GPR32AsmOperand;
356 // size operand of ext instruction
357 def size_ext : Operand<i32> {
358 let EncoderMethod = "getSizeExtEncoding";
359 let DecoderMethod = "DecodeExtSize";
362 // size operand of ins instruction
363 def size_ins : Operand<i32> {
364 let EncoderMethod = "getSizeInsEncoding";
365 let DecoderMethod = "DecodeInsSize";
368 // Transformation Function - get the lower 16 bits.
369 def LO16 : SDNodeXForm<imm, [{
370 return getImm(N, N->getZExtValue() & 0xFFFF);
373 // Transformation Function - get the higher 16 bits.
374 def HI16 : SDNodeXForm<imm, [{
375 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
379 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
381 // Node immediate is zero (e.g. insve.d)
382 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
384 // Node immediate fits as 16-bit sign extended on target immediate.
386 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
388 // Node immediate fits as 16-bit sign extended on target immediate.
390 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
392 // Node immediate fits as 15-bit sign extended on target immediate.
394 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
396 // Node immediate fits as 16-bit zero extended on target immediate.
397 // The LO16 param means that only the lower 16 bits of the node
398 // immediate are caught.
400 def immZExt16 : PatLeaf<(imm), [{
401 if (N->getValueType(0) == MVT::i32)
402 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
404 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
407 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
408 def immLow16Zero : PatLeaf<(imm), [{
409 int64_t Val = N->getSExtValue();
410 return isInt<32>(Val) && !(Val & 0xffff);
413 // shamt field must fit in 5 bits.
414 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
416 // True if (N + 1) fits in 16-bit field.
417 def immSExt16Plus1 : PatLeaf<(imm), [{
418 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
421 // Mips Address Mode! SDNode frameindex could possibily be a match
422 // since load and store instructions from stack used it.
424 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
427 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
430 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
433 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
435 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
437 //===----------------------------------------------------------------------===//
438 // Instructions specific format
439 //===----------------------------------------------------------------------===//
441 // Arithmetic and logical instructions with 3 register operands.
442 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
443 InstrItinClass Itin = NoItinerary,
444 SDPatternOperator OpNode = null_frag>:
445 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
446 !strconcat(opstr, "\t$rd, $rs, $rt"),
447 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
448 let isCommutable = isComm;
449 let isReMaterializable = 1;
450 let TwoOperandAliasConstraint = "$rd = $rs";
453 // Arithmetic and logical instructions with 2 register operands.
454 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
455 InstrItinClass Itin = NoItinerary,
456 SDPatternOperator imm_type = null_frag,
457 SDPatternOperator OpNode = null_frag> :
458 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
459 !strconcat(opstr, "\t$rt, $rs, $imm16"),
460 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
462 let isReMaterializable = 1;
463 let TwoOperandAliasConstraint = "$rs = $rt";
466 // Arithmetic Multiply ADD/SUB
467 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
468 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
469 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
470 let Defs = [HI0, LO0];
471 let Uses = [HI0, LO0];
472 let isCommutable = isComm;
476 class LogicNOR<string opstr, RegisterOperand RO>:
477 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
478 !strconcat(opstr, "\t$rd, $rs, $rt"),
479 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
480 let isCommutable = 1;
484 class shift_rotate_imm<string opstr, Operand ImmOpnd,
485 RegisterOperand RO, InstrItinClass itin,
486 SDPatternOperator OpNode = null_frag,
487 SDPatternOperator PF = null_frag> :
488 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
489 !strconcat(opstr, "\t$rd, $rt, $shamt"),
490 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
491 let TwoOperandAliasConstraint = "$rt = $rd";
494 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
495 SDPatternOperator OpNode = null_frag>:
496 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
497 !strconcat(opstr, "\t$rd, $rt, $rs"),
498 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
501 // Load Upper Imediate
502 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
503 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
504 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
505 let neverHasSideEffects = 1;
506 let isReMaterializable = 1;
510 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
511 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
512 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
513 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
514 let DecoderMethod = "DecodeMem";
515 let canFoldAsLoad = 1;
519 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
520 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
521 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
522 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
523 let DecoderMethod = "DecodeMem";
527 // Load/Store Left/Right
528 let canFoldAsLoad = 1 in
529 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
530 InstrItinClass Itin> :
531 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
532 !strconcat(opstr, "\t$rt, $addr"),
533 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
534 let DecoderMethod = "DecodeMem";
535 string Constraints = "$src = $rt";
538 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
539 InstrItinClass Itin> :
540 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
541 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
542 let DecoderMethod = "DecodeMem";
545 // Conditional Branch
546 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
547 RegisterOperand RO> :
548 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
549 !strconcat(opstr, "\t$rs, $rt, $offset"),
550 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
553 let isTerminator = 1;
554 let hasDelaySlot = 1;
558 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
559 RegisterOperand RO> :
560 InstSE<(outs), (ins RO:$rs, opnd:$offset),
561 !strconcat(opstr, "\t$rs, $offset"),
562 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
565 let isTerminator = 1;
566 let hasDelaySlot = 1;
571 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
572 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
573 !strconcat(opstr, "\t$rd, $rs, $rt"),
574 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
575 II_SLT_SLTU, FrmR, opstr>;
577 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
579 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
580 !strconcat(opstr, "\t$rt, $rs, $imm16"),
581 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
582 II_SLTI_SLTIU, FrmI, opstr>;
585 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
586 SDPatternOperator targetoperator, string bopstr> :
587 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
588 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
591 let hasDelaySlot = 1;
592 let DecoderMethod = "DecodeJumpTarget";
596 // Unconditional branch
597 class UncondBranch<Instruction BEQInst> :
598 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
599 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
601 let isTerminator = 1;
603 let hasDelaySlot = 1;
604 let Predicates = [RelocPIC, HasStdEnc];
608 // Base class for indirect branch and return instruction classes.
609 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
610 class JumpFR<string opstr, RegisterOperand RO,
611 SDPatternOperator operator = null_frag>:
612 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
616 class IndirectBranch<string opstr, RegisterOperand RO> :
617 JumpFR<opstr, RO, brind> {
619 let isIndirectBranch = 1;
622 // Return instruction
623 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
625 let isCodeGenOnly = 1;
627 let hasExtraSrcRegAllocReq = 1;
630 // Jump and Link (Call)
631 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
632 class JumpLink<string opstr, DAGOperand opnd> :
633 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
634 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
635 let DecoderMethod = "DecodeJumpTarget";
638 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
639 Register RetReg, RegisterOperand ResRO = RO>:
640 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
641 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
643 class JumpLinkReg<string opstr, RegisterOperand RO>:
644 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
647 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
648 InstSE<(outs), (ins RO:$rs, opnd:$offset),
649 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
653 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
654 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
655 class TailCall<Instruction JumpInst> :
656 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
657 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
659 class TailCallReg<RegisterOperand RO, Instruction JRInst,
660 RegisterOperand ResRO = RO> :
661 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
662 PseudoInstExpansion<(JRInst ResRO:$rs)>;
665 class BAL_BR_Pseudo<Instruction RealInst> :
666 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
667 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
669 let isTerminator = 1;
671 let hasDelaySlot = 1;
676 class SYS_FT<string opstr> :
677 InstSE<(outs), (ins uimm20:$code_),
678 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
680 class BRK_FT<string opstr> :
681 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
682 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
686 class ER_FT<string opstr> :
687 InstSE<(outs), (ins),
688 opstr, [], NoItinerary, FrmOther, opstr>;
691 class DEI_FT<string opstr, RegisterOperand RO> :
692 InstSE<(outs RO:$rt), (ins),
693 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
696 class WAIT_FT<string opstr> :
697 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
700 let hasSideEffects = 1 in
701 class SYNC_FT<string opstr> :
702 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
703 NoItinerary, FrmOther, opstr>;
705 let hasSideEffects = 1 in
706 class TEQ_FT<string opstr, RegisterOperand RO> :
707 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
708 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
711 class TEQI_FT<string opstr, RegisterOperand RO> :
712 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
713 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
715 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
716 list<Register> DefRegs> :
717 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
719 let isCommutable = 1;
721 let neverHasSideEffects = 1;
724 // Pseudo multiply/divide instruction with explicit accumulator register
726 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
727 SDPatternOperator OpNode, InstrItinClass Itin,
728 bit IsComm = 1, bit HasSideEffects = 0,
729 bit UsesCustomInserter = 0> :
730 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
731 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
732 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
733 let isCommutable = IsComm;
734 let hasSideEffects = HasSideEffects;
735 let usesCustomInserter = UsesCustomInserter;
738 // Pseudo multiply add/sub instruction with explicit accumulator register
740 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
742 : PseudoSE<(outs ACC64:$ac),
743 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
745 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
747 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
748 string Constraints = "$acin = $ac";
751 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
752 list<Register> DefRegs> :
753 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
754 [], itin, FrmR, opstr> {
759 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
760 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
761 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
763 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
764 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
767 let neverHasSideEffects = 1;
770 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
771 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
772 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
775 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
776 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
779 let neverHasSideEffects = 1;
782 class EffectiveAddress<string opstr, RegisterOperand RO> :
783 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
784 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
785 !strconcat(opstr, "_lea")> {
786 let isCodeGenOnly = 1;
787 let DecoderMethod = "DecodeMem";
790 // Count Leading Ones/Zeros in Word
791 class CountLeading0<string opstr, RegisterOperand RO>:
792 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
793 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
794 Requires<[HasBitCount, HasStdEnc]>;
796 class CountLeading1<string opstr, RegisterOperand RO>:
797 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
798 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
799 Requires<[HasBitCount, HasStdEnc]>;
801 // Sign Extend in Register.
802 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
803 InstrItinClass itin> :
804 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
805 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
806 let Predicates = [HasSEInReg, HasStdEnc];
810 class SubwordSwap<string opstr, RegisterOperand RO>:
811 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
812 NoItinerary, FrmR, opstr> {
813 let Predicates = [HasSwap, HasStdEnc];
814 let neverHasSideEffects = 1;
818 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
819 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
823 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
824 SDPatternOperator Op = null_frag>:
825 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
826 !strconcat(opstr, " $rt, $rs, $pos, $size"),
827 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
829 let Predicates = [HasMips32r2, HasStdEnc];
832 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
833 SDPatternOperator Op = null_frag>:
834 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
835 !strconcat(opstr, " $rt, $rs, $pos, $size"),
836 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
837 NoItinerary, FrmR, opstr> {
838 let Predicates = [HasMips32r2, HasStdEnc];
839 let Constraints = "$src = $rt";
842 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
843 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
844 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
845 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
847 // Atomic Compare & Swap.
848 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
849 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
850 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
852 class LLBase<string opstr, RegisterOperand RO> :
853 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
854 [], NoItinerary, FrmI> {
855 let DecoderMethod = "DecodeMem";
859 class SCBase<string opstr, RegisterOperand RO> :
860 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
861 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
862 let DecoderMethod = "DecodeMem";
864 let Constraints = "$rt = $dst";
867 class MFC3OP<string asmstr, RegisterOperand RO> :
868 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
869 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
871 class TrapBase<Instruction RealInst>
872 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
873 PseudoInstExpansion<(RealInst 0, 0)> {
875 let isTerminator = 1;
876 let isCodeGenOnly = 1;
879 //===----------------------------------------------------------------------===//
880 // Pseudo instructions
881 //===----------------------------------------------------------------------===//
884 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
885 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
887 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
888 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
889 [(callseq_start timm:$amt)]>;
890 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
891 [(callseq_end timm:$amt1, timm:$amt2)]>;
894 let usesCustomInserter = 1 in {
895 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
896 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
897 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
898 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
899 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
900 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
901 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
902 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
903 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
904 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
905 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
906 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
907 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
908 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
909 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
910 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
911 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
912 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
914 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
915 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
916 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
918 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
919 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
920 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
923 /// Pseudo instructions for loading and storing accumulator registers.
924 let isPseudo = 1, isCodeGenOnly = 1 in {
925 def LOAD_ACC64 : Load<"", ACC64>;
926 def STORE_ACC64 : Store<"", ACC64>;
929 // We need these two pseudo instructions to avoid offset calculation for long
930 // branches. See the comment in file MipsLongBranch.cpp for detailed
933 // Expands to: lui $dst, %hi($tgt - $baltgt)
934 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
935 (ins brtarget:$tgt, brtarget:$baltgt), []>;
937 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
938 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
939 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
941 //===----------------------------------------------------------------------===//
942 // Instruction definition
943 //===----------------------------------------------------------------------===//
944 //===----------------------------------------------------------------------===//
945 // MipsI Instructions
946 //===----------------------------------------------------------------------===//
948 /// Arithmetic Instructions (ALU Immediate)
949 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
951 ADDI_FM<0x9>, IsAsCheapAsAMove;
952 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
953 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
955 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
957 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
960 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
963 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
966 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
968 /// Arithmetic Instructions (3-Operand, R-Type)
969 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
971 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
973 let Defs = [HI0, LO0] in
974 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
976 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
977 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
978 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
979 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
980 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
982 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
984 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
986 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
988 /// Shift Instructions
989 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
990 immZExt5>, SRA_FM<0, 0>;
991 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
992 immZExt5>, SRA_FM<2, 0>;
993 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
994 immZExt5>, SRA_FM<3, 0>;
995 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
997 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
999 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1002 // Rotate Instructions
1003 let Predicates = [HasMips32r2, HasStdEnc] in {
1004 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1005 immZExt5>, SRA_FM<2, 1>;
1006 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1010 /// Load and Store Instructions
1012 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1013 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1015 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1017 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1018 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1020 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1021 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1022 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1024 /// load/store left/right
1025 let Predicates = [NotInMicroMips] in {
1026 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1027 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1028 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1029 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1032 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1033 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1034 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1035 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1036 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1037 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1038 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1040 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1041 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1042 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1043 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1044 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1045 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1047 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1048 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1049 def TRAP : TrapBase<BREAK>;
1051 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1052 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1054 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1055 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1057 let Predicates = [NotInMicroMips] in {
1058 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1060 /// Load-linked, Store-conditional
1061 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1062 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1065 /// Jump and Branch Instructions
1066 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1067 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1068 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1069 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1070 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1071 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1073 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1075 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1077 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1079 def B : UncondBranch<BEQ>;
1081 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1082 let Predicates = [NotInMicroMips, HasStdEnc] in {
1083 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1084 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1086 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1087 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1088 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1089 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1090 def TAILCALL : TailCall<J>;
1091 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1093 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1095 // Exception handling related node and instructions.
1096 // The conversion sequence is:
1097 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1098 // MIPSeh_return -> (stack change + indirect branch)
1100 // MIPSeh_return takes the place of regular return instruction
1101 // but takes two arguments (V1, V0) which are used for storing
1102 // the offset and return address respectively.
1103 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1105 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1106 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1108 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1109 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1110 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1111 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1113 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1116 /// Multiply and Divide Instructions.
1117 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1119 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1121 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1123 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1126 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1127 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1128 let Predicates = [NotInMicroMips] in {
1129 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1130 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1133 /// Sign Ext In Register Instructions.
1134 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1135 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1138 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1139 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1141 /// Word Swap Bytes Within Halfwords
1142 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1145 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1147 // FrameIndexes are legalized when they are operands from load/store
1148 // instructions. The same not happens for stack address copies, so an
1149 // add op with mem ComplexPattern is used and the stack address copy
1150 // can be matched. It's similar to Sparc LEA_ADDRi
1151 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1154 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1155 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1156 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1157 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1159 let Predicates = [HasStdEnc, NotDSP] in {
1160 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1161 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1162 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1163 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1164 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1165 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1166 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1167 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1168 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1171 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1173 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1176 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1178 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1179 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1181 /// Move Control Registers From/To CPU Registers
1182 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1183 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1184 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1185 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1187 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1189 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1190 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1191 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>;
1193 //===----------------------------------------------------------------------===//
1194 // Instruction aliases
1195 //===----------------------------------------------------------------------===//
1196 def : InstAlias<"move $dst, $src",
1197 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1198 Requires<[IsGP32, NotInMicroMips]>;
1199 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1200 def : InstAlias<"addu $rs, $rt, $imm",
1201 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1202 def : InstAlias<"add $rs, $rt, $imm",
1203 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1204 def : InstAlias<"and $rs, $rt, $imm",
1205 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1206 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1207 let Predicates = [NotInMicroMips] in {
1208 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1210 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1211 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1212 def : InstAlias<"not $rt, $rs",
1213 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1214 def : InstAlias<"neg $rt, $rs",
1215 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1216 def : InstAlias<"negu $rt",
1217 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1218 def : InstAlias<"negu $rt, $rs",
1219 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1220 def : InstAlias<"slt $rs, $rt, $imm",
1221 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1222 def : InstAlias<"sltu $rt, $rs, $imm",
1223 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1224 def : InstAlias<"xor $rs, $rt, $imm",
1225 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1226 def : InstAlias<"or $rs, $rt, $imm",
1227 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1228 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1229 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1230 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1231 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1232 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1233 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1234 def : InstAlias<"bnez $rs,$offset",
1235 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1236 def : InstAlias<"beqz $rs,$offset",
1237 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1238 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1240 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1241 def : InstAlias<"break", (BREAK 0, 0), 1>;
1242 def : InstAlias<"ei", (EI ZERO), 1>;
1243 def : InstAlias<"di", (DI ZERO), 1>;
1245 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1246 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1247 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1248 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1249 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1250 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1251 def : InstAlias<"sll $rd, $rt, $rs",
1252 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1253 def : InstAlias<"sub, $rd, $rs, $imm",
1254 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1255 def : InstAlias<"sub $rs, $imm",
1256 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1258 def : InstAlias<"subu, $rd, $rs, $imm",
1259 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1260 def : InstAlias<"subu $rs, $imm",
1261 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1263 def : InstAlias<"srl $rd, $rt, $rs",
1264 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1265 //===----------------------------------------------------------------------===//
1266 // Assembler Pseudo Instructions
1267 //===----------------------------------------------------------------------===//
1269 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1270 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1271 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1272 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1274 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1275 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1276 !strconcat(instr_asm, "\t$rt, $addr")> ;
1277 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1279 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1280 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1281 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1282 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1284 //===----------------------------------------------------------------------===//
1285 // Arbitrary patterns that map to one or more instructions
1286 //===----------------------------------------------------------------------===//
1288 // Load/store pattern templates.
1289 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1290 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1292 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1293 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1296 def : MipsPat<(i32 immSExt16:$in),
1297 (ADDiu ZERO, imm:$in)>;
1298 def : MipsPat<(i32 immZExt16:$in),
1299 (ORi ZERO, imm:$in)>;
1300 def : MipsPat<(i32 immLow16Zero:$in),
1301 (LUi (HI16 imm:$in))>;
1303 // Arbitrary immediates
1304 def : MipsPat<(i32 imm:$imm),
1305 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1307 // Carry MipsPatterns
1308 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1309 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1310 let Predicates = [HasStdEnc, NotDSP] in {
1311 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1312 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1313 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1314 (ADDiu GPR32:$src, imm:$imm)>;
1318 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1319 (JAL tglobaladdr:$dst)>;
1320 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1321 (JAL texternalsym:$dst)>;
1322 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1323 // (JALR GPR32:$dst)>;
1326 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1327 (TAILCALL tglobaladdr:$dst)>;
1328 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1329 (TAILCALL texternalsym:$dst)>;
1331 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1332 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1333 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1334 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1335 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1336 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1338 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1339 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1340 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1341 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1342 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1343 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1345 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1346 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1347 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1348 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1349 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1350 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1351 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1352 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1353 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1354 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1357 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1358 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1359 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1360 (ADDiu GPR32:$gp, tconstpool:$in)>;
1363 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1364 MipsPat<(MipsWrapper RC:$gp, node:$in),
1365 (ADDiuOp RC:$gp, node:$in)>;
1367 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1368 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1369 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1370 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1371 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1372 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1374 // Mips does not have "not", so we expand our way
1375 def : MipsPat<(not GPR32:$in),
1376 (NOR GPR32Opnd:$in, ZERO)>;
1379 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1380 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1381 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1384 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1387 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1388 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1389 Instruction SLTiuOp, Register ZEROReg> {
1390 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1391 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1392 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1393 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1395 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1396 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1397 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1398 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1399 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1400 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1401 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1402 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1403 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1404 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1405 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1406 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1408 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1409 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1410 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1411 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1413 def : MipsPat<(brcond RC:$cond, bb:$dst),
1414 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1417 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1419 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1420 (BLEZ i32:$lhs, bb:$dst)>;
1421 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1422 (BGEZ i32:$lhs, bb:$dst)>;
1425 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1426 Instruction SLTuOp, Register ZEROReg> {
1427 def : MipsPat<(seteq RC:$lhs, 0),
1428 (SLTiuOp RC:$lhs, 1)>;
1429 def : MipsPat<(setne RC:$lhs, 0),
1430 (SLTuOp ZEROReg, RC:$lhs)>;
1431 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1432 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1433 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1434 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1437 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1438 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1439 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1440 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1441 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1444 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1445 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1446 (SLTOp RC:$rhs, RC:$lhs)>;
1447 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1448 (SLTuOp RC:$rhs, RC:$lhs)>;
1451 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1452 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1453 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1454 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1455 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1458 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1459 Instruction SLTiuOp> {
1460 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1461 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1462 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1463 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1466 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1467 defm : SetlePats<GPR32, SLT, SLTu>;
1468 defm : SetgtPats<GPR32, SLT, SLTu>;
1469 defm : SetgePats<GPR32, SLT, SLTu>;
1470 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1473 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1475 // Load halfword/word patterns.
1476 let AddedComplexity = 40 in {
1477 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1478 def : LoadRegImmPat<LH, i32, sextloadi16>;
1479 def : LoadRegImmPat<LW, i32, load>;
1482 //===----------------------------------------------------------------------===//
1483 // Floating Point Support
1484 //===----------------------------------------------------------------------===//
1486 include "MipsInstrFPU.td"
1487 include "Mips64InstrInfo.td"
1488 include "MipsCondMov.td"
1493 include "Mips16InstrFormats.td"
1494 include "Mips16InstrInfo.td"
1497 include "MipsDSPInstrFormats.td"
1498 include "MipsDSPInstrInfo.td"
1501 include "MipsMSAInstrFormats.td"
1502 include "MipsMSAInstrInfo.td"
1505 include "MicroMipsInstrFormats.td"
1506 include "MicroMipsInstrInfo.td"
1507 include "MicroMipsInstrFPU.td"