1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def pcrel16 : Operand<i32> {
284 def MipsMemAsmOperand : AsmOperandClass {
286 let ParserMethod = "parseMemOperand";
289 def MipsInvertedImmoperand : AsmOperandClass {
291 let RenderMethod = "addImmOperands";
292 let ParserMethod = "parseInvNum";
295 def PtrRegAsmOperand : AsmOperandClass {
297 let ParserMethod = "parsePtrReg";
301 def InvertedImOperand : Operand<i32> {
302 let ParserMatchClass = MipsInvertedImmoperand;
306 def mem : Operand<iPTR> {
307 let PrintMethod = "printMemOperand";
308 let MIOperandInfo = (ops ptr_rc, simm16);
309 let EncoderMethod = "getMemEncoding";
310 let ParserMatchClass = MipsMemAsmOperand;
311 let OperandType = "OPERAND_MEMORY";
314 def mem_ea : Operand<iPTR> {
315 let PrintMethod = "printMemOperandEA";
316 let MIOperandInfo = (ops ptr_rc, simm16);
317 let EncoderMethod = "getMemEncoding";
318 let OperandType = "OPERAND_MEMORY";
321 def PtrRC : Operand<iPTR> {
322 let MIOperandInfo = (ops ptr_rc);
323 let DecoderMethod = "DecodePtrRegisterClass";
324 let ParserMatchClass = PtrRegAsmOperand;
327 // size operand of ext instruction
328 def size_ext : Operand<i32> {
329 let EncoderMethod = "getSizeExtEncoding";
330 let DecoderMethod = "DecodeExtSize";
333 // size operand of ins instruction
334 def size_ins : Operand<i32> {
335 let EncoderMethod = "getSizeInsEncoding";
336 let DecoderMethod = "DecodeInsSize";
339 // Transformation Function - get the lower 16 bits.
340 def LO16 : SDNodeXForm<imm, [{
341 return getImm(N, N->getZExtValue() & 0xFFFF);
344 // Transformation Function - get the higher 16 bits.
345 def HI16 : SDNodeXForm<imm, [{
346 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
350 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
352 // Node immediate fits as 16-bit sign extended on target immediate.
354 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
356 // Node immediate fits as 16-bit sign extended on target immediate.
358 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
360 // Node immediate fits as 15-bit sign extended on target immediate.
362 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
364 // Node immediate fits as 16-bit zero extended on target immediate.
365 // The LO16 param means that only the lower 16 bits of the node
366 // immediate are caught.
368 def immZExt16 : PatLeaf<(imm), [{
369 if (N->getValueType(0) == MVT::i32)
370 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
372 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
375 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
376 def immLow16Zero : PatLeaf<(imm), [{
377 int64_t Val = N->getSExtValue();
378 return isInt<32>(Val) && !(Val & 0xffff);
381 // shamt field must fit in 5 bits.
382 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
384 // True if (N + 1) fits in 16-bit field.
385 def immSExt16Plus1 : PatLeaf<(imm), [{
386 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
389 // Mips Address Mode! SDNode frameindex could possibily be a match
390 // since load and store instructions from stack used it.
392 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
395 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
398 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
401 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
403 //===----------------------------------------------------------------------===//
404 // Instructions specific format
405 //===----------------------------------------------------------------------===//
407 // Arithmetic and logical instructions with 3 register operands.
408 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
409 InstrItinClass Itin = NoItinerary,
410 SDPatternOperator OpNode = null_frag>:
411 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
412 !strconcat(opstr, "\t$rd, $rs, $rt"),
413 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
414 let isCommutable = isComm;
415 let isReMaterializable = 1;
418 // Arithmetic and logical instructions with 2 register operands.
419 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
420 InstrItinClass Itin = NoItinerary,
421 SDPatternOperator imm_type = null_frag,
422 SDPatternOperator OpNode = null_frag> :
423 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
424 !strconcat(opstr, "\t$rt, $rs, $imm16"),
425 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
427 let isReMaterializable = 1;
428 let TwoOperandAliasConstraint = "$rs = $rt";
431 // Arithmetic Multiply ADD/SUB
432 class MArithR<string opstr, bit isComm = 0> :
433 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
434 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
435 let Defs = [HI0, LO0];
436 let Uses = [HI0, LO0];
437 let isCommutable = isComm;
441 class LogicNOR<string opstr, RegisterOperand RO>:
442 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
443 !strconcat(opstr, "\t$rd, $rs, $rt"),
444 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
445 let isCommutable = 1;
449 class shift_rotate_imm<string opstr, Operand ImmOpnd,
450 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
451 SDPatternOperator PF = null_frag> :
452 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
453 !strconcat(opstr, "\t$rd, $rt, $shamt"),
454 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
456 class shift_rotate_reg<string opstr, RegisterOperand RO,
457 SDPatternOperator OpNode = null_frag>:
458 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
459 !strconcat(opstr, "\t$rd, $rt, $rs"),
460 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
462 // Load Upper Imediate
463 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
464 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
465 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
466 let neverHasSideEffects = 1;
467 let isReMaterializable = 1;
471 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
472 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
473 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
474 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
475 let DecoderMethod = "DecodeMem";
476 let canFoldAsLoad = 1;
480 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
481 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
482 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
483 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
484 let DecoderMethod = "DecodeMem";
488 // Load/Store Left/Right
489 let canFoldAsLoad = 1 in
490 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
491 InstrItinClass Itin> :
492 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
493 !strconcat(opstr, "\t$rt, $addr"),
494 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
495 let DecoderMethod = "DecodeMem";
496 string Constraints = "$src = $rt";
499 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
500 InstrItinClass Itin> :
501 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
502 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
503 let DecoderMethod = "DecodeMem";
506 // Conditional Branch
507 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
508 RegisterOperand RO> :
509 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
510 !strconcat(opstr, "\t$rs, $rt, $offset"),
511 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
514 let isTerminator = 1;
515 let hasDelaySlot = 1;
519 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
520 RegisterOperand RO> :
521 InstSE<(outs), (ins RO:$rs, opnd:$offset),
522 !strconcat(opstr, "\t$rs, $offset"),
523 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
526 let isTerminator = 1;
527 let hasDelaySlot = 1;
532 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
533 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
534 !strconcat(opstr, "\t$rd, $rs, $rt"),
535 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
538 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
540 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
541 !strconcat(opstr, "\t$rt, $rs, $imm16"),
542 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
546 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
547 SDPatternOperator targetoperator, string bopstr> :
548 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
549 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
552 let hasDelaySlot = 1;
553 let DecoderMethod = "DecodeJumpTarget";
557 // Unconditional branch
558 class UncondBranch<Instruction BEQInst> :
559 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
560 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
562 let isTerminator = 1;
564 let hasDelaySlot = 1;
565 let Predicates = [RelocPIC, HasStdEnc];
569 // Base class for indirect branch and return instruction classes.
570 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
571 class JumpFR<string opstr, RegisterOperand RO,
572 SDPatternOperator operator = null_frag>:
573 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
577 class IndirectBranch<string opstr, RegisterOperand RO> :
578 JumpFR<opstr, RO, brind> {
580 let isIndirectBranch = 1;
583 // Return instruction
584 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
586 let isCodeGenOnly = 1;
588 let hasExtraSrcRegAllocReq = 1;
591 // Jump and Link (Call)
592 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
593 class JumpLink<string opstr, DAGOperand opnd> :
594 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
595 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
596 let DecoderMethod = "DecodeJumpTarget";
599 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
600 Register RetReg, RegisterOperand ResRO = RO>:
601 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
602 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
604 class JumpLinkReg<string opstr, RegisterOperand RO>:
605 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
606 [], IIBranch, FrmR, opstr>;
608 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
609 InstSE<(outs), (ins RO:$rs, opnd:$offset),
610 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
614 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
615 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
616 class TailCall<Instruction JumpInst> :
617 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
618 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
620 class TailCallReg<RegisterOperand RO, Instruction JRInst,
621 RegisterOperand ResRO = RO> :
622 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
623 PseudoInstExpansion<(JRInst ResRO:$rs)>;
626 class BAL_BR_Pseudo<Instruction RealInst> :
627 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
628 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
630 let isTerminator = 1;
632 let hasDelaySlot = 1;
637 class SYS_FT<string opstr> :
638 InstSE<(outs), (ins uimm20:$code_),
639 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI>;
641 class BRK_FT<string opstr> :
642 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
643 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary, FrmOther>;
646 class ER_FT<string opstr> :
647 InstSE<(outs), (ins),
648 opstr, [], NoItinerary, FrmOther>;
651 class DEI_FT<string opstr, RegisterOperand RO> :
652 InstSE<(outs RO:$rt), (ins),
653 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther>;
656 class WAIT_FT<string opstr> :
657 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther> {
658 let Inst{31-26} = 0x10;
661 let Inst{5-0} = 0x20;
665 let hasSideEffects = 1 in
667 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
668 NoItinerary, FrmOther>;
670 let hasSideEffects = 1 in
671 class TEQ_FT<string opstr, RegisterOperand RO> :
672 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
673 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
676 class TEQI_FT<string opstr, RegisterOperand RO> :
677 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
678 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
680 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
681 list<Register> DefRegs> :
682 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
684 let isCommutable = 1;
686 let neverHasSideEffects = 1;
689 // Pseudo multiply/divide instruction with explicit accumulator register
691 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
692 SDPatternOperator OpNode, InstrItinClass Itin,
693 bit IsComm = 1, bit HasSideEffects = 0,
694 bit UsesCustomInserter = 0> :
695 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
696 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
697 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
698 let isCommutable = IsComm;
699 let hasSideEffects = HasSideEffects;
700 let usesCustomInserter = UsesCustomInserter;
703 // Pseudo multiply add/sub instruction with explicit accumulator register
705 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
706 : PseudoSE<(outs ACC64:$ac),
707 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
709 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
711 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
712 string Constraints = "$acin = $ac";
715 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
716 list<Register> DefRegs> :
717 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
718 [], itin, FrmR, opstr> {
723 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
724 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
725 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
727 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
728 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
731 let neverHasSideEffects = 1;
734 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
735 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
736 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
738 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
739 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
742 let neverHasSideEffects = 1;
745 class EffectiveAddress<string opstr, RegisterOperand RO> :
746 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
747 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
748 let isCodeGenOnly = 1;
749 let DecoderMethod = "DecodeMem";
752 // Count Leading Ones/Zeros in Word
753 class CountLeading0<string opstr, RegisterOperand RO>:
754 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
755 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
756 Requires<[HasBitCount, HasStdEnc]>;
758 class CountLeading1<string opstr, RegisterOperand RO>:
759 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
760 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
761 Requires<[HasBitCount, HasStdEnc]>;
764 // Sign Extend in Register.
765 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
766 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
767 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
768 let Predicates = [HasSEInReg, HasStdEnc];
772 class SubwordSwap<string opstr, RegisterOperand RO>:
773 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
774 NoItinerary, FrmR, opstr> {
775 let Predicates = [HasSwap, HasStdEnc];
776 let neverHasSideEffects = 1;
780 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
781 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
785 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
786 SDPatternOperator Op = null_frag>:
787 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
788 !strconcat(opstr, " $rt, $rs, $pos, $size"),
789 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
791 let Predicates = [HasMips32r2, HasStdEnc];
794 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
795 SDPatternOperator Op = null_frag>:
796 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
797 !strconcat(opstr, " $rt, $rs, $pos, $size"),
798 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
799 NoItinerary, FrmR, opstr> {
800 let Predicates = [HasMips32r2, HasStdEnc];
801 let Constraints = "$src = $rt";
804 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
805 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
806 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
807 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
809 // Atomic Compare & Swap.
810 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
811 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
812 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
814 class LLBase<string opstr, RegisterOperand RO> :
815 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
816 [], NoItinerary, FrmI> {
817 let DecoderMethod = "DecodeMem";
821 class SCBase<string opstr, RegisterOperand RO> :
822 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
823 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
824 let DecoderMethod = "DecodeMem";
826 let Constraints = "$rt = $dst";
829 class MFC3OP<string asmstr, RegisterOperand RO> :
830 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
831 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
833 class TrapBase<Instruction RealInst>
834 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
835 PseudoInstExpansion<(RealInst 0, 0)> {
837 let isTerminator = 1;
838 let isCodeGenOnly = 1;
841 //===----------------------------------------------------------------------===//
842 // Pseudo instructions
843 //===----------------------------------------------------------------------===//
846 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
847 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
849 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
850 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
851 [(callseq_start timm:$amt)]>;
852 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
853 [(callseq_end timm:$amt1, timm:$amt2)]>;
856 let usesCustomInserter = 1 in {
857 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
858 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
859 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
860 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
861 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
862 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
863 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
864 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
865 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
866 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
867 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
868 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
869 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
870 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
871 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
872 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
873 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
874 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
876 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
877 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
878 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
880 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
881 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
882 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
885 /// Pseudo instructions for loading and storing accumulator registers.
886 let isPseudo = 1, isCodeGenOnly = 1 in {
887 def LOAD_ACC64 : Load<"", ACC64>;
888 def STORE_ACC64 : Store<"", ACC64>;
891 //===----------------------------------------------------------------------===//
892 // Instruction definition
893 //===----------------------------------------------------------------------===//
894 //===----------------------------------------------------------------------===//
895 // MipsI Instructions
896 //===----------------------------------------------------------------------===//
898 /// Arithmetic Instructions (ALU Immediate)
899 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
901 ADDI_FM<0x9>, IsAsCheapAsAMove;
902 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
903 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
905 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
907 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
910 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
913 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
916 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
918 /// Arithmetic Instructions (3-Operand, R-Type)
919 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
921 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
923 let Defs = [HI0, LO0] in
924 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
926 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
927 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
928 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
929 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
930 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
932 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
934 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
936 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
938 /// Shift Instructions
939 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
941 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
943 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
945 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
946 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
947 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
949 // Rotate Instructions
950 let Predicates = [HasMips32r2, HasStdEnc] in {
951 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
954 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
958 /// Load and Store Instructions
960 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
961 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
963 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
965 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
966 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
968 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
969 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
970 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
972 /// load/store left/right
973 let Predicates = [NotInMicroMips] in {
974 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
975 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
976 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
977 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
980 def SYNC : SYNC_FT, SYNC_FM;
981 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
982 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
983 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
984 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
985 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
986 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
988 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
989 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
990 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
991 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
992 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
993 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
995 def BREAK : BRK_FT<"break">, BRK_FM<0xd>;
996 def SYSCALL : SYS_FT<"syscall">, SYS_FM<0xc>;
997 def TRAP : TrapBase<BREAK>;
999 def ERET : ER_FT<"eret">, ER_FM<0x18>;
1000 def DERET : ER_FT<"deret">, ER_FM<0x1f>;
1002 def EI : DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1003 def DI : DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1005 def WAIT : WAIT_FT<"wait">;
1007 /// Load-linked, Store-conditional
1008 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1009 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1011 /// Jump and Branch Instructions
1012 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1013 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1014 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1015 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1016 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1017 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1019 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1021 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1023 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1025 def B : UncondBranch<BEQ>;
1027 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1028 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1029 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1030 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1031 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1032 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1033 def TAILCALL : TailCall<J>;
1034 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1036 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1038 // Exception handling related node and instructions.
1039 // The conversion sequence is:
1040 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1041 // MIPSeh_return -> (stack change + indirect branch)
1043 // MIPSeh_return takes the place of regular return instruction
1044 // but takes two arguments (V1, V0) which are used for storing
1045 // the offset and return address respectively.
1046 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1048 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1049 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1051 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1052 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1053 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1054 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1056 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1059 /// Multiply and Divide Instructions.
1060 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1062 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1064 def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1066 def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1069 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1070 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1071 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1072 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1074 /// Sign Ext In Register Instructions.
1075 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1076 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1079 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1080 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1082 /// Word Swap Bytes Within Halfwords
1083 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1086 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1088 // FrameIndexes are legalized when they are operands from load/store
1089 // instructions. The same not happens for stack address copies, so an
1090 // add op with mem ComplexPattern is used and the stack address copy
1091 // can be matched. It's similar to Sparc LEA_ADDRi
1092 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1095 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1096 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1097 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1098 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1100 let Predicates = [HasStdEnc, NotDSP] in {
1101 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1102 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1103 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1104 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1105 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1106 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1107 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1108 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1109 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1112 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1114 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1117 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1119 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1120 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1122 /// Move Control Registers From/To CPU Registers
1123 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1124 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1125 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1126 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1128 //===----------------------------------------------------------------------===//
1129 // Instruction aliases
1130 //===----------------------------------------------------------------------===//
1131 def : InstAlias<"move $dst, $src",
1132 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1133 Requires<[NotMips64]>;
1134 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1135 def : InstAlias<"addu $rs, $rt, $imm",
1136 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1137 def : InstAlias<"add $rs, $rt, $imm",
1138 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1139 def : InstAlias<"and $rs, $rt, $imm",
1140 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1141 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1142 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1143 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1144 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1145 def : InstAlias<"not $rt, $rs",
1146 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1147 def : InstAlias<"neg $rt, $rs",
1148 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1149 def : InstAlias<"negu $rt, $rs",
1150 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1151 def : InstAlias<"slt $rs, $rt, $imm",
1152 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1153 def : InstAlias<"xor $rs, $rt, $imm",
1154 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1155 def : InstAlias<"or $rs, $rt, $imm",
1156 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1157 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1158 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1159 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1160 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1161 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1162 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1163 def : InstAlias<"bnez $rs,$offset",
1164 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1165 def : InstAlias<"beqz $rs,$offset",
1166 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1167 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1169 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1170 def : InstAlias<"break", (BREAK 0, 0), 1>;
1171 def : InstAlias<"ei", (EI ZERO), 1>;
1172 def : InstAlias<"di", (DI ZERO), 1>;
1174 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1175 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1176 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1177 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1178 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1179 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1180 def : InstAlias<"sub, $rd, $rs, $imm",
1181 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1182 def : InstAlias<"subu, $rd, $rs, $imm",
1183 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1185 //===----------------------------------------------------------------------===//
1186 // Assembler Pseudo Instructions
1187 //===----------------------------------------------------------------------===//
1189 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1190 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1191 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1192 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1194 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1195 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1196 !strconcat(instr_asm, "\t$rt, $addr")> ;
1197 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1199 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1200 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1201 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1202 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1204 //===----------------------------------------------------------------------===//
1205 // Arbitrary patterns that map to one or more instructions
1206 //===----------------------------------------------------------------------===//
1208 // Load/store pattern templates.
1209 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1210 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1212 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1213 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1216 def : MipsPat<(i32 immSExt16:$in),
1217 (ADDiu ZERO, imm:$in)>;
1218 def : MipsPat<(i32 immZExt16:$in),
1219 (ORi ZERO, imm:$in)>;
1220 def : MipsPat<(i32 immLow16Zero:$in),
1221 (LUi (HI16 imm:$in))>;
1223 // Arbitrary immediates
1224 def : MipsPat<(i32 imm:$imm),
1225 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1227 // Carry MipsPatterns
1228 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1229 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1230 let Predicates = [HasStdEnc, NotDSP] in {
1231 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1232 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1233 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1234 (ADDiu GPR32:$src, imm:$imm)>;
1238 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1239 (JAL tglobaladdr:$dst)>;
1240 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1241 (JAL texternalsym:$dst)>;
1242 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1243 // (JALR GPR32:$dst)>;
1246 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1247 (TAILCALL tglobaladdr:$dst)>;
1248 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1249 (TAILCALL texternalsym:$dst)>;
1251 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1252 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1253 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1254 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1255 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1256 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1258 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1259 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1260 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1261 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1262 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1263 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1265 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1266 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1267 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1268 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1269 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1270 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1271 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1272 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1273 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1274 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1277 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1278 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1279 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1280 (ADDiu GPR32:$gp, tconstpool:$in)>;
1283 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1284 MipsPat<(MipsWrapper RC:$gp, node:$in),
1285 (ADDiuOp RC:$gp, node:$in)>;
1287 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1288 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1289 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1290 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1291 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1292 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1294 // Mips does not have "not", so we expand our way
1295 def : MipsPat<(not GPR32:$in),
1296 (NOR GPR32Opnd:$in, ZERO)>;
1299 let Predicates = [HasStdEnc] in {
1300 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1301 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1302 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1306 let Predicates = [HasStdEnc] in
1307 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1310 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1311 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1312 Instruction SLTiuOp, Register ZEROReg> {
1313 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1314 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1315 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1316 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1318 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1319 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1320 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1321 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1322 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1323 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1324 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1325 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1326 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1327 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1328 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1329 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1331 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1332 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1333 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1334 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1336 def : MipsPat<(brcond RC:$cond, bb:$dst),
1337 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1340 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1342 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1343 (BLEZ i32:$lhs, bb:$dst)>;
1344 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1345 (BGEZ i32:$lhs, bb:$dst)>;
1348 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1349 Instruction SLTuOp, Register ZEROReg> {
1350 def : MipsPat<(seteq RC:$lhs, 0),
1351 (SLTiuOp RC:$lhs, 1)>;
1352 def : MipsPat<(setne RC:$lhs, 0),
1353 (SLTuOp ZEROReg, RC:$lhs)>;
1354 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1355 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1356 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1357 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1360 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1361 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1362 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1363 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1364 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1367 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1368 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1369 (SLTOp RC:$rhs, RC:$lhs)>;
1370 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1371 (SLTuOp RC:$rhs, RC:$lhs)>;
1374 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1375 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1376 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1377 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1378 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1381 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1382 Instruction SLTiuOp> {
1383 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1384 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1385 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1386 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1389 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1390 defm : SetlePats<GPR32, SLT, SLTu>;
1391 defm : SetgtPats<GPR32, SLT, SLTu>;
1392 defm : SetgePats<GPR32, SLT, SLTu>;
1393 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1396 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1398 // Load halfword/word patterns.
1399 let AddedComplexity = 40 in {
1400 let Predicates = [HasStdEnc] in {
1401 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1402 def : LoadRegImmPat<LH, i32, sextloadi16>;
1403 def : LoadRegImmPat<LW, i32, load>;
1407 //===----------------------------------------------------------------------===//
1408 // Floating Point Support
1409 //===----------------------------------------------------------------------===//
1411 include "MipsInstrFPU.td"
1412 include "Mips64InstrInfo.td"
1413 include "MipsCondMov.td"
1418 include "Mips16InstrFormats.td"
1419 include "Mips16InstrInfo.td"
1422 include "MipsDSPInstrFormats.td"
1423 include "MipsDSPInstrInfo.td"
1426 include "MipsMSAInstrFormats.td"
1427 include "MipsMSAInstrInfo.td"
1430 include "MicroMipsInstrFormats.td"
1431 include "MicroMipsInstrInfo.td"