1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def pcrel16 : Operand<i32> {
284 def MipsMemAsmOperand : AsmOperandClass {
286 let ParserMethod = "parseMemOperand";
289 def MipsInvertedImmoperand : AsmOperandClass {
291 let RenderMethod = "addImmOperands";
292 let ParserMethod = "parseInvNum";
295 def PtrRegAsmOperand : AsmOperandClass {
297 let ParserMethod = "parsePtrReg";
301 def InvertedImOperand : Operand<i32> {
302 let ParserMatchClass = MipsInvertedImmoperand;
305 class mem_generic : Operand<iPTR> {
306 let PrintMethod = "printMemOperand";
307 let MIOperandInfo = (ops ptr_rc, simm16);
308 let EncoderMethod = "getMemEncoding";
309 let ParserMatchClass = MipsMemAsmOperand;
310 let OperandType = "OPERAND_MEMORY";
314 def mem : mem_generic;
316 // MSA specific address operand
317 def mem_msa : mem_generic {
318 let EncoderMethod = "getMSAMemEncoding";
321 def mem_ea : Operand<iPTR> {
322 let PrintMethod = "printMemOperandEA";
323 let MIOperandInfo = (ops ptr_rc, simm16);
324 let EncoderMethod = "getMemEncoding";
325 let OperandType = "OPERAND_MEMORY";
328 def PtrRC : Operand<iPTR> {
329 let MIOperandInfo = (ops ptr_rc);
330 let DecoderMethod = "DecodePtrRegisterClass";
331 let ParserMatchClass = PtrRegAsmOperand;
334 // size operand of ext instruction
335 def size_ext : Operand<i32> {
336 let EncoderMethod = "getSizeExtEncoding";
337 let DecoderMethod = "DecodeExtSize";
340 // size operand of ins instruction
341 def size_ins : Operand<i32> {
342 let EncoderMethod = "getSizeInsEncoding";
343 let DecoderMethod = "DecodeInsSize";
346 // Transformation Function - get the lower 16 bits.
347 def LO16 : SDNodeXForm<imm, [{
348 return getImm(N, N->getZExtValue() & 0xFFFF);
351 // Transformation Function - get the higher 16 bits.
352 def HI16 : SDNodeXForm<imm, [{
353 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
357 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
359 // Node immediate fits as 16-bit sign extended on target immediate.
361 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
363 // Node immediate fits as 16-bit sign extended on target immediate.
365 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
367 // Node immediate fits as 15-bit sign extended on target immediate.
369 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
371 // Node immediate fits as 16-bit zero extended on target immediate.
372 // The LO16 param means that only the lower 16 bits of the node
373 // immediate are caught.
375 def immZExt16 : PatLeaf<(imm), [{
376 if (N->getValueType(0) == MVT::i32)
377 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
379 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
382 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
383 def immLow16Zero : PatLeaf<(imm), [{
384 int64_t Val = N->getSExtValue();
385 return isInt<32>(Val) && !(Val & 0xffff);
388 // shamt field must fit in 5 bits.
389 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
391 // True if (N + 1) fits in 16-bit field.
392 def immSExt16Plus1 : PatLeaf<(imm), [{
393 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
396 // Mips Address Mode! SDNode frameindex could possibily be a match
397 // since load and store instructions from stack used it.
399 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
402 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
405 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
408 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
410 //===----------------------------------------------------------------------===//
411 // Instructions specific format
412 //===----------------------------------------------------------------------===//
414 // Arithmetic and logical instructions with 3 register operands.
415 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
416 InstrItinClass Itin = NoItinerary,
417 SDPatternOperator OpNode = null_frag>:
418 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
419 !strconcat(opstr, "\t$rd, $rs, $rt"),
420 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
421 let isCommutable = isComm;
422 let isReMaterializable = 1;
425 // Arithmetic and logical instructions with 2 register operands.
426 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
427 InstrItinClass Itin = NoItinerary,
428 SDPatternOperator imm_type = null_frag,
429 SDPatternOperator OpNode = null_frag> :
430 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
431 !strconcat(opstr, "\t$rt, $rs, $imm16"),
432 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
434 let isReMaterializable = 1;
435 let TwoOperandAliasConstraint = "$rs = $rt";
438 // Arithmetic Multiply ADD/SUB
439 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
440 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
441 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
442 let Defs = [HI0, LO0];
443 let Uses = [HI0, LO0];
444 let isCommutable = isComm;
448 class LogicNOR<string opstr, RegisterOperand RO>:
449 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
450 !strconcat(opstr, "\t$rd, $rs, $rt"),
451 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
452 let isCommutable = 1;
456 class shift_rotate_imm<string opstr, Operand ImmOpnd,
457 RegisterOperand RO, InstrItinClass itin,
458 SDPatternOperator OpNode = null_frag,
459 SDPatternOperator PF = null_frag> :
460 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
461 !strconcat(opstr, "\t$rd, $rt, $shamt"),
462 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
464 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
465 SDPatternOperator OpNode = null_frag>:
466 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
467 !strconcat(opstr, "\t$rd, $rt, $rs"),
468 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
471 // Load Upper Imediate
472 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
473 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
474 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
475 let neverHasSideEffects = 1;
476 let isReMaterializable = 1;
480 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
481 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
482 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
483 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
484 let DecoderMethod = "DecodeMem";
485 let canFoldAsLoad = 1;
489 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
490 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
491 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
492 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
493 let DecoderMethod = "DecodeMem";
497 // Load/Store Left/Right
498 let canFoldAsLoad = 1 in
499 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
500 InstrItinClass Itin> :
501 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
502 !strconcat(opstr, "\t$rt, $addr"),
503 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
504 let DecoderMethod = "DecodeMem";
505 string Constraints = "$src = $rt";
508 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
509 InstrItinClass Itin> :
510 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
511 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
512 let DecoderMethod = "DecodeMem";
515 // Conditional Branch
516 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
517 RegisterOperand RO> :
518 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
519 !strconcat(opstr, "\t$rs, $rt, $offset"),
520 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
523 let isTerminator = 1;
524 let hasDelaySlot = 1;
528 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
529 RegisterOperand RO> :
530 InstSE<(outs), (ins RO:$rs, opnd:$offset),
531 !strconcat(opstr, "\t$rs, $offset"),
532 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
535 let isTerminator = 1;
536 let hasDelaySlot = 1;
541 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
542 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
543 !strconcat(opstr, "\t$rd, $rs, $rt"),
544 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
545 II_SLT_SLTU, FrmR, opstr>;
547 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
549 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
550 !strconcat(opstr, "\t$rt, $rs, $imm16"),
551 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
552 II_SLTI_SLTIU, FrmI, opstr>;
555 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
556 SDPatternOperator targetoperator, string bopstr> :
557 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
558 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
561 let hasDelaySlot = 1;
562 let DecoderMethod = "DecodeJumpTarget";
566 // Unconditional branch
567 class UncondBranch<Instruction BEQInst> :
568 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
569 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
571 let isTerminator = 1;
573 let hasDelaySlot = 1;
574 let Predicates = [RelocPIC, HasStdEnc];
578 // Base class for indirect branch and return instruction classes.
579 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
580 class JumpFR<string opstr, RegisterOperand RO,
581 SDPatternOperator operator = null_frag>:
582 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
586 class IndirectBranch<string opstr, RegisterOperand RO> :
587 JumpFR<opstr, RO, brind> {
589 let isIndirectBranch = 1;
592 // Return instruction
593 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
595 let isCodeGenOnly = 1;
597 let hasExtraSrcRegAllocReq = 1;
600 // Jump and Link (Call)
601 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
602 class JumpLink<string opstr, DAGOperand opnd> :
603 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
604 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
605 let DecoderMethod = "DecodeJumpTarget";
608 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
609 Register RetReg, RegisterOperand ResRO = RO>:
610 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
611 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
613 class JumpLinkReg<string opstr, RegisterOperand RO>:
614 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
615 [], IIBranch, FrmR, opstr>;
617 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
618 InstSE<(outs), (ins RO:$rs, opnd:$offset),
619 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
623 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
624 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
625 class TailCall<Instruction JumpInst> :
626 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
627 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
629 class TailCallReg<RegisterOperand RO, Instruction JRInst,
630 RegisterOperand ResRO = RO> :
631 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
632 PseudoInstExpansion<(JRInst ResRO:$rs)>;
635 class BAL_BR_Pseudo<Instruction RealInst> :
636 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
637 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
639 let isTerminator = 1;
641 let hasDelaySlot = 1;
646 class SYS_FT<string opstr> :
647 InstSE<(outs), (ins uimm20:$code_),
648 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
650 class BRK_FT<string opstr> :
651 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
652 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
656 class ER_FT<string opstr> :
657 InstSE<(outs), (ins),
658 opstr, [], NoItinerary, FrmOther, opstr>;
661 class DEI_FT<string opstr, RegisterOperand RO> :
662 InstSE<(outs RO:$rt), (ins),
663 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
666 class WAIT_FT<string opstr> :
667 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
670 let hasSideEffects = 1 in
671 class SYNC_FT<string opstr> :
672 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
673 NoItinerary, FrmOther, opstr>;
675 let hasSideEffects = 1 in
676 class TEQ_FT<string opstr, RegisterOperand RO> :
677 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
678 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
681 class TEQI_FT<string opstr, RegisterOperand RO> :
682 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
683 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
685 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
686 list<Register> DefRegs> :
687 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
689 let isCommutable = 1;
691 let neverHasSideEffects = 1;
694 // Pseudo multiply/divide instruction with explicit accumulator register
696 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
697 SDPatternOperator OpNode, InstrItinClass Itin,
698 bit IsComm = 1, bit HasSideEffects = 0,
699 bit UsesCustomInserter = 0> :
700 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
701 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
702 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
703 let isCommutable = IsComm;
704 let hasSideEffects = HasSideEffects;
705 let usesCustomInserter = UsesCustomInserter;
708 // Pseudo multiply add/sub instruction with explicit accumulator register
710 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
712 : PseudoSE<(outs ACC64:$ac),
713 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
715 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
717 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
718 string Constraints = "$acin = $ac";
721 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
722 list<Register> DefRegs> :
723 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
724 [], itin, FrmR, opstr> {
729 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
730 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
731 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
733 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
734 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
737 let neverHasSideEffects = 1;
740 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
741 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
742 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
745 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
746 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
749 let neverHasSideEffects = 1;
752 class EffectiveAddress<string opstr, RegisterOperand RO> :
753 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
754 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
755 !strconcat(opstr, "_lea")> {
756 let isCodeGenOnly = 1;
757 let DecoderMethod = "DecodeMem";
760 // Count Leading Ones/Zeros in Word
761 class CountLeading0<string opstr, RegisterOperand RO>:
762 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
763 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
764 Requires<[HasBitCount, HasStdEnc]>;
766 class CountLeading1<string opstr, RegisterOperand RO>:
767 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
768 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
769 Requires<[HasBitCount, HasStdEnc]>;
772 // Sign Extend in Register.
773 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
774 InstrItinClass itin> :
775 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
776 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
777 let Predicates = [HasSEInReg, HasStdEnc];
781 class SubwordSwap<string opstr, RegisterOperand RO>:
782 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
783 NoItinerary, FrmR, opstr> {
784 let Predicates = [HasSwap, HasStdEnc];
785 let neverHasSideEffects = 1;
789 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
790 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
794 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
795 SDPatternOperator Op = null_frag>:
796 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
797 !strconcat(opstr, " $rt, $rs, $pos, $size"),
798 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
800 let Predicates = [HasMips32r2, HasStdEnc];
803 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
804 SDPatternOperator Op = null_frag>:
805 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
806 !strconcat(opstr, " $rt, $rs, $pos, $size"),
807 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
808 NoItinerary, FrmR, opstr> {
809 let Predicates = [HasMips32r2, HasStdEnc];
810 let Constraints = "$src = $rt";
813 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
814 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
815 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
816 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
818 // Atomic Compare & Swap.
819 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
820 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
821 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
823 class LLBase<string opstr, RegisterOperand RO> :
824 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
825 [], NoItinerary, FrmI> {
826 let DecoderMethod = "DecodeMem";
830 class SCBase<string opstr, RegisterOperand RO> :
831 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
832 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
833 let DecoderMethod = "DecodeMem";
835 let Constraints = "$rt = $dst";
838 class MFC3OP<string asmstr, RegisterOperand RO> :
839 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
840 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
842 class TrapBase<Instruction RealInst>
843 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
844 PseudoInstExpansion<(RealInst 0, 0)> {
846 let isTerminator = 1;
847 let isCodeGenOnly = 1;
850 //===----------------------------------------------------------------------===//
851 // Pseudo instructions
852 //===----------------------------------------------------------------------===//
855 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
856 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
858 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
859 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
860 [(callseq_start timm:$amt)]>;
861 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
862 [(callseq_end timm:$amt1, timm:$amt2)]>;
865 let usesCustomInserter = 1 in {
866 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
867 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
868 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
869 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
870 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
871 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
872 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
873 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
874 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
875 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
876 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
877 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
878 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
879 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
880 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
881 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
882 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
883 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
885 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
886 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
887 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
889 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
890 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
891 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
894 /// Pseudo instructions for loading and storing accumulator registers.
895 let isPseudo = 1, isCodeGenOnly = 1 in {
896 def LOAD_ACC64 : Load<"", ACC64>;
897 def STORE_ACC64 : Store<"", ACC64>;
900 //===----------------------------------------------------------------------===//
901 // Instruction definition
902 //===----------------------------------------------------------------------===//
903 //===----------------------------------------------------------------------===//
904 // MipsI Instructions
905 //===----------------------------------------------------------------------===//
907 /// Arithmetic Instructions (ALU Immediate)
908 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
910 ADDI_FM<0x9>, IsAsCheapAsAMove;
911 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
912 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
914 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
916 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
919 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
922 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
925 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
927 /// Arithmetic Instructions (3-Operand, R-Type)
928 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
930 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
932 let Defs = [HI0, LO0] in
933 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
935 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
936 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
937 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
938 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
939 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
941 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
943 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
945 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
947 /// Shift Instructions
948 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
949 immZExt5>, SRA_FM<0, 0>;
950 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
951 immZExt5>, SRA_FM<2, 0>;
952 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
953 immZExt5>, SRA_FM<3, 0>;
954 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
956 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
958 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
961 // Rotate Instructions
962 let Predicates = [HasMips32r2, HasStdEnc] in {
963 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
964 immZExt5>, SRA_FM<2, 1>;
965 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
969 /// Load and Store Instructions
971 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
972 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
974 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
976 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
977 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
979 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
980 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
981 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
983 /// load/store left/right
984 let Predicates = [NotInMicroMips] in {
985 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
986 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
987 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
988 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
991 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
992 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
993 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
994 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
995 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
996 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
997 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
999 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1000 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1001 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1002 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1003 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1004 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1006 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1007 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1008 def TRAP : TrapBase<BREAK>;
1010 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1011 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1013 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1014 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1016 def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM;
1018 /// Load-linked, Store-conditional
1019 let Predicates = [NotInMicroMips] in {
1020 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1021 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1024 /// Jump and Branch Instructions
1025 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1026 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1027 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1028 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1029 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1030 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1032 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1034 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1036 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1038 def B : UncondBranch<BEQ>;
1040 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1041 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1042 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1043 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1044 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1045 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1046 def TAILCALL : TailCall<J>;
1047 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1049 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1051 // Exception handling related node and instructions.
1052 // The conversion sequence is:
1053 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1054 // MIPSeh_return -> (stack change + indirect branch)
1056 // MIPSeh_return takes the place of regular return instruction
1057 // but takes two arguments (V1, V0) which are used for storing
1058 // the offset and return address respectively.
1059 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1061 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1062 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1064 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1065 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1066 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1067 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1069 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1072 /// Multiply and Divide Instructions.
1073 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1075 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1077 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1079 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1082 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1083 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1084 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1085 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1087 /// Sign Ext In Register Instructions.
1088 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1089 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1092 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1093 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1095 /// Word Swap Bytes Within Halfwords
1096 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1099 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1101 // FrameIndexes are legalized when they are operands from load/store
1102 // instructions. The same not happens for stack address copies, so an
1103 // add op with mem ComplexPattern is used and the stack address copy
1104 // can be matched. It's similar to Sparc LEA_ADDRi
1105 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1108 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1109 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1110 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1111 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1113 let Predicates = [HasStdEnc, NotDSP] in {
1114 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1115 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1116 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1117 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1118 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1119 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1120 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1121 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1122 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1125 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1127 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1130 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1132 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1133 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1135 /// Move Control Registers From/To CPU Registers
1136 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1137 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1138 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1139 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1141 //===----------------------------------------------------------------------===//
1142 // Instruction aliases
1143 //===----------------------------------------------------------------------===//
1144 def : InstAlias<"move $dst, $src",
1145 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1146 Requires<[NotMips64]>;
1147 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1148 def : InstAlias<"addu $rs, $rt, $imm",
1149 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1150 def : InstAlias<"add $rs, $rt, $imm",
1151 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1152 def : InstAlias<"and $rs, $rt, $imm",
1153 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1154 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1155 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1156 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1157 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1158 def : InstAlias<"not $rt, $rs",
1159 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1160 def : InstAlias<"neg $rt, $rs",
1161 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1162 def : InstAlias<"negu $rt, $rs",
1163 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1164 def : InstAlias<"slt $rs, $rt, $imm",
1165 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1166 def : InstAlias<"xor $rs, $rt, $imm",
1167 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1168 def : InstAlias<"or $rs, $rt, $imm",
1169 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1170 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1171 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1172 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1173 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1174 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1175 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1176 def : InstAlias<"bnez $rs,$offset",
1177 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1178 def : InstAlias<"beqz $rs,$offset",
1179 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1180 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1182 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1183 def : InstAlias<"break", (BREAK 0, 0), 1>;
1184 def : InstAlias<"ei", (EI ZERO), 1>;
1185 def : InstAlias<"di", (DI ZERO), 1>;
1187 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1188 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1189 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1190 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1191 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1192 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1193 def : InstAlias<"sub, $rd, $rs, $imm",
1194 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1195 def : InstAlias<"subu, $rd, $rs, $imm",
1196 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1198 //===----------------------------------------------------------------------===//
1199 // Assembler Pseudo Instructions
1200 //===----------------------------------------------------------------------===//
1202 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1203 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1204 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1205 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1207 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1208 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1209 !strconcat(instr_asm, "\t$rt, $addr")> ;
1210 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1212 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1213 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1214 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1215 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1217 //===----------------------------------------------------------------------===//
1218 // Arbitrary patterns that map to one or more instructions
1219 //===----------------------------------------------------------------------===//
1221 // Load/store pattern templates.
1222 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1223 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1225 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1226 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1229 def : MipsPat<(i32 immSExt16:$in),
1230 (ADDiu ZERO, imm:$in)>;
1231 def : MipsPat<(i32 immZExt16:$in),
1232 (ORi ZERO, imm:$in)>;
1233 def : MipsPat<(i32 immLow16Zero:$in),
1234 (LUi (HI16 imm:$in))>;
1236 // Arbitrary immediates
1237 def : MipsPat<(i32 imm:$imm),
1238 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1240 // Carry MipsPatterns
1241 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1242 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1243 let Predicates = [HasStdEnc, NotDSP] in {
1244 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1245 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1246 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1247 (ADDiu GPR32:$src, imm:$imm)>;
1251 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1252 (JAL tglobaladdr:$dst)>;
1253 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1254 (JAL texternalsym:$dst)>;
1255 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1256 // (JALR GPR32:$dst)>;
1259 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1260 (TAILCALL tglobaladdr:$dst)>;
1261 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1262 (TAILCALL texternalsym:$dst)>;
1264 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1265 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1266 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1267 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1268 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1269 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1271 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1272 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1273 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1274 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1275 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1276 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1278 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1279 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1280 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1281 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1282 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1283 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1284 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1285 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1286 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1287 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1290 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1291 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1292 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1293 (ADDiu GPR32:$gp, tconstpool:$in)>;
1296 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1297 MipsPat<(MipsWrapper RC:$gp, node:$in),
1298 (ADDiuOp RC:$gp, node:$in)>;
1300 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1301 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1302 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1303 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1304 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1305 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1307 // Mips does not have "not", so we expand our way
1308 def : MipsPat<(not GPR32:$in),
1309 (NOR GPR32Opnd:$in, ZERO)>;
1312 let Predicates = [HasStdEnc] in {
1313 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1314 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1315 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1319 let Predicates = [HasStdEnc] in
1320 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1323 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1324 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1325 Instruction SLTiuOp, Register ZEROReg> {
1326 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1327 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1328 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1329 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1331 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1332 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1333 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1334 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1335 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1336 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1337 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1338 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1339 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1340 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1341 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1342 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1344 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1345 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1346 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1347 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1349 def : MipsPat<(brcond RC:$cond, bb:$dst),
1350 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1353 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1355 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1356 (BLEZ i32:$lhs, bb:$dst)>;
1357 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1358 (BGEZ i32:$lhs, bb:$dst)>;
1361 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1362 Instruction SLTuOp, Register ZEROReg> {
1363 def : MipsPat<(seteq RC:$lhs, 0),
1364 (SLTiuOp RC:$lhs, 1)>;
1365 def : MipsPat<(setne RC:$lhs, 0),
1366 (SLTuOp ZEROReg, RC:$lhs)>;
1367 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1368 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1369 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1370 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1373 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1374 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1375 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1376 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1377 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1380 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1381 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1382 (SLTOp RC:$rhs, RC:$lhs)>;
1383 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1384 (SLTuOp RC:$rhs, RC:$lhs)>;
1387 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1388 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1389 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1390 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1391 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1394 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1395 Instruction SLTiuOp> {
1396 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1397 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1398 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1399 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1402 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1403 defm : SetlePats<GPR32, SLT, SLTu>;
1404 defm : SetgtPats<GPR32, SLT, SLTu>;
1405 defm : SetgePats<GPR32, SLT, SLTu>;
1406 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1409 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1411 // Load halfword/word patterns.
1412 let AddedComplexity = 40 in {
1413 let Predicates = [HasStdEnc] in {
1414 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1415 def : LoadRegImmPat<LH, i32, sextloadi16>;
1416 def : LoadRegImmPat<LW, i32, load>;
1420 //===----------------------------------------------------------------------===//
1421 // Floating Point Support
1422 //===----------------------------------------------------------------------===//
1424 include "MipsInstrFPU.td"
1425 include "Mips64InstrInfo.td"
1426 include "MipsCondMov.td"
1431 include "Mips16InstrFormats.td"
1432 include "Mips16InstrInfo.td"
1435 include "MipsDSPInstrFormats.td"
1436 include "MipsDSPInstrInfo.td"
1439 include "MipsMSAInstrFormats.td"
1440 include "MipsMSAInstrInfo.td"
1443 include "MicroMipsInstrFormats.td"
1444 include "MicroMipsInstrInfo.td"
1445 include "MicroMipsInstrFPU.td"