1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "MipsInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Mips profiles and nodes
22 //===----------------------------------------------------------------------===//
24 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
25 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
26 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
30 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
31 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
32 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
33 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
36 def SDT_MipsDivRem : SDTypeProfile<0, 2,
40 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
42 def SDT_MipsDynAlloc : SDTypeProfile<1, 1, [SDTCisVT<0, i32>,
44 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
46 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
47 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
48 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
49 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
53 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
54 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapperPIC : SDNode<"MipsISD::WrapperPIC", SDTIntUnaryOp>;
112 // Pointer to dynamically allocated stack area.
113 def MipsDynAlloc : SDNode<"MipsISD::DynAlloc", SDT_MipsDynAlloc,
114 [SDNPHasChain, SDNPInGlue]>;
116 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain]>;
118 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
119 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
121 //===----------------------------------------------------------------------===//
122 // Mips Instruction Predicate Definitions.
123 //===----------------------------------------------------------------------===//
124 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">;
125 def HasBitCount : Predicate<"Subtarget.hasBitCount()">;
126 def HasSwap : Predicate<"Subtarget.hasSwap()">;
127 def HasCondMov : Predicate<"Subtarget.hasCondMov()">;
128 def HasMips32 : Predicate<"Subtarget.hasMips32()">;
129 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">;
130 def HasMips64 : Predicate<"Subtarget.hasMips64()">;
131 def NotMips64 : Predicate<"!Subtarget.hasMips64()">;
132 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">;
133 def IsN64 : Predicate<"Subtarget.isABI_N64()">;
134 def NotN64 : Predicate<"!Subtarget.isABI_N64()">;
136 //===----------------------------------------------------------------------===//
137 // Mips Operand, Complex Patterns and Transformations Definitions.
138 //===----------------------------------------------------------------------===//
140 // Instruction operand types
141 def brtarget : Operand<OtherVT>;
142 def calltarget : Operand<i32>;
143 def simm16 : Operand<i32>;
144 def simm16_64 : Operand<i64>;
145 def shamt : Operand<i32>;
148 def uimm16 : Operand<i32> {
149 let PrintMethod = "printUnsignedImm";
153 def mem : Operand<i32> {
154 let PrintMethod = "printMemOperand";
155 let MIOperandInfo = (ops CPURegs, simm16);
158 def mem64 : Operand<i64> {
159 let PrintMethod = "printMemOperand";
160 let MIOperandInfo = (ops CPU64Regs, simm16_64);
163 def mem_ea : Operand<i32> {
164 let PrintMethod = "printMemOperandEA";
165 let MIOperandInfo = (ops CPURegs, simm16);
168 // Transformation Function - get the lower 16 bits.
169 def LO16 : SDNodeXForm<imm, [{
170 return getI32Imm((unsigned)N->getZExtValue() & 0xFFFF);
173 // Transformation Function - get the higher 16 bits.
174 def HI16 : SDNodeXForm<imm, [{
175 return getI32Imm((unsigned)N->getZExtValue() >> 16);
178 // Node immediate fits as 16-bit sign extended on target immediate.
180 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
182 // Node immediate fits as 16-bit zero extended on target immediate.
183 // The LO16 param means that only the lower 16 bits of the node
184 // immediate are caught.
186 def immZExt16 : PatLeaf<(imm), [{
187 if (N->getValueType(0) == MVT::i32)
188 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
190 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
193 // shamt field must fit in 5 bits.
194 def immZExt5 : PatLeaf<(imm), [{
195 return N->getZExtValue() == ((N->getZExtValue()) & 0x1f) ;
198 // Mips Address Mode! SDNode frameindex could possibily be a match
199 // since load and store instructions from stack used it.
200 def addr : ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], []>;
202 //===----------------------------------------------------------------------===//
203 // Pattern fragment for load/store
204 //===----------------------------------------------------------------------===//
205 class UnalignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
206 LoadSDNode *LD = cast<LoadSDNode>(N);
207 return LD->getMemoryVT().getSizeInBits()/8 > LD->getAlignment();
210 class AlignedLoad<PatFrag Node> : PatFrag<(ops node:$ptr), (Node node:$ptr), [{
211 LoadSDNode *LD = cast<LoadSDNode>(N);
212 return LD->getMemoryVT().getSizeInBits()/8 <= LD->getAlignment();
215 class UnalignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
216 (Node node:$val, node:$ptr), [{
217 StoreSDNode *SD = cast<StoreSDNode>(N);
218 return SD->getMemoryVT().getSizeInBits()/8 > SD->getAlignment();
221 class AlignedStore<PatFrag Node> : PatFrag<(ops node:$val, node:$ptr),
222 (Node node:$val, node:$ptr), [{
223 StoreSDNode *SD = cast<StoreSDNode>(N);
224 return SD->getMemoryVT().getSizeInBits()/8 <= SD->getAlignment();
227 // Load/Store PatFrags.
228 def sextloadi16_a : AlignedLoad<sextloadi16>;
229 def zextloadi16_a : AlignedLoad<zextloadi16>;
230 def extloadi16_a : AlignedLoad<extloadi16>;
231 def load_a : AlignedLoad<load>;
232 def sextloadi32_a : AlignedLoad<sextloadi32>;
233 def zextloadi32_a : AlignedLoad<zextloadi32>;
234 def extloadi32_a : AlignedLoad<extloadi32>;
235 def truncstorei16_a : AlignedStore<truncstorei16>;
236 def store_a : AlignedStore<store>;
237 def truncstorei32_a : AlignedStore<truncstorei32>;
238 def sextloadi16_u : UnalignedLoad<sextloadi16>;
239 def zextloadi16_u : UnalignedLoad<zextloadi16>;
240 def extloadi16_u : UnalignedLoad<extloadi16>;
241 def load_u : UnalignedLoad<load>;
242 def sextloadi32_u : UnalignedLoad<sextloadi32>;
243 def zextloadi32_u : UnalignedLoad<zextloadi32>;
244 def extloadi32_u : UnalignedLoad<extloadi32>;
245 def truncstorei16_u : UnalignedStore<truncstorei16>;
246 def store_u : UnalignedStore<store>;
247 def truncstorei32_u : UnalignedStore<truncstorei32>;
249 //===----------------------------------------------------------------------===//
250 // Instructions specific format
251 //===----------------------------------------------------------------------===//
253 // Arithmetic 3 register operands
254 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
255 InstrItinClass itin, bit isComm = 0>:
256 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
257 !strconcat(instr_asm, "\t$dst, $b, $c"),
258 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin> {
259 let isCommutable = isComm;
262 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm,
264 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
265 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu> {
266 let isCommutable = isComm;
269 // Arithmetic 2 register operands
270 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
271 Operand Od, PatLeaf imm_type> :
272 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
273 !strconcat(instr_asm, "\t$dst, $b, $c"),
274 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
276 class ArithOverflowI<bits<6> op, string instr_asm, SDNode OpNode,
277 Operand Od, PatLeaf imm_type> :
278 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, Od:$c),
279 !strconcat(instr_asm, "\t$dst, $b, $c"), [], IIAlu>;
281 // Arithmetic Multiply ADD/SUB
282 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
283 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
284 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
285 !strconcat(instr_asm, "\t$rs, $rt"),
286 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
287 let isCommutable = isComm;
291 let isCommutable = 1 in
292 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
293 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
294 !strconcat(instr_asm, "\t$dst, $b, $c"),
295 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
297 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
298 FI<op, (outs CPURegs:$dst), (ins CPURegs:$b, uimm16:$c),
299 !strconcat(instr_asm, "\t$dst, $b, $c"),
300 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt16:$c))], IIAlu>;
302 let isCommutable = 1 in
303 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
304 FR<op, func, (outs CPURegs:$dst), (ins CPURegs:$b, CPURegs:$c),
305 !strconcat(instr_asm, "\t$dst, $b, $c"),
306 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
309 class LogicR_shift_rotate_imm<bits<6> func, bits<5> _rs, string instr_asm,
311 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$b, shamt:$c),
312 !strconcat(instr_asm, "\t$dst, $b, $c"),
313 [(set CPURegs:$dst, (OpNode CPURegs:$b, (i32 immZExt5:$c)))], IIAlu> {
317 class LogicR_shift_rotate_reg<bits<6> func, bits<5> _shamt, string instr_asm,
319 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$c, CPURegs:$b),
320 !strconcat(instr_asm, "\t$dst, $b, $c"),
321 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu> {
325 // Load Upper Imediate
326 class LoadUpper<bits<6> op, string instr_asm>:
330 !strconcat(instr_asm, "\t$dst, $imm"),
334 let canFoldAsLoad = 1 in
335 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
336 Operand MemOpnd, bit Pseudo>:
337 FI<op, (outs RC:$dst), (ins MemOpnd:$addr),
338 !strconcat(instr_asm, "\t$dst, $addr"),
339 [(set RC:$dst, (OpNode addr:$addr))], IILoad> {
340 let isPseudo = Pseudo;
343 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
344 Operand MemOpnd, bit Pseudo>:
345 FI<op, (outs), (ins RC:$dst, MemOpnd:$addr),
346 !strconcat(instr_asm, "\t$dst, $addr"),
347 [(OpNode RC:$dst, addr:$addr)], IIStore> {
348 let isPseudo = Pseudo;
352 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
354 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
356 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
361 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
363 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
365 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
370 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
372 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
374 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
379 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
381 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
383 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
387 // Conditional Branch
388 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op, RegisterClass RC>:
389 CBranchBase<op, (outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
390 !strconcat(instr_asm, "\t$rs, $rt, $offset"),
391 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch> {
393 let isTerminator = 1;
394 let hasDelaySlot = 1;
397 class CBranchZero<bits<6> op, bits<5> _rt, string instr_asm, PatFrag cond_op,
399 CBranchBase<op, (outs), (ins RC:$rs, brtarget:$offset),
400 !strconcat(instr_asm, "\t$rs, $offset"),
401 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch> {
404 let isTerminator = 1;
405 let hasDelaySlot = 1;
409 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
411 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
412 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
413 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
416 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
417 PatLeaf imm_type, RegisterClass RC>:
418 FI<op, (outs CPURegs:$rd), (ins RC:$rs, Od:$i),
419 !strconcat(instr_asm, "\t$rd, $rs, $i"),
420 [(set CPURegs:$rd, (cond_op RC:$rs, imm_type:$i))],
423 // Unconditional branch
424 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
425 class JumpFJ<bits<6> op, string instr_asm>:
426 FJ<op, (outs), (ins brtarget:$target),
427 !strconcat(instr_asm, "\t$target"), [(br bb:$target)], IIBranch>;
429 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
430 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
431 FR<op, func, (outs), (ins CPURegs:$target),
432 !strconcat(instr_asm, "\t$target"), [(brind CPURegs:$target)], IIBranch>;
434 // Jump and Link (Call)
435 let isCall=1, hasDelaySlot=1,
436 // All calls clobber the non-callee saved registers...
437 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2, T3, T4, T5, T6, T7, T8, T9,
438 K0, K1, D0, D1, D2, D3, D4, D5, D6, D7, D8, D9], Uses = [GP] in {
439 class JumpLink<bits<6> op, string instr_asm>:
440 FJ<op, (outs), (ins calltarget:$target, variable_ops),
441 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
445 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
446 FR<op, func, (outs), (ins CPURegs:$rs, variable_ops),
447 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink CPURegs:$rs)], IIBranch>;
449 class BranchLink<string instr_asm>:
450 FI<0x1, (outs), (ins CPURegs:$rs, brtarget:$target, variable_ops),
451 !strconcat(instr_asm, "\t$rs, $target"), [], IIBranch>;
455 let Defs = [HI, LO] in {
456 let isCommutable = 1 in
457 class Mul<bits<6> func, string instr_asm, InstrItinClass itin>:
458 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
459 !strconcat(instr_asm, "\t$a, $b"), [], itin>;
461 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
462 FR<0x00, func, (outs), (ins CPURegs:$a, CPURegs:$b),
463 !strconcat(instr_asm, "\t$$zero, $a, $b"),
464 [(op CPURegs:$a, CPURegs:$b)], itin>;
469 let rs = 0, rt = 0 in
470 class MoveFromLOHI<bits<6> func, string instr_asm>:
471 FR<0x00, func, (outs CPURegs:$dst), (ins),
472 !strconcat(instr_asm, "\t$dst"), [], IIHiLo>;
474 let rt = 0, rd = 0 in
475 class MoveToLOHI<bits<6> func, string instr_asm>:
476 FR<0x00, func, (outs), (ins CPURegs:$src),
477 !strconcat(instr_asm, "\t$src"), [], IIHiLo>;
480 class EffectiveAddress<string instr_asm> :
481 FI<0x09, (outs CPURegs:$dst), (ins mem_ea:$addr),
482 instr_asm, [(set CPURegs:$dst, addr:$addr)], IIAlu>;
484 // Count Leading Ones/Zeros in Word
485 class CountLeading<bits<6> func, string instr_asm, list<dag> pattern>:
486 FR<0x1c, func, (outs CPURegs:$dst), (ins CPURegs:$src),
487 !strconcat(instr_asm, "\t$dst, $src"), pattern, IIAlu>,
488 Requires<[HasBitCount]> {
493 // Sign Extend in Register.
494 class SignExtInReg<bits<6> func, string instr_asm, ValueType vt>:
495 FR<0x3f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
496 !strconcat(instr_asm, "\t$dst, $src"),
497 [(set CPURegs:$dst, (sext_inreg CPURegs:$src, vt))], NoItinerary>;
500 class ByteSwap<bits<6> func, string instr_asm>:
501 FR<0x1f, func, (outs CPURegs:$dst), (ins CPURegs:$src),
502 !strconcat(instr_asm, "\t$dst, $src"),
503 [(set CPURegs:$dst, (bswap CPURegs:$src))], NoItinerary>;
506 class CondMov<bits<6> func, string instr_asm, PatLeaf MovCode>:
507 FR<0x00, func, (outs CPURegs:$dst), (ins CPURegs:$F, CPURegs:$T,
508 CPURegs:$cond), !strconcat(instr_asm, "\t$dst, $T, $cond"),
512 class ReadHardware: FR<0x1f, 0x3b, (outs CPURegs:$dst), (ins HWRegs:$src),
513 "rdhwr\t$dst, $src", [], IIAlu> {
519 class ExtIns<bits<6> _funct, string instr_asm, dag outs, dag ins,
520 list<dag> pattern, InstrItinClass itin>:
521 FR<0x1f, _funct, outs, ins, !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
522 pattern, itin>, Requires<[HasMips32r2]> {
529 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
530 class Atomic2Ops<PatFrag Op, string Opstr> :
531 MipsPseudo<(outs CPURegs:$dst), (ins CPURegs:$ptr, CPURegs:$incr),
532 !strconcat("atomic_", Opstr, "\t$dst, $ptr, $incr"),
534 (Op CPURegs:$ptr, CPURegs:$incr))]>;
536 // Atomic Compare & Swap.
537 class AtomicCmpSwap<PatFrag Op, string Width> :
538 MipsPseudo<(outs CPURegs:$dst),
539 (ins CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap),
540 !strconcat("atomic_cmp_swap_", Width,
541 "\t$dst, $ptr, $cmp, $swap"),
543 (Op CPURegs:$ptr, CPURegs:$cmp, CPURegs:$swap))]>;
545 //===----------------------------------------------------------------------===//
546 // Pseudo instructions
547 //===----------------------------------------------------------------------===//
549 // As stack alignment is always done with addiu, we need a 16-bit immediate
550 let Defs = [SP], Uses = [SP] in {
551 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins uimm16:$amt),
552 "!ADJCALLSTACKDOWN $amt",
553 [(callseq_start timm:$amt)]>;
554 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins uimm16:$amt1, uimm16:$amt2),
555 "!ADJCALLSTACKUP $amt1",
556 [(callseq_end timm:$amt1, timm:$amt2)]>;
559 // Some assembly macros need to avoid pseudoinstructions and assembler
560 // automatic reodering, we should reorder ourselves.
561 def MACRO : MipsPseudo<(outs), (ins), ".set\tmacro", []>;
562 def REORDER : MipsPseudo<(outs), (ins), ".set\treorder", []>;
563 def NOMACRO : MipsPseudo<(outs), (ins), ".set\tnomacro", []>;
564 def NOREORDER : MipsPseudo<(outs), (ins), ".set\tnoreorder", []>;
566 // These macros are inserted to prevent GAS from complaining
567 // when using the AT register.
568 def NOAT : MipsPseudo<(outs), (ins), ".set\tnoat", []>;
569 def ATMACRO : MipsPseudo<(outs), (ins), ".set\tat", []>;
571 // When handling PIC code the assembler needs .cpload and .cprestore
572 // directives. If the real instructions corresponding these directives
573 // are used, we have the same behavior, but get also a bunch of warnings
574 // from the assembler.
575 def CPLOAD : MipsPseudo<(outs), (ins CPURegs:$picreg), ".cpload\t$picreg", []>;
576 def CPRESTORE : MipsPseudo<(outs), (ins i32imm:$loc), ".cprestore\t$loc", []>;
578 let usesCustomInserter = 1 in {
579 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, "load_add_8">;
580 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, "load_add_16">;
581 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, "load_add_32">;
582 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, "load_sub_8">;
583 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, "load_sub_16">;
584 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, "load_sub_32">;
585 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, "load_and_8">;
586 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, "load_and_16">;
587 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, "load_and_32">;
588 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, "load_or_8">;
589 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, "load_or_16">;
590 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, "load_or_32">;
591 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, "load_xor_8">;
592 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, "load_xor_16">;
593 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, "load_xor_32">;
594 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, "load_nand_8">;
595 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, "load_nand_16">;
596 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, "load_nand_32">;
598 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, "swap_8">;
599 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, "swap_16">;
600 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, "swap_32">;
602 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, "8">;
603 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, "16">;
604 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, "32">;
607 //===----------------------------------------------------------------------===//
608 // Instruction definition
609 //===----------------------------------------------------------------------===//
611 //===----------------------------------------------------------------------===//
612 // MipsI Instructions
613 //===----------------------------------------------------------------------===//
615 /// Arithmetic Instructions (ALU Immediate)
616 def ADDiu : ArithI<0x09, "addiu", add, simm16, immSExt16>;
617 def ADDi : ArithOverflowI<0x08, "addi", add, simm16, immSExt16>;
618 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
619 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
620 def ANDi : LogicI<0x0c, "andi", and>;
621 def ORi : LogicI<0x0d, "ori", or>;
622 def XORi : LogicI<0x0e, "xori", xor>;
623 def LUi : LoadUpper<0x0f, "lui">;
625 /// Arithmetic Instructions (3-Operand, R-Type)
626 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu, 1>;
627 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
628 def ADD : ArithOverflowR<0x00, 0x20, "add", 1>;
629 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
630 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
631 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
632 def AND : LogicR<0x24, "and", and>;
633 def OR : LogicR<0x25, "or", or>;
634 def XOR : LogicR<0x26, "xor", xor>;
635 def NOR : LogicNOR<0x00, 0x27, "nor">;
637 /// Shift Instructions
638 def SLL : LogicR_shift_rotate_imm<0x00, 0x00, "sll", shl>;
639 def SRL : LogicR_shift_rotate_imm<0x02, 0x00, "srl", srl>;
640 def SRA : LogicR_shift_rotate_imm<0x03, 0x00, "sra", sra>;
641 def SLLV : LogicR_shift_rotate_reg<0x04, 0x00, "sllv", shl>;
642 def SRLV : LogicR_shift_rotate_reg<0x06, 0x00, "srlv", srl>;
643 def SRAV : LogicR_shift_rotate_reg<0x07, 0x00, "srav", sra>;
645 // Rotate Instructions
646 let Predicates = [HasMips32r2] in {
647 def ROTR : LogicR_shift_rotate_imm<0x02, 0x01, "rotr", rotr>;
648 def ROTRV : LogicR_shift_rotate_reg<0x06, 0x01, "rotrv", rotr>;
651 /// Load and Store Instructions
653 defm LB : LoadM32<0x20, "lb", sextloadi8>;
654 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
655 defm LH : LoadM32<0x21, "lh", sextloadi16_a>;
656 defm LHu : LoadM32<0x25, "lhu", zextloadi16_a>;
657 defm LW : LoadM32<0x23, "lw", load_a>;
658 defm SB : StoreM32<0x28, "sb", truncstorei8>;
659 defm SH : StoreM32<0x29, "sh", truncstorei16_a>;
660 defm SW : StoreM32<0x2b, "sw", store_a>;
663 defm ULH : LoadM32<0x21, "ulh", sextloadi16_u, 1>;
664 defm ULHu : LoadM32<0x25, "ulhu", zextloadi16_u, 1>;
665 defm ULW : LoadM32<0x23, "ulw", load_u, 1>;
666 defm USH : StoreM32<0x29, "ush", truncstorei16_u, 1>;
667 defm USW : StoreM32<0x2b, "usw", store_u, 1>;
669 let hasSideEffects = 1 in
670 def SYNC : MipsInst<(outs), (ins i32imm:$stype), "sync $stype",
671 [(MipsSync imm:$stype)], NoItinerary>
678 /// Load-linked, Store-conditional
680 def LL : FI<0x30, (outs CPURegs:$dst), (ins mem:$addr),
681 "ll\t$dst, $addr", [], IILoad>;
682 let mayStore = 1, Constraints = "$src = $dst" in
683 def SC : FI<0x38, (outs CPURegs:$dst), (ins CPURegs:$src, mem:$addr),
684 "sc\t$src, $addr", [], IIStore>;
686 /// Jump and Branch Instructions
687 def J : JumpFJ<0x02, "j">;
688 let isIndirectBranch = 1 in
689 def JR : JumpFR<0x00, 0x08, "jr">;
690 def JAL : JumpLink<0x03, "jal">;
691 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
692 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
693 def BNE : CBranch<0x05, "bne", setne, CPURegs>;
694 def BGEZ : CBranchZero<0x01, 1, "bgez", setge, CPURegs>;
695 def BGTZ : CBranchZero<0x07, 0, "bgtz", setgt, CPURegs>;
696 def BLEZ : CBranchZero<0x07, 0, "blez", setle, CPURegs>;
697 def BLTZ : CBranchZero<0x01, 0, "bltz", setlt, CPURegs>;
699 def BGEZAL : BranchLink<"bgezal">;
700 def BLTZAL : BranchLink<"bltzal">;
702 let isReturn=1, isTerminator=1, hasDelaySlot=1,
703 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
704 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
705 "jr\t$target", [(MipsRet CPURegs:$target)], IIBranch>;
707 /// Multiply and Divide Instructions.
708 def MULT : Mul<0x18, "mult", IIImul>;
709 def MULTu : Mul<0x19, "multu", IIImul>;
710 def SDIV : Div<MipsDivRem, 0x1a, "div", IIIdiv>;
711 def UDIV : Div<MipsDivRemU, 0x1b, "divu", IIIdiv>;
714 def MTHI : MoveToLOHI<0x11, "mthi">;
716 def MTLO : MoveToLOHI<0x13, "mtlo">;
719 def MFHI : MoveFromLOHI<0x10, "mfhi">;
721 def MFLO : MoveFromLOHI<0x12, "mflo">;
723 /// Sign Ext In Register Instructions.
724 let Predicates = [HasSEInReg] in {
725 let shamt = 0x10, rs = 0 in
726 def SEB : SignExtInReg<0x21, "seb", i8>;
728 let shamt = 0x18, rs = 0 in
729 def SEH : SignExtInReg<0x20, "seh", i16>;
733 def CLZ : CountLeading<0b100000, "clz",
734 [(set CPURegs:$dst, (ctlz CPURegs:$src))]>;
735 def CLO : CountLeading<0b100001, "clo",
736 [(set CPURegs:$dst, (ctlz (not CPURegs:$src)))]>;
739 let Predicates = [HasSwap] in {
740 let shamt = 0x3, rs = 0 in
741 def WSBW : ByteSwap<0x20, "wsbw">;
745 def MIPS_CMOV_ZERO : PatLeaf<(i32 0)>;
746 def MIPS_CMOV_NZERO : PatLeaf<(i32 1)>;
748 // Conditional moves:
749 // These instructions are expanded in
750 // MipsISelLowering::EmitInstrWithCustomInserter if target does not have
751 // conditional move instructions.
752 // flag:int, data:int
753 let usesCustomInserter = 1, shamt = 0, Constraints = "$F = $dst" in
754 class CondMovIntInt<bits<6> funct, string instr_asm> :
755 FR<0, funct, (outs CPURegs:$dst),
756 (ins CPURegs:$T, CPURegs:$cond, CPURegs:$F),
757 !strconcat(instr_asm, "\t$dst, $T, $cond"), [], NoItinerary>;
759 def MOVZ_I : CondMovIntInt<0x0a, "movz">;
760 def MOVN_I : CondMovIntInt<0x0b, "movn">;
764 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
766 // FrameIndexes are legalized when they are operands from load/store
767 // instructions. The same not happens for stack address copies, so an
768 // add op with mem ComplexPattern is used and the stack address copy
769 // can be matched. It's similar to Sparc LEA_ADDRi
770 def LEA_ADDiu : EffectiveAddress<"addiu\t$dst, $addr">;
772 // DynAlloc node points to dynamically allocated stack space.
773 // $sp is added to the list of implicitly used registers to prevent dead code
774 // elimination from removing instructions that modify $sp.
776 def DynAlloc : EffectiveAddress<"addiu\t$dst, $addr">;
779 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
780 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
781 def MSUB : MArithR<4, "msub", MipsMSub>;
782 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
784 // MUL is a assembly macro in the current used ISAs. In recent ISA's
785 // it is a real instruction.
786 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul, 1>, Requires<[HasMips32]>;
788 def RDHWR : ReadHardware;
790 def EXT : ExtIns<0, "ext", (outs CPURegs:$rt),
791 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz),
793 (MipsExt CPURegs:$rs, immZExt5:$pos, immZExt5:$sz))],
796 let Constraints = "$src = $rt" in
797 def INS : ExtIns<4, "ins", (outs CPURegs:$rt),
798 (ins CPURegs:$rs, uimm16:$pos, uimm16:$sz, CPURegs:$src),
800 (MipsIns CPURegs:$rs, immZExt5:$pos, immZExt5:$sz,
804 //===----------------------------------------------------------------------===//
805 // Arbitrary patterns that map to one or more instructions
806 //===----------------------------------------------------------------------===//
809 def : Pat<(i32 immSExt16:$in),
810 (ADDiu ZERO, imm:$in)>;
811 def : Pat<(i32 immZExt16:$in),
812 (ORi ZERO, imm:$in)>;
814 // Arbitrary immediates
815 def : Pat<(i32 imm:$imm),
816 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
819 def : Pat<(subc CPURegs:$lhs, CPURegs:$rhs),
820 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
821 def : Pat<(addc CPURegs:$lhs, CPURegs:$rhs),
822 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
823 def : Pat<(addc CPURegs:$src, immSExt16:$imm),
824 (ADDiu CPURegs:$src, imm:$imm)>;
827 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
828 (JAL tglobaladdr:$dst)>;
829 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
830 (JAL texternalsym:$dst)>;
831 //def : Pat<(MipsJmpLink CPURegs:$dst),
832 // (JALR CPURegs:$dst)>;
835 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
836 def : Pat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
837 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
838 def : Pat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
839 def : Pat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
840 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
841 def : Pat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
842 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
844 def : Pat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
845 def : Pat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
846 def : Pat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
847 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
849 def : Pat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
850 def : Pat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
851 def : Pat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
852 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
855 def : Pat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
856 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
857 def : Pat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
858 (ADDiu CPURegs:$gp, tconstpool:$in)>;
861 def : Pat<(add CPURegs:$gp, (MipsTlsGd tglobaltlsaddr:$in)),
862 (ADDiu CPURegs:$gp, tglobaltlsaddr:$in)>;
865 def : Pat<(MipsTprelHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
866 def : Pat<(MipsTprelLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
867 def : Pat<(add CPURegs:$hi, (MipsTprelLo tglobaltlsaddr:$lo)),
868 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
871 class WrapperPICPat<SDNode node>:
872 Pat<(MipsWrapperPIC node:$in),
873 (ADDiu GP, node:$in)>;
875 def : WrapperPICPat<tglobaladdr>;
876 def : WrapperPICPat<tconstpool>;
877 def : WrapperPICPat<texternalsym>;
878 def : WrapperPICPat<tblockaddress>;
879 def : WrapperPICPat<tjumptable>;
881 // Mips does not have "not", so we expand our way
882 def : Pat<(not CPURegs:$in),
883 (NOR CPURegs:$in, ZERO)>;
885 // extended load and stores
886 def : Pat<(extloadi1 addr:$src), (LBu addr:$src)>;
887 def : Pat<(extloadi8 addr:$src), (LBu addr:$src)>;
888 def : Pat<(extloadi16_a addr:$src), (LHu addr:$src)>;
889 def : Pat<(extloadi16_u addr:$src), (ULHu addr:$src)>;
892 def : Pat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
895 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
896 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
897 Instruction SLTiuOp, Register ZEROReg> {
898 def : Pat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
899 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
900 def : Pat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
901 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
903 def : Pat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
904 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
905 def : Pat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
906 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
907 def : Pat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
908 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
909 def : Pat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
910 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
912 def : Pat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
913 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
914 def : Pat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
915 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
917 def : Pat<(brcond RC:$cond, bb:$dst),
918 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
921 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
924 multiclass MovzPats<RegisterClass RC, Instruction MOVZInst> {
925 def : Pat<(select (i32 (setge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
926 (MOVZInst RC:$T, (SLT CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
927 def : Pat<(select (i32 (setuge CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
928 (MOVZInst RC:$T, (SLTu CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
929 def : Pat<(select (i32 (setge CPURegs:$lhs, immSExt16:$rhs)), RC:$T, RC:$F),
930 (MOVZInst RC:$T, (SLTi CPURegs:$lhs, immSExt16:$rhs), RC:$F)>;
931 def : Pat<(select (i32 (setuge CPURegs:$lh, immSExt16:$rh)), RC:$T, RC:$F),
932 (MOVZInst RC:$T, (SLTiu CPURegs:$lh, immSExt16:$rh), RC:$F)>;
933 def : Pat<(select (i32 (setle CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
934 (MOVZInst RC:$T, (SLT CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
935 def : Pat<(select (i32 (setule CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
936 (MOVZInst RC:$T, (SLTu CPURegs:$rhs, CPURegs:$lhs), RC:$F)>;
937 def : Pat<(select (i32 (seteq CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
938 (MOVZInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
939 def : Pat<(select (i32 (seteq CPURegs:$lhs, 0)), RC:$T, RC:$F),
940 (MOVZInst RC:$T, CPURegs:$lhs, RC:$F)>;
943 multiclass MovnPats<RegisterClass RC, Instruction MOVNInst> {
944 def : Pat<(select (i32 (setne CPURegs:$lhs, CPURegs:$rhs)), RC:$T, RC:$F),
945 (MOVNInst RC:$T, (XOR CPURegs:$lhs, CPURegs:$rhs), RC:$F)>;
946 def : Pat<(select CPURegs:$cond, RC:$T, RC:$F),
947 (MOVNInst RC:$T, CPURegs:$cond, RC:$F)>;
948 def : Pat<(select (i32 (setne CPURegs:$lhs, 0)), RC:$T, RC:$F),
949 (MOVNInst RC:$T, CPURegs:$lhs, RC:$F)>;
952 defm : MovzPats<CPURegs, MOVZ_I>;
953 defm : MovnPats<CPURegs, MOVN_I>;
956 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
957 (SLTiu (XOR CPURegs:$lhs, CPURegs:$rhs), 1)>;
958 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
959 (SLTu ZERO, (XOR CPURegs:$lhs, CPURegs:$rhs))>;
961 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
962 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
963 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
964 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
966 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
967 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
968 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
969 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
971 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
972 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
973 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
974 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
976 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
977 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
978 def : Pat<(setuge CPURegs:$lhs, immSExt16:$rhs),
979 (XORi (SLTiu CPURegs:$lhs, immSExt16:$rhs), 1)>;
981 // select MipsDynAlloc
982 def : Pat<(MipsDynAlloc addr:$f), (DynAlloc addr:$f)>;
984 //===----------------------------------------------------------------------===//
985 // Floating Point Support
986 //===----------------------------------------------------------------------===//
988 include "MipsInstrFPU.td"
989 include "Mips64InstrInfo.td"