1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPSideEffect,
83 SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
88 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
89 [SDNPOptInGlue, SDNPOutGlue]>;
90 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
91 [SDNPOptInGlue, SDNPOutGlue]>;
92 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
93 [SDNPOptInGlue, SDNPOutGlue]>;
96 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
98 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
101 // Target constant nodes that are not part of any isel patterns and remain
102 // unchanged can cause instructions with illegal operands to be emitted.
103 // Wrapper node patterns give the instruction selector a chance to replace
104 // target constant nodes that would otherwise remain unchanged with ADDiu
105 // nodes. Without these wrapper node patterns, the following conditional move
106 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
108 // movn %got(d)($gp), %got(c)($gp), $4
109 // This instruction is illegal since movn can take only register operands.
111 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
113 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
115 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
116 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
118 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
120 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
124 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
126 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
128 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
132 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 //===----------------------------------------------------------------------===//
136 // Mips Instruction Predicate Definitions.
137 //===----------------------------------------------------------------------===//
138 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
139 AssemblerPredicate<"FeatureSEInReg">;
140 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
141 AssemblerPredicate<"FeatureBitCount">;
142 def HasSwap : Predicate<"Subtarget.hasSwap()">,
143 AssemblerPredicate<"FeatureSwap">;
144 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
145 AssemblerPredicate<"FeatureCondMov">;
146 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
147 AssemblerPredicate<"FeatureFPIdx">;
148 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
149 AssemblerPredicate<"FeatureMips32">;
150 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
151 AssemblerPredicate<"FeatureMips32r2">;
152 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
153 AssemblerPredicate<"FeatureMips64">;
154 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
155 AssemblerPredicate<"!FeatureMips64">;
156 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
157 AssemblerPredicate<"FeatureMips64r2">;
158 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
159 AssemblerPredicate<"FeatureN64">;
160 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
161 AssemblerPredicate<"!FeatureN64">;
162 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
163 AssemblerPredicate<"FeatureMips16">;
164 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
165 AssemblerPredicate<"FeatureMips32">;
166 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
167 AssemblerPredicate<"FeatureMips32">;
168 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
169 AssemblerPredicate<"FeatureMips32">;
170 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
171 AssemblerPredicate<"!FeatureMips16">;
173 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
174 let Predicates = [HasStdEnc];
178 bit isCommutable = 1;
195 bit isTerminator = 1;
198 bit hasExtraSrcRegAllocReq = 1;
199 bit isCodeGenOnly = 1;
202 class IsAsCheapAsAMove {
203 bit isAsCheapAsAMove = 1;
206 class NeverHasSideEffects {
207 bit neverHasSideEffects = 1;
210 //===----------------------------------------------------------------------===//
211 // Instruction format superclass
212 //===----------------------------------------------------------------------===//
214 include "MipsInstrFormats.td"
216 //===----------------------------------------------------------------------===//
217 // Mips Operand, Complex Patterns and Transformations Definitions.
218 //===----------------------------------------------------------------------===//
220 // Instruction operand types
221 def jmptarget : Operand<OtherVT> {
222 let EncoderMethod = "getJumpTargetOpValue";
224 def brtarget : Operand<OtherVT> {
225 let EncoderMethod = "getBranchTargetOpValue";
226 let OperandType = "OPERAND_PCREL";
227 let DecoderMethod = "DecodeBranchTarget";
229 def calltarget : Operand<iPTR> {
230 let EncoderMethod = "getJumpTargetOpValue";
232 def calltarget64: Operand<i64>;
233 def simm16 : Operand<i32> {
234 let DecoderMethod= "DecodeSimm16";
237 def simm20 : Operand<i32> {
240 def simm16_64 : Operand<i64>;
241 def shamt : Operand<i32>;
244 def uimm16 : Operand<i32> {
245 let PrintMethod = "printUnsignedImm";
248 def MipsMemAsmOperand : AsmOperandClass {
250 let ParserMethod = "parseMemOperand";
254 def mem : Operand<i32> {
255 let PrintMethod = "printMemOperand";
256 let MIOperandInfo = (ops CPURegs, simm16);
257 let EncoderMethod = "getMemEncoding";
258 let ParserMatchClass = MipsMemAsmOperand;
261 def mem64 : Operand<i64> {
262 let PrintMethod = "printMemOperand";
263 let MIOperandInfo = (ops CPU64Regs, simm16_64);
264 let EncoderMethod = "getMemEncoding";
265 let ParserMatchClass = MipsMemAsmOperand;
268 def mem_ea : Operand<i32> {
269 let PrintMethod = "printMemOperandEA";
270 let MIOperandInfo = (ops CPURegs, simm16);
271 let EncoderMethod = "getMemEncoding";
274 def mem_ea_64 : Operand<i64> {
275 let PrintMethod = "printMemOperandEA";
276 let MIOperandInfo = (ops CPU64Regs, simm16_64);
277 let EncoderMethod = "getMemEncoding";
280 // size operand of ext instruction
281 def size_ext : Operand<i32> {
282 let EncoderMethod = "getSizeExtEncoding";
283 let DecoderMethod = "DecodeExtSize";
286 // size operand of ins instruction
287 def size_ins : Operand<i32> {
288 let EncoderMethod = "getSizeInsEncoding";
289 let DecoderMethod = "DecodeInsSize";
292 // Transformation Function - get the lower 16 bits.
293 def LO16 : SDNodeXForm<imm, [{
294 return getImm(N, N->getZExtValue() & 0xFFFF);
297 // Transformation Function - get the higher 16 bits.
298 def HI16 : SDNodeXForm<imm, [{
299 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
302 // Node immediate fits as 16-bit sign extended on target immediate.
304 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
306 // Node immediate fits as 16-bit sign extended on target immediate.
308 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
310 // Node immediate fits as 15-bit sign extended on target immediate.
312 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
314 // Node immediate fits as 16-bit zero extended on target immediate.
315 // The LO16 param means that only the lower 16 bits of the node
316 // immediate are caught.
318 def immZExt16 : PatLeaf<(imm), [{
319 if (N->getValueType(0) == MVT::i32)
320 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
322 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
325 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
326 def immLow16Zero : PatLeaf<(imm), [{
327 int64_t Val = N->getSExtValue();
328 return isInt<32>(Val) && !(Val & 0xffff);
331 // shamt field must fit in 5 bits.
332 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
334 // Mips Address Mode! SDNode frameindex could possibily be a match
335 // since load and store instructions from stack used it.
337 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
339 //===----------------------------------------------------------------------===//
340 // Instructions specific format
341 //===----------------------------------------------------------------------===//
343 // Arithmetic and logical instructions with 3 register operands.
344 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
345 InstrItinClass Itin = NoItinerary,
346 SDPatternOperator OpNode = null_frag>:
347 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
348 !strconcat(opstr, "\t$rd, $rs, $rt"),
349 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
350 let isCommutable = isComm;
351 let isReMaterializable = 1;
356 // Arithmetic and logical instructions with 2 register operands.
357 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
358 SDPatternOperator imm_type = null_frag,
359 SDPatternOperator OpNode = null_frag> :
360 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
361 !strconcat(opstr, "\t$rt, $rs, $imm16"),
362 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> {
363 let isReMaterializable = 1;
366 // Arithmetic Multiply ADD/SUB
367 class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
368 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
369 !strconcat(opstr, "\t$rs, $rt"),
370 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> {
373 let isCommutable = isComm;
377 class LogicNOR<string opstr, RegisterOperand RC>:
378 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
379 !strconcat(opstr, "\t$rd, $rs, $rt"),
380 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
381 let isCommutable = 1;
385 class shift_rotate_imm<string opstr, Operand ImmOpnd,
386 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
387 SDPatternOperator PF = null_frag> :
388 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
389 !strconcat(opstr, "\t$rd, $rt, $shamt"),
390 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
392 class shift_rotate_reg<string opstr, RegisterOperand RC,
393 SDPatternOperator OpNode = null_frag>:
394 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
395 !strconcat(opstr, "\t$rd, $rt, $rs"),
396 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>;
398 // Load Upper Imediate
399 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
400 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
401 [], IIAlu, FrmI>, IsAsCheapAsAMove {
402 let neverHasSideEffects = 1;
403 let isReMaterializable = 1;
406 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
407 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
409 let Inst{25-21} = addr{20-16};
410 let Inst{15-0} = addr{15-0};
411 let DecoderMethod = "DecodeMem";
415 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
417 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
418 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
419 let DecoderMethod = "DecodeMem";
420 let canFoldAsLoad = 1;
423 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
425 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
426 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
427 let DecoderMethod = "DecodeMem";
430 multiclass LoadM<string opstr, RegisterClass RC,
431 SDPatternOperator OpNode = null_frag> {
432 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
433 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
434 let DecoderNamespace = "Mips64";
435 let isCodeGenOnly = 1;
439 multiclass StoreM<string opstr, RegisterClass RC,
440 SDPatternOperator OpNode = null_frag> {
441 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
442 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
443 let DecoderNamespace = "Mips64";
444 let isCodeGenOnly = 1;
448 // Load/Store Left/Right
449 let canFoldAsLoad = 1 in
450 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
452 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
453 !strconcat(opstr, "\t$rt, $addr"),
454 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
455 let DecoderMethod = "DecodeMem";
456 string Constraints = "$src = $rt";
459 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
461 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
462 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
463 let DecoderMethod = "DecodeMem";
466 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
467 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
468 Requires<[NotN64, HasStdEnc]>;
469 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
470 Requires<[IsN64, HasStdEnc]> {
471 let DecoderNamespace = "Mips64";
472 let isCodeGenOnly = 1;
476 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
477 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
478 Requires<[NotN64, HasStdEnc]>;
479 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
480 Requires<[IsN64, HasStdEnc]> {
481 let DecoderNamespace = "Mips64";
482 let isCodeGenOnly = 1;
486 // Conditional Branch
487 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
488 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
489 !strconcat(opstr, "\t$rs, $rt, $offset"),
490 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
493 let isTerminator = 1;
494 let hasDelaySlot = 1;
498 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
499 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
500 !strconcat(opstr, "\t$rs, $offset"),
501 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
503 let isTerminator = 1;
504 let hasDelaySlot = 1;
509 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
510 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
511 !strconcat(opstr, "\t$rd, $rs, $rt"),
512 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
514 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
516 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
517 !strconcat(opstr, "\t$rt, $rs, $imm16"),
518 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
522 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
523 SDPatternOperator targetoperator> :
524 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
525 [(operator targetoperator:$target)], IIBranch, FrmJ> {
528 let hasDelaySlot = 1;
529 let DecoderMethod = "DecodeJumpTarget";
533 // Unconditional branch
534 class UncondBranch<string opstr> :
535 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
536 [(br bb:$offset)], IIBranch, FrmI> {
538 let isTerminator = 1;
540 let hasDelaySlot = 1;
541 let Predicates = [RelocPIC, HasStdEnc];
545 // Base class for indirect branch and return instruction classes.
546 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
547 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
548 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
551 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
553 let isIndirectBranch = 1;
556 // Return instruction
557 class RetBase<RegisterClass RC>: JumpFR<RC> {
559 let isCodeGenOnly = 1;
561 let hasExtraSrcRegAllocReq = 1;
564 // Jump and Link (Call)
565 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
566 class JumpLink<string opstr> :
567 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
568 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
569 let DecoderMethod = "DecodeJumpTarget";
572 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
574 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
575 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
577 class JumpLinkReg<string opstr, RegisterClass RC>:
578 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
581 class BGEZAL_FT<string opstr, RegisterOperand RO> :
582 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
583 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
588 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
590 let isTerminator = 1;
592 let hasDelaySlot = 1;
597 let hasSideEffects = 1 in
599 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
600 NoItinerary, FrmOther>;
603 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
604 list<Register> DefRegs> :
605 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
607 let isCommutable = 1;
609 let neverHasSideEffects = 1;
612 class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO,
613 list<Register> DefRegs> :
614 InstSE<(outs), (ins RO:$rs, RO:$rt),
615 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin,
621 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
622 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
624 let neverHasSideEffects = 1;
627 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
628 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
630 let neverHasSideEffects = 1;
633 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
634 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
635 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
636 let isCodeGenOnly = 1;
637 let DecoderMethod = "DecodeMem";
640 // Count Leading Ones/Zeros in Word
641 class CountLeading0<string opstr, RegisterOperand RO>:
642 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
643 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
644 Requires<[HasBitCount, HasStdEnc]>;
646 class CountLeading1<string opstr, RegisterOperand RO>:
647 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
648 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
649 Requires<[HasBitCount, HasStdEnc]>;
652 // Sign Extend in Register.
653 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
654 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
655 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
656 let Predicates = [HasSEInReg, HasStdEnc];
660 class SubwordSwap<string opstr, RegisterOperand RO>:
661 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
663 let Predicates = [HasSwap, HasStdEnc];
664 let neverHasSideEffects = 1;
668 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
669 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
673 class ExtBase<string opstr, RegisterOperand RO>:
674 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
675 !strconcat(opstr, " $rt, $rs, $pos, $size"),
676 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
678 let Predicates = [HasMips32r2, HasStdEnc];
681 class InsBase<string opstr, RegisterOperand RO>:
682 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
683 !strconcat(opstr, " $rt, $rs, $pos, $size"),
684 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
686 let Predicates = [HasMips32r2, HasStdEnc];
687 let Constraints = "$src = $rt";
690 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
691 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
692 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
693 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
695 multiclass Atomic2Ops32<PatFrag Op> {
696 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
697 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
698 Requires<[IsN64, HasStdEnc]> {
699 let DecoderNamespace = "Mips64";
703 // Atomic Compare & Swap.
704 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
705 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
706 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
708 multiclass AtomicCmpSwap32<PatFrag Op> {
709 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
710 Requires<[NotN64, HasStdEnc]>;
711 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
712 Requires<[IsN64, HasStdEnc]> {
713 let DecoderNamespace = "Mips64";
717 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
718 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
719 [], NoItinerary, FrmI> {
720 let DecoderMethod = "DecodeMem";
724 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
725 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
726 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
727 let DecoderMethod = "DecodeMem";
729 let Constraints = "$rt = $dst";
732 class MFC3OP<dag outs, dag ins, string asmstr> :
733 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
735 //===----------------------------------------------------------------------===//
736 // Pseudo instructions
737 //===----------------------------------------------------------------------===//
740 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
741 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
743 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
744 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
745 [(callseq_start timm:$amt)]>;
746 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
747 [(callseq_end timm:$amt1, timm:$amt2)]>;
750 let usesCustomInserter = 1 in {
751 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
752 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
753 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
754 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
755 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
756 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
757 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
758 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
759 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
760 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
761 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
762 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
763 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
764 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
765 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
766 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
767 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
768 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
770 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
771 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
772 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
774 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
775 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
776 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
779 //===----------------------------------------------------------------------===//
780 // Instruction definition
781 //===----------------------------------------------------------------------===//
782 //===----------------------------------------------------------------------===//
783 // MipsI Instructions
784 //===----------------------------------------------------------------------===//
786 /// Arithmetic Instructions (ALU Immediate)
787 def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
788 ADDI_FM<0x9>, IsAsCheapAsAMove;
789 def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
790 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
791 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
792 def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
794 def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
796 def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
798 def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
800 /// Arithmetic Instructions (3-Operand, R-Type)
801 def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>;
802 def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
803 def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
804 def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
805 def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
806 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
807 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
808 def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
809 def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
810 def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
811 def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
813 /// Shift Instructions
814 def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
816 def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
818 def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
820 def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
821 def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
822 def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
824 // Rotate Instructions
825 let Predicates = [HasMips32r2, HasStdEnc] in {
826 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>,
828 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>;
831 /// Load and Store Instructions
833 defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
834 defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
835 defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
836 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
837 defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
838 defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
839 defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
840 defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
842 /// load/store left/right
843 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
844 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
845 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
846 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
848 def SYNC : SYNC_FT, SYNC_FM;
850 /// Load-linked, Store-conditional
851 let Predicates = [NotN64, HasStdEnc] in {
852 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
853 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
856 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
857 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
858 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
861 /// Jump and Branch Instructions
862 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
863 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
864 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
865 def B : UncondBranch<"b">, B_FM;
866 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
867 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
868 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
869 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
870 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
871 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
873 def BAL_BR: BAL_FT, BAL_FM;
875 def JAL : JumpLink<"jal">, FJ<3>;
876 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
877 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
878 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
879 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
880 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
881 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
883 def RET : RetBase<CPURegs>, MTLO_FM<8>;
885 // Exception handling related node and instructions.
886 // The conversion sequence is:
887 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
888 // MIPSeh_return -> (stack change + indirect branch)
890 // MIPSeh_return takes the place of regular return instruction
891 // but takes two arguments (V1, V0) which are used for storing
892 // the offset and return address respectively.
893 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
895 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
896 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
898 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
899 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
900 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
901 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
903 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
906 /// Multiply and Divide Instructions.
907 def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
908 def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
909 def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>,
911 def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
914 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
915 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
916 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
917 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
919 /// Sign Ext In Register Instructions.
920 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
921 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
924 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
925 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
927 /// Word Swap Bytes Within Halfwords
928 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
931 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
933 // FrameIndexes are legalized when they are operands from load/store
934 // instructions. The same not happens for stack address copies, so an
935 // add op with mem ComplexPattern is used and the stack address copy
936 // can be matched. It's similar to Sparc LEA_ADDRi
937 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
940 def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>;
941 def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>;
942 def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>;
943 def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>;
945 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
947 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
948 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
950 /// Move Control Registers From/To CPU Registers
951 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
952 (ins CPURegsOpnd:$rd, uimm16:$sel),
953 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
955 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
956 (ins CPURegsOpnd:$rt),
957 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
959 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
960 (ins CPURegsOpnd:$rd, uimm16:$sel),
961 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
963 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
964 (ins CPURegsOpnd:$rt),
965 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
967 //===----------------------------------------------------------------------===//
968 // Instruction aliases
969 //===----------------------------------------------------------------------===//
970 def : InstAlias<"move $dst, $src",
971 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
972 Requires<[NotMips64]>;
973 def : InstAlias<"move $dst, $src",
974 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>,
975 Requires<[NotMips64]>;
976 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
977 def : InstAlias<"addu $rs, $rt, $imm",
978 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
979 def : InstAlias<"add $rs, $rt, $imm",
980 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
981 def : InstAlias<"and $rs, $rt, $imm",
982 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
983 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
984 Requires<[NotMips64]>;
985 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
986 def : InstAlias<"not $rt, $rs",
987 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
988 def : InstAlias<"neg $rt, $rs",
989 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
990 def : InstAlias<"negu $rt, $rs",
991 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
992 def : InstAlias<"slt $rs, $rt, $imm",
993 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
994 def : InstAlias<"xor $rs, $rt, $imm",
995 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
996 Requires<[NotMips64]>;
997 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
998 def : InstAlias<"mfc0 $rt, $rd",
999 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1000 def : InstAlias<"mtc0 $rt, $rd",
1001 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1002 def : InstAlias<"mfc2 $rt, $rd",
1003 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1004 def : InstAlias<"mtc2 $rt, $rd",
1005 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1007 //===----------------------------------------------------------------------===//
1008 // Assembler Pseudo Instructions
1009 //===----------------------------------------------------------------------===//
1011 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1012 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1013 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1014 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1016 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1017 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1018 !strconcat(instr_asm, "\t$rt, $addr")> ;
1019 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1021 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1022 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1023 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1024 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1028 //===----------------------------------------------------------------------===//
1029 // Arbitrary patterns that map to one or more instructions
1030 //===----------------------------------------------------------------------===//
1033 def : MipsPat<(i32 immSExt16:$in),
1034 (ADDiu ZERO, imm:$in)>;
1035 def : MipsPat<(i32 immZExt16:$in),
1036 (ORi ZERO, imm:$in)>;
1037 def : MipsPat<(i32 immLow16Zero:$in),
1038 (LUi (HI16 imm:$in))>;
1040 // Arbitrary immediates
1041 def : MipsPat<(i32 imm:$imm),
1042 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1044 // Carry MipsPatterns
1045 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1046 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1047 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1048 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1049 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1050 (ADDiu CPURegs:$src, imm:$imm)>;
1053 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1054 (JAL tglobaladdr:$dst)>;
1055 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1056 (JAL texternalsym:$dst)>;
1057 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1058 // (JALR CPURegs:$dst)>;
1061 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1062 (TAILCALL tglobaladdr:$dst)>;
1063 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1064 (TAILCALL texternalsym:$dst)>;
1066 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1067 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1068 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1069 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1070 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1071 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1073 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1074 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1075 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1076 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1077 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1078 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1080 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1081 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1082 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1083 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1084 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1085 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1086 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1087 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1088 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1089 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1092 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1093 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1094 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1095 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1098 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1099 MipsPat<(MipsWrapper RC:$gp, node:$in),
1100 (ADDiuOp RC:$gp, node:$in)>;
1102 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1103 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1104 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1105 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1106 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1107 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1109 // Mips does not have "not", so we expand our way
1110 def : MipsPat<(not CPURegs:$in),
1111 (NOR CPURegsOpnd:$in, ZERO)>;
1114 let Predicates = [NotN64, HasStdEnc] in {
1115 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1116 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1117 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1119 let Predicates = [IsN64, HasStdEnc] in {
1120 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1121 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1122 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1126 let Predicates = [NotN64, HasStdEnc] in {
1127 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1129 let Predicates = [IsN64, HasStdEnc] in {
1130 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1134 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1135 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1136 Instruction SLTiuOp, Register ZEROReg> {
1137 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1138 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1139 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1140 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1142 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1143 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1144 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1145 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1146 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1147 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1148 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1149 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1151 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1152 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1153 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1154 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1156 def : MipsPat<(brcond RC:$cond, bb:$dst),
1157 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1160 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1163 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1164 Instruction SLTuOp, Register ZEROReg> {
1165 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1166 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1167 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1168 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1171 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1172 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1173 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1174 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1175 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1178 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1179 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1180 (SLTOp RC:$rhs, RC:$lhs)>;
1181 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1182 (SLTuOp RC:$rhs, RC:$lhs)>;
1185 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1186 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1187 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1188 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1189 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1192 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1193 Instruction SLTiuOp> {
1194 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1195 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1196 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1197 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1200 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1201 defm : SetlePats<CPURegs, SLT, SLTu>;
1202 defm : SetgtPats<CPURegs, SLT, SLTu>;
1203 defm : SetgePats<CPURegs, SLT, SLTu>;
1204 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1207 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1209 //===----------------------------------------------------------------------===//
1210 // Floating Point Support
1211 //===----------------------------------------------------------------------===//
1213 include "MipsInstrFPU.td"
1214 include "Mips64InstrInfo.td"
1215 include "MipsCondMov.td"
1220 include "Mips16InstrFormats.td"
1221 include "Mips16InstrInfo.td"
1224 include "MipsDSPInstrFormats.td"
1225 include "MipsDSPInstrInfo.td"