1 //===- MipsInstrInfo.td - Mips Register defs --------------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by Bruno Cardoso Lopes and is distributed under the
6 // University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Instruction format superclass
12 //===----------------------------------------------------------------------===//
14 include "MipsInstrFormats.td"
16 //===----------------------------------------------------------------------===//
17 // Mips profiles and nodes
18 //===----------------------------------------------------------------------===//
21 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
22 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink, [SDNPHasChain,
25 // Hi and Lo nodes are created to let easy manipulation of 16-bit when
26 // handling 32-bit immediates. They are used on MipsISelLowering to
27 // lower stuff like GlobalAddress, ExternalSymbol, ...
28 // This two nodes have nothing to do with Mips Registers Hi and Lo.
29 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp, [SDNPOutFlag]>;
30 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
32 // Necessary to generate glued instructions when loading GlobalAddress
34 def MipsAdd : SDNode<"MipsISD::Add", SDTIntBinOp, [SDNPCommutative,
35 SDNPAssociative, SDNPOptInFlag]>;
38 def SDT_MipsRet : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
39 def MipsRet : SDNode<"MipsISD::Ret", SDT_MipsRet, [SDNPHasChain,
42 // These are target-independent nodes, but have target-specific formats.
43 def SDT_MipsCallSeq : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
44 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeq,
45 [SDNPHasChain, SDNPOutFlag]>;
46 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeq,
47 [SDNPHasChain, SDNPOutFlag]>;
49 // Instruction operand types
50 def brtarget : Operand<OtherVT>;
51 def calltarget : Operand<i32>;
52 def uimm16 : Operand<i32>;
53 def simm16 : Operand<i32>;
54 def shamt : Operand<i32>;
57 def mem : Operand<i32> {
58 let PrintMethod = "printMemOperand";
59 let MIOperandInfo = (ops simm16, CPURegs);
62 //===----------------------------------------------------------------------===//
63 // Mips Patterns and Transformations
64 //===----------------------------------------------------------------------===//
66 // Transformation Function - get the lower 16 bits.
67 def LO16 : SDNodeXForm<imm, [{
68 return getI32Imm((unsigned)N->getValue() & 0xFFFF);
71 // Transformation Function - get the higher 16 bits.
72 def HI16 : SDNodeXForm<imm, [{
73 return getI32Imm((unsigned)N->getValue() >> 16);
76 // Node immediate fits as 16-bit sign extended on target immediate.
78 def immSExt16 : PatLeaf<(imm), [{
79 if (N->getValueType(0) == MVT::i32)
80 return (int32_t)N->getValue() == (short)N->getValue();
82 return (int64_t)N->getValue() == (short)N->getValue();
85 // Node immediate fits as 16-bit zero extended on target immediate.
86 // The LO16 param means that only the lower 16 bits of the node
87 // immediate are caught.
89 def immZExt16 : PatLeaf<(imm), [{
90 if (N->getValueType(0) == MVT::i32)
91 return (uint32_t)N->getValue() == (unsigned short)N->getValue();
93 return (uint64_t)N->getValue() == (unsigned short)N->getValue();
96 // Node immediate fits as 32-bit zero extended on target immediate.
97 //def immZExt32 : PatLeaf<(imm), [{
98 // return (uint64_t)N->getValue() == (uint32_t)N->getValue();
101 // shamt field must fit in 5 bits.
102 def immZExt5 : PatLeaf<(imm), [{
103 return N->getValue() == ((N->getValue()) & 0x1f) ;
106 // Mips Address Mode! SDNode frameindex could possibily be a match
107 // since load and store instructions from stack used it.
108 def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], []>;
110 //===----------------------------------------------------------------------===//
111 // Instructions specific format
112 //===----------------------------------------------------------------------===//
114 // Arithmetic 3 register operands
115 let isCommutable = 1 in
116 class ArithR<bits<6> op, bits<6> func, string instr_asm, SDNode OpNode,
117 InstrItinClass itin>:
121 (ins CPURegs:$b, CPURegs:$c),
122 !strconcat(instr_asm, " $dst, $b, $c"),
123 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], itin>;
125 let isCommutable = 1 in
126 class ArithOverflowR<bits<6> op, bits<6> func, string instr_asm>:
130 (ins CPURegs:$b, CPURegs:$c),
131 !strconcat(instr_asm, " $dst, $b, $c"),
134 // Arithmetic 2 register operands
135 let isCommutable = 1 in
136 class ArithI<bits<6> op, string instr_asm, SDNode OpNode,
137 Operand Od, PatLeaf imm_type> :
140 (ins CPURegs:$b, Od:$c),
141 !strconcat(instr_asm, " $dst, $b, $c"),
142 [(set CPURegs:$dst, (OpNode CPURegs:$b, imm_type:$c))], IIAlu>;
144 // Arithmetic Multiply ADD/SUB
146 class MArithR<bits<6> func, string instr_asm> :
151 !strconcat(instr_asm, " $rs, $rt"),
155 class LogicR<bits<6> func, string instr_asm, SDNode OpNode>:
159 (ins CPURegs:$b, CPURegs:$c),
160 !strconcat(instr_asm, " $dst, $b, $c"),
161 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
163 class LogicI<bits<6> op, string instr_asm, SDNode OpNode>:
166 (ins CPURegs:$b, uimm16:$c),
167 !strconcat(instr_asm, " $dst, $b, $c"),
168 [(set CPURegs:$dst, (OpNode CPURegs:$b, immSExt16:$c))], IIAlu>;
170 class LogicNOR<bits<6> op, bits<6> func, string instr_asm>:
174 (ins CPURegs:$b, CPURegs:$c),
175 !strconcat(instr_asm, " $dst, $b, $c"),
176 [(set CPURegs:$dst, (not (or CPURegs:$b, CPURegs:$c)))], IIAlu>;
180 class LogicR_shift_imm<bits<6> func, string instr_asm, SDNode OpNode>:
184 (ins CPURegs:$b, shamt:$c),
185 !strconcat(instr_asm, " $dst, $b, $c"),
186 [(set CPURegs:$dst, (OpNode CPURegs:$b, immZExt5:$c))], IIAlu>;
188 class LogicR_shift_reg<bits<6> func, string instr_asm, SDNode OpNode>:
192 (ins CPURegs:$b, CPURegs:$c),
193 !strconcat(instr_asm, " $dst, $b, $c"),
194 [(set CPURegs:$dst, (OpNode CPURegs:$b, CPURegs:$c))], IIAlu>;
196 // Load Upper Imediate
197 class LoadUpper<bits<6> op, string instr_asm>:
201 !strconcat(instr_asm, " $dst, $imm"),
205 let isLoad = 1, hasDelaySlot = 1 in
206 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode>:
210 !strconcat(instr_asm, " $dst, $addr"),
211 [(set CPURegs:$dst, (OpNode addr:$addr))], IILoad>;
214 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode>:
217 (ins CPURegs:$dst, mem:$addr),
218 !strconcat(instr_asm, " $dst, $addr"),
219 [(OpNode CPURegs:$dst, addr:$addr)], IIStore>;
221 // Conditional Branch
222 let isBranch = 1, isTerminator=1, hasDelaySlot = 1 in {
223 class CBranch<bits<6> op, string instr_asm, PatFrag cond_op>:
226 (ins CPURegs:$a, CPURegs:$b, brtarget:$offset),
227 !strconcat(instr_asm, " $a, $b, $offset"),
228 [(brcond (cond_op CPURegs:$a, CPURegs:$b), bb:$offset)],
232 class CBranchZero<bits<6> op, string instr_asm, PatFrag cond_op>:
235 (ins CPURegs:$src, brtarget:$offset),
236 !strconcat(instr_asm, " $src, $offset"),
237 [(brcond (cond_op CPURegs:$src, 0), bb:$offset)],
242 class SetCC_R<bits<6> op, bits<6> func, string instr_asm,
247 (ins CPURegs:$b, CPURegs:$c),
248 !strconcat(instr_asm, " $dst, $b, $c"),
249 [(set CPURegs:$dst, (cond_op CPURegs:$b, CPURegs:$c))],
252 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op,
253 Operand Od, PatLeaf imm_type>:
256 (ins CPURegs:$b, Od:$c),
257 !strconcat(instr_asm, " $dst, $b, $c"),
258 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))],
261 // Unconditional branch
262 let isBranch=1, isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
263 class JumpFJ<bits<6> op, string instr_asm>:
266 (ins brtarget:$target),
267 !strconcat(instr_asm, " $target"),
268 [(br bb:$target)], IIBranch>;
270 let isBranch=1, isTerminator=1, isBarrier=1, rd=0, hasDelaySlot = 1 in
271 class JumpFR<bits<6> op, bits<6> func, string instr_asm>:
275 (ins CPURegs:$target),
276 !strconcat(instr_asm, " $target"),
279 // Jump and Link (Call)
280 let isCall=1, hasDelaySlot=1,
281 // All calls clobber the non-callee saved registers...
282 Defs = [AT, V0, V1, A0, A1, A2, A3, T0, T1, T2,
283 T3, T4, T5, T6, T7, T8, T9, K0, K1, GP] in {
284 class JumpLink<bits<6> op, string instr_asm>:
287 (ins calltarget:$target),
288 !strconcat(instr_asm, " $target"),
289 [(MipsJmpLink imm:$target)], IIBranch>;
292 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm>:
297 !strconcat(instr_asm, " $rs"),
298 [(MipsJmpLink CPURegs:$rs)], IIBranch>;
300 class BranchLink<string instr_asm>:
303 (ins CPURegs:$rs, brtarget:$target),
304 !strconcat(instr_asm, " $rs, $target"),
309 class MulDiv<bits<6> func, string instr_asm, InstrItinClass itin>:
313 (ins CPURegs:$a, CPURegs:$b),
314 !strconcat(instr_asm, " $a, $b"),
318 class MoveFromTo<bits<6> func, string instr_asm>:
323 !strconcat(instr_asm, " $dst"),
326 // Count Leading Ones/Zeros in Word
327 class CountLeading<bits<6> func, string instr_asm>:
332 !strconcat(instr_asm, " $dst, $src"),
335 class EffectiveAddress<string instr_asm> :
340 [(set CPURegs:$dst, addr:$addr)], IIAlu>;
342 //===----------------------------------------------------------------------===//
343 // Pseudo instructions
344 //===----------------------------------------------------------------------===//
346 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>:
347 MipsInst<outs, ins, asmstr, pattern, IIPseudo>;
349 // As stack alignment is always done with addiu, we need a 16-bit immediate
350 let Defs = [SP], Uses = [SP] in {
351 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins uimm16:$amt),
352 "!ADJCALLSTACKDOWN $amt",
353 [(callseq_start imm:$amt)]>;
354 def ADJCALLSTACKUP : Pseudo<(outs), (ins uimm16:$amt),
355 "!ADJCALLSTACKUP $amt",
356 [(callseq_end imm:$amt)]>;
359 def IMPLICIT_DEF_CPURegs : Pseudo<(outs CPURegs:$dst), (ins),
360 "!IMPLICIT_DEF $dst",
361 [(set CPURegs:$dst, (undef))]>;
363 //===----------------------------------------------------------------------===//
364 // Instruction definition
365 //===----------------------------------------------------------------------===//
367 //===----------------------------------------------------------------------===//
368 // MipsI Instructions
369 //===----------------------------------------------------------------------===//
373 // ADDiu just accept 16-bit immediates but we handle this on Pat's.
374 // immZExt32 is used here so it can match GlobalAddress immediates.
375 def ADDiu : ArithI<0x09, "addiu", MipsAdd, uimm16, immZExt16>;
376 def ADDi : ArithI<0x08, "addi", add, simm16, immSExt16>;
377 def MUL : ArithR<0x1c, 0x02, "mul", mul, IIImul>;
378 def ADDu : ArithR<0x00, 0x21, "addu", add, IIAlu>;
379 def SUBu : ArithR<0x00, 0x23, "subu", sub, IIAlu>;
380 def ADD : ArithOverflowR<0x00, 0x20, "add">;
381 def SUB : ArithOverflowR<0x00, 0x22, "sub">;
382 def MADD : MArithR<0x00, "madd">;
383 def MADDU : MArithR<0x01, "maddu">;
384 def MSUB : MArithR<0x04, "msub">;
385 def MSUBU : MArithR<0x05, "msubu">;
388 def AND : LogicR<0x24, "and", and>;
389 def OR : LogicR<0x25, "or", or>;
390 def XOR : LogicR<0x26, "xor", xor>;
391 def ANDi : LogicI<0x0c, "andi", and>;
392 def ORi : LogicI<0x0d, "ori", or>;
393 def XORi : LogicI<0x0e, "xori", xor>;
394 def NOR : LogicNOR<0x00, 0x27, "nor">;
397 def SLL : LogicR_shift_imm<0x00, "sll", shl>;
398 def SRL : LogicR_shift_imm<0x02, "srl", srl>;
399 def SRA : LogicR_shift_imm<0x03, "sra", sra>;
400 def SLLV : LogicR_shift_reg<0x04, "sllv", shl>;
401 def SRLV : LogicR_shift_reg<0x06, "srlv", srl>;
402 def SRAV : LogicR_shift_reg<0x07, "srav", sra>;
404 // Load Upper Immediate
405 def LUi : LoadUpper<0x0f, "lui">;
408 def LB : LoadM<0x20, "lb", sextloadi8>;
409 def LBu : LoadM<0x24, "lbu", zextloadi8>;
410 def LH : LoadM<0x21, "lh", sextloadi16>;
411 def LHu : LoadM<0x25, "lhu", zextloadi16>;
412 def LW : LoadM<0x23, "lw", load>;
413 def SB : StoreM<0x28, "sb", truncstorei8>;
414 def SH : StoreM<0x29, "sh", truncstorei16>;
415 def SW : StoreM<0x2b, "sw", store>;
417 // Conditional Branch
418 def BEQ : CBranch<0x04, "beq", seteq>;
419 def BNE : CBranch<0x05, "bne", setne>;
422 def BGEZ : CBranchZero<0x01, "bgez", setge>;
425 def BGTZ : CBranchZero<0x07, "bgtz", setgt>;
426 def BLEZ : CBranchZero<0x07, "blez", setle>;
427 def BLTZ : CBranchZero<0x01, "bltz", setlt>;
430 // Set Condition Code
431 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt>;
432 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult>;
433 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16>;
434 def SLTiu : SetCC_I<0x0b, "sltiu", setult, uimm16, immZExt16>;
436 // Unconditional jump
437 def J : JumpFJ<0x02, "j">;
438 def JR : JumpFR<0x00, 0x08, "jr">;
440 // Jump and Link (Call)
441 def JAL : JumpLink<0x03, "jal">;
442 def JALR : JumpLinkReg<0x00, 0x09, "jalr">;
443 def BGEZAL : BranchLink<"bgezal">;
444 def BLTZAL : BranchLink<"bltzal">;
446 // MulDiv and Move From Hi/Lo operations, have
447 // their correpondent SDNodes created on ISelDAG.
448 // Special Mul, Div operations
449 def MULT : MulDiv<0x18, "mult", IIImul>;
450 def MULTu : MulDiv<0x19, "multu", IIImul>;
451 def DIV : MulDiv<0x1a, "div", IIIdiv>;
452 def DIVu : MulDiv<0x1b, "divu", IIIdiv>;
455 def MFHI : MoveFromTo<0x10, "mfhi">;
456 def MFLO : MoveFromTo<0x12, "mflo">;
457 def MTHI : MoveFromTo<0x11, "mthi">;
458 def MTLO : MoveFromTo<0x13, "mtlo">;
461 def CLO : CountLeading<0x21, "clo">;
462 def CLZ : CountLeading<0x20, "clz">;
466 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
468 // Ret instruction - as mips does not have "ret" a
469 // jr $ra must be generated.
470 let isReturn=1, isTerminator=1, hasDelaySlot=1,
471 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
473 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
474 "jr $target", [(MipsRet CPURegs:$target)], IIBranch>;
477 // FrameIndexes are legalized when they are operands from load/store
478 // instructions. The same not happens for stack address copies, so an
479 // add op with mem ComplexPattern is used and the stack address copy
480 // can be matched. It's similar to Sparc LEA_ADDRi
481 def LEA_ADDiu : EffectiveAddress<"addiu $dst, ${addr:stackloc}">;
483 //===----------------------------------------------------------------------===//
484 // Arbitrary patterns that map to one or more instructions
485 //===----------------------------------------------------------------------===//
488 def : Pat<(i32 immSExt16:$in),
489 (ADDiu ZERO, imm:$in)>;
490 def : Pat<(i32 immZExt16:$in),
491 (ORi ZERO, imm:$in)>;
493 // Arbitrary immediates
494 def : Pat<(i32 imm:$imm),
495 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
498 def : Pat<(MipsJmpLink (i32 tglobaladdr:$dst)),
499 (JAL tglobaladdr:$dst)>;
500 def : Pat<(MipsJmpLink (i32 texternalsym:$dst)),
501 (JAL texternalsym:$dst)>;
502 def : Pat<(MipsJmpLink CPURegs:$dst),
503 (JALR CPURegs:$dst)>;
505 // GlobalAddress, Constant Pool, ExternalSymbol, and JumpTable
506 def : Pat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
507 def : Pat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
508 def : Pat<(MipsAdd CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
509 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
511 // Mips does not have not, so we increase the operation
512 def : Pat<(not CPURegs:$in),
513 (NOR CPURegs:$in, ZERO)>;
515 // extended load and stores
516 def : Pat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
517 def : Pat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
518 def : Pat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
519 def : Pat<(truncstorei1 CPURegs:$src, addr:$addr),
520 (SB CPURegs:$src, addr:$addr)>;
526 // direct match equal/notequal zero branches
527 def : Pat<(brcond (setne CPURegs:$lhs, 0), bb:$dst),
528 (BNE CPURegs:$lhs, ZERO, bb:$dst)>;
529 def : Pat<(brcond (seteq CPURegs:$lhs, 0), bb:$dst),
530 (BEQ CPURegs:$lhs, ZERO, bb:$dst)>;
532 def : Pat<(brcond (setge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
533 (BGEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
534 def : Pat<(brcond (setuge CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
535 (BGEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
537 def : Pat<(brcond (setgt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
538 (BGTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
539 def : Pat<(brcond (setugt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
540 (BGTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
542 def : Pat<(brcond (setle CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
543 (BLEZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
544 def : Pat<(brcond (setule CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
545 (BLEZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
547 def : Pat<(brcond (setlt CPURegs:$lhs, immSExt16:$rhs), bb:$dst),
548 (BNE (SLTi CPURegs:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
549 def : Pat<(brcond (setult CPURegs:$lhs, immZExt16:$rhs), bb:$dst),
550 (BNE (SLTiu CPURegs:$lhs, immZExt16:$rhs), ZERO, bb:$dst)>;
551 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
552 (BNE (SLT CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
553 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
554 (BNE (SLTu CPURegs:$lhs, CPURegs:$rhs), ZERO, bb:$dst)>;
556 def : Pat<(brcond (setlt CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
557 (BLTZ (SUB CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
558 def : Pat<(brcond (setult CPURegs:$lhs, CPURegs:$rhs), bb:$dst),
559 (BLTZ (SUBu CPURegs:$lhs, CPURegs:$rhs), bb:$dst)>;
561 // generic brcond pattern
562 def : Pat<(brcond CPURegs:$cond, bb:$dst),
563 (BNE CPURegs:$cond, ZERO, bb:$dst)>;
566 /// setcc patterns, only matched when there
567 /// is no brcond following a setcc operation
570 // setcc 2 register operands
571 def : Pat<(setle CPURegs:$lhs, CPURegs:$rhs),
572 (XORi (SLT CPURegs:$rhs, CPURegs:$lhs), 1)>;
573 def : Pat<(setule CPURegs:$lhs, CPURegs:$rhs),
574 (XORi (SLTu CPURegs:$rhs, CPURegs:$lhs), 1)>;
576 def : Pat<(setgt CPURegs:$lhs, CPURegs:$rhs),
577 (SLT CPURegs:$rhs, CPURegs:$lhs)>;
578 def : Pat<(setugt CPURegs:$lhs, CPURegs:$rhs),
579 (SLTu CPURegs:$rhs, CPURegs:$lhs)>;
581 def : Pat<(setge CPURegs:$lhs, CPURegs:$rhs),
582 (XORi (SLT CPURegs:$lhs, CPURegs:$rhs), 1)>;
583 def : Pat<(setuge CPURegs:$lhs, CPURegs:$rhs),
584 (XORi (SLTu CPURegs:$lhs, CPURegs:$rhs), 1)>;
586 def : Pat<(setne CPURegs:$lhs, CPURegs:$rhs),
587 (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
588 (SLT CPURegs:$rhs, CPURegs:$lhs))>;
590 def : Pat<(seteq CPURegs:$lhs, CPURegs:$rhs),
591 (XORi (OR (SLT CPURegs:$lhs, CPURegs:$rhs),
592 (SLT CPURegs:$rhs, CPURegs:$lhs)), 1)>;
594 // setcc reg/imm operands
595 def : Pat<(setge CPURegs:$lhs, immSExt16:$rhs),
596 (XORi (SLTi CPURegs:$lhs, immSExt16:$rhs), 1)>;
597 def : Pat<(setuge CPURegs:$lhs, immZExt16:$rhs),
598 (XORi (SLTiu CPURegs:$lhs, immZExt16:$rhs), 1)>;