1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"FeatureMips32r6">;
171 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"!FeatureMips32r6">;
173 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
176 AssemblerPredicate<"!FeatureGP64Bit">;
177 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
178 AssemblerPredicate<"FeatureMips64">;
179 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
180 AssemblerPredicate<"FeatureMips64r2">;
181 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"FeatureMips64r6">;
183 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"!FeatureMips64r6">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_4_32 {
224 list<Predicate> InsnPredicates = [NotMips4_32];
226 class ISA_MIPS1_NOT_32R6_64R6 {
227 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
229 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
230 class ISA_MIPS2_NOT_32R6_64R6 {
231 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
233 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
234 class ISA_MIPS3_NOT_32R6_64R6 {
235 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
237 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
238 class ISA_MIPS32_NOT_32R6_64R6 {
239 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
241 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
242 class ISA_MIPS32R2_NOT_32R6_64R6 {
243 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
245 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
246 class ISA_MIPS64_NOT_64R6 {
247 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
249 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
250 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
251 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
253 // The portions of MIPS-III that were also added to MIPS32
254 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
256 // The portions of MIPS-III that were also added to MIPS32 but were removed in
257 // MIPS32r6 and MIPS64r6.
258 class INSN_MIPS3_32_NOT_32R6_64R6 {
259 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
262 // The portions of MIPS-III that were also added to MIPS32
263 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
265 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
266 // MIPS32r6 and MIPS64r6.
267 class INSN_MIPS4_32_NOT_32R6_64R6 {
268 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
271 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
272 // MIPS32r6 and MIPS64r6.
273 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
274 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
277 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
278 // MIPS32r6 and MIPS64r6.
279 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
280 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
283 //===----------------------------------------------------------------------===//
285 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
286 let EncodingPredicates = [HasStdEnc];
289 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
290 InstAlias<Asm, Result, Emit>, PredicateControl;
293 bit isCommutable = 1;
310 bit isTerminator = 1;
313 bit hasExtraSrcRegAllocReq = 1;
314 bit isCodeGenOnly = 1;
317 class IsAsCheapAsAMove {
318 bit isAsCheapAsAMove = 1;
321 class NeverHasSideEffects {
322 bit hasSideEffects = 0;
325 //===----------------------------------------------------------------------===//
326 // Instruction format superclass
327 //===----------------------------------------------------------------------===//
329 include "MipsInstrFormats.td"
331 //===----------------------------------------------------------------------===//
332 // Mips Operand, Complex Patterns and Transformations Definitions.
333 //===----------------------------------------------------------------------===//
335 def MipsJumpTargetAsmOperand : AsmOperandClass {
336 let Name = "JumpTarget";
337 let ParserMethod = "parseJumpTarget";
338 let PredicateMethod = "isImm";
339 let RenderMethod = "addImmOperands";
342 // Instruction operand types
343 def jmptarget : Operand<OtherVT> {
344 let EncoderMethod = "getJumpTargetOpValue";
345 let ParserMatchClass = MipsJumpTargetAsmOperand;
347 def brtarget : Operand<OtherVT> {
348 let EncoderMethod = "getBranchTargetOpValue";
349 let OperandType = "OPERAND_PCREL";
350 let DecoderMethod = "DecodeBranchTarget";
351 let ParserMatchClass = MipsJumpTargetAsmOperand;
353 def calltarget : Operand<iPTR> {
354 let EncoderMethod = "getJumpTargetOpValue";
355 let ParserMatchClass = MipsJumpTargetAsmOperand;
358 def simm9 : Operand<i32>;
359 def simm10 : Operand<i32>;
360 def simm11 : Operand<i32>;
362 def simm16 : Operand<i32> {
363 let DecoderMethod= "DecodeSimm16";
366 def simm19_lsl2 : Operand<i32> {
367 let EncoderMethod = "getSimm19Lsl2Encoding";
368 let DecoderMethod = "DecodeSimm19Lsl2";
369 let ParserMatchClass = MipsJumpTargetAsmOperand;
372 def simm18_lsl3 : Operand<i32> {
373 let EncoderMethod = "getSimm18Lsl3Encoding";
374 let DecoderMethod = "DecodeSimm18Lsl3";
375 let ParserMatchClass = MipsJumpTargetAsmOperand;
378 def simm20 : Operand<i32> {
381 def uimm20 : Operand<i32> {
384 def uimm10 : Operand<i32> {
387 def simm16_64 : Operand<i64> {
388 let DecoderMethod = "DecodeSimm16";
392 def uimmz : Operand<i32> {
393 let PrintMethod = "printUnsignedImm";
397 def uimm2 : Operand<i32> {
398 let PrintMethod = "printUnsignedImm";
401 def uimm3 : Operand<i32> {
402 let PrintMethod = "printUnsignedImm";
405 def uimm5 : Operand<i32> {
406 let PrintMethod = "printUnsignedImm";
409 def uimm6 : Operand<i32> {
410 let PrintMethod = "printUnsignedImm";
413 def uimm16 : Operand<i32> {
414 let PrintMethod = "printUnsignedImm";
417 def pcrel16 : Operand<i32> {
420 def MipsMemAsmOperand : AsmOperandClass {
422 let ParserMethod = "parseMemOperand";
425 def MipsMemSimm11AsmOperand : AsmOperandClass {
426 let Name = "MemOffsetSimm11";
427 let SuperClasses = [MipsMemAsmOperand];
428 let RenderMethod = "addMemOperands";
429 let ParserMethod = "parseMemOperand";
430 let PredicateMethod = "isMemWithSimmOffset<11>";
433 def MipsMemSimm16AsmOperand : AsmOperandClass {
434 let Name = "MemOffsetSimm16";
435 let SuperClasses = [MipsMemAsmOperand];
436 let RenderMethod = "addMemOperands";
437 let ParserMethod = "parseMemOperand";
438 let PredicateMethod = "isMemWithSimmOffset<16>";
441 def MipsInvertedImmoperand : AsmOperandClass {
443 let RenderMethod = "addImmOperands";
444 let ParserMethod = "parseInvNum";
447 def InvertedImOperand : Operand<i32> {
448 let ParserMatchClass = MipsInvertedImmoperand;
451 def InvertedImOperand64 : Operand<i64> {
452 let ParserMatchClass = MipsInvertedImmoperand;
455 class mem_generic : Operand<iPTR> {
456 let PrintMethod = "printMemOperand";
457 let MIOperandInfo = (ops ptr_rc, simm16);
458 let EncoderMethod = "getMemEncoding";
459 let ParserMatchClass = MipsMemAsmOperand;
460 let OperandType = "OPERAND_MEMORY";
464 def mem : mem_generic;
466 // MSA specific address operand
467 def mem_msa : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm10);
469 let EncoderMethod = "getMSAMemEncoding";
472 def mem_simm9 : mem_generic {
473 let MIOperandInfo = (ops ptr_rc, simm9);
474 let EncoderMethod = "getMemEncoding";
477 def mem_simm11 : mem_generic {
478 let MIOperandInfo = (ops ptr_rc, simm11);
479 let EncoderMethod = "getMemEncoding";
480 let ParserMatchClass = MipsMemSimm11AsmOperand;
483 def mem_simm16 : mem_generic {
484 let MIOperandInfo = (ops ptr_rc, simm16);
485 let EncoderMethod = "getMemEncoding";
486 let ParserMatchClass = MipsMemSimm16AsmOperand;
489 def mem_ea : Operand<iPTR> {
490 let PrintMethod = "printMemOperandEA";
491 let MIOperandInfo = (ops ptr_rc, simm16);
492 let EncoderMethod = "getMemEncoding";
493 let OperandType = "OPERAND_MEMORY";
496 def PtrRC : Operand<iPTR> {
497 let MIOperandInfo = (ops ptr_rc);
498 let DecoderMethod = "DecodePtrRegisterClass";
499 let ParserMatchClass = GPR32AsmOperand;
502 // size operand of ext instruction
503 def size_ext : Operand<i32> {
504 let EncoderMethod = "getSizeExtEncoding";
505 let DecoderMethod = "DecodeExtSize";
508 // size operand of ins instruction
509 def size_ins : Operand<i32> {
510 let EncoderMethod = "getSizeInsEncoding";
511 let DecoderMethod = "DecodeInsSize";
514 // Transformation Function - get the lower 16 bits.
515 def LO16 : SDNodeXForm<imm, [{
516 return getImm(N, N->getZExtValue() & 0xFFFF);
519 // Transformation Function - get the higher 16 bits.
520 def HI16 : SDNodeXForm<imm, [{
521 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
525 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
527 // Node immediate is zero (e.g. insve.d)
528 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
530 // Node immediate fits as 16-bit sign extended on target immediate.
532 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
534 // Node immediate fits as 16-bit sign extended on target immediate.
536 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
538 // Node immediate fits as 15-bit sign extended on target immediate.
540 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
542 // Node immediate fits as 16-bit zero extended on target immediate.
543 // The LO16 param means that only the lower 16 bits of the node
544 // immediate are caught.
546 def immZExt16 : PatLeaf<(imm), [{
547 if (N->getValueType(0) == MVT::i32)
548 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
550 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
553 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
554 def immLow16Zero : PatLeaf<(imm), [{
555 int64_t Val = N->getSExtValue();
556 return isInt<32>(Val) && !(Val & 0xffff);
559 // shamt field must fit in 5 bits.
560 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
562 // True if (N + 1) fits in 16-bit field.
563 def immSExt16Plus1 : PatLeaf<(imm), [{
564 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
567 // Mips Address Mode! SDNode frameindex could possibily be a match
568 // since load and store instructions from stack used it.
570 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
573 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
576 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
579 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
581 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
583 //===----------------------------------------------------------------------===//
584 // Instructions specific format
585 //===----------------------------------------------------------------------===//
587 // Arithmetic and logical instructions with 3 register operands.
588 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
589 InstrItinClass Itin = NoItinerary,
590 SDPatternOperator OpNode = null_frag>:
591 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
592 !strconcat(opstr, "\t$rd, $rs, $rt"),
593 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
594 let isCommutable = isComm;
595 let isReMaterializable = 1;
596 let TwoOperandAliasConstraint = "$rd = $rs";
599 // Arithmetic and logical instructions with 2 register operands.
600 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
601 InstrItinClass Itin = NoItinerary,
602 SDPatternOperator imm_type = null_frag,
603 SDPatternOperator OpNode = null_frag> :
604 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
605 !strconcat(opstr, "\t$rt, $rs, $imm16"),
606 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
608 let isReMaterializable = 1;
609 let TwoOperandAliasConstraint = "$rs = $rt";
612 // Arithmetic Multiply ADD/SUB
613 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
614 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
615 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
616 let Defs = [HI0, LO0];
617 let Uses = [HI0, LO0];
618 let isCommutable = isComm;
622 class LogicNOR<string opstr, RegisterOperand RO>:
623 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
624 !strconcat(opstr, "\t$rd, $rs, $rt"),
625 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
626 let isCommutable = 1;
630 class shift_rotate_imm<string opstr, Operand ImmOpnd,
631 RegisterOperand RO, InstrItinClass itin,
632 SDPatternOperator OpNode = null_frag,
633 SDPatternOperator PF = null_frag> :
634 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
635 !strconcat(opstr, "\t$rd, $rt, $shamt"),
636 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
637 let TwoOperandAliasConstraint = "$rt = $rd";
640 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
641 SDPatternOperator OpNode = null_frag>:
642 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
643 !strconcat(opstr, "\t$rd, $rt, $rs"),
644 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
647 // Load Upper Imediate
648 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
649 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
650 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
651 let hasSideEffects = 0;
652 let isReMaterializable = 1;
656 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
657 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
658 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
659 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
660 let DecoderMethod = "DecodeMem";
661 let canFoldAsLoad = 1;
665 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
666 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
667 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
668 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
669 let DecoderMethod = "DecodeMem";
673 // Load/Store Left/Right
674 let canFoldAsLoad = 1 in
675 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
676 InstrItinClass Itin> :
677 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
678 !strconcat(opstr, "\t$rt, $addr"),
679 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
680 let DecoderMethod = "DecodeMem";
681 string Constraints = "$src = $rt";
684 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
685 InstrItinClass Itin> :
686 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
687 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
688 let DecoderMethod = "DecodeMem";
692 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
693 SDPatternOperator OpNode= null_frag> :
694 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
695 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
696 let DecoderMethod = "DecodeFMem2";
700 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
701 SDPatternOperator OpNode= null_frag> :
702 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
703 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
704 let DecoderMethod = "DecodeFMem2";
709 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
710 SDPatternOperator OpNode= null_frag> :
711 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
712 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
713 let DecoderMethod = "DecodeFMem3";
717 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
718 SDPatternOperator OpNode= null_frag> :
719 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
720 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
721 let DecoderMethod = "DecodeFMem3";
725 // Conditional Branch
726 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
727 RegisterOperand RO, bit DelaySlot = 1> :
728 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
729 !strconcat(opstr, "\t$rs, $rt, $offset"),
730 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
733 let isTerminator = 1;
734 let hasDelaySlot = DelaySlot;
738 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
739 RegisterOperand RO, bit DelaySlot = 1> :
740 InstSE<(outs), (ins RO:$rs, opnd:$offset),
741 !strconcat(opstr, "\t$rs, $offset"),
742 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
745 let isTerminator = 1;
746 let hasDelaySlot = DelaySlot;
751 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
752 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
753 !strconcat(opstr, "\t$rd, $rs, $rt"),
754 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
755 II_SLT_SLTU, FrmR, opstr>;
757 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
759 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
760 !strconcat(opstr, "\t$rt, $rs, $imm16"),
761 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
762 II_SLTI_SLTIU, FrmI, opstr>;
765 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
766 SDPatternOperator targetoperator, string bopstr> :
767 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
768 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
771 let hasDelaySlot = 1;
772 let DecoderMethod = "DecodeJumpTarget";
776 // Unconditional branch
777 class UncondBranch<Instruction BEQInst> :
778 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
779 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
781 let isTerminator = 1;
783 let hasDelaySlot = 1;
784 let AdditionalPredicates = [RelocPIC];
788 // Base class for indirect branch and return instruction classes.
789 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
790 class JumpFR<string opstr, RegisterOperand RO,
791 SDPatternOperator operator = null_frag>:
792 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
796 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
798 let isIndirectBranch = 1;
801 // Jump and Link (Call)
802 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
803 class JumpLink<string opstr, DAGOperand opnd> :
804 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
805 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
806 let DecoderMethod = "DecodeJumpTarget";
809 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
810 Register RetReg, RegisterOperand ResRO = RO>:
811 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
812 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
814 class JumpLinkReg<string opstr, RegisterOperand RO>:
815 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
818 class BGEZAL_FT<string opstr, DAGOperand opnd,
819 RegisterOperand RO, bit DelaySlot = 1> :
820 InstSE<(outs), (ins RO:$rs, opnd:$offset),
821 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
822 let hasDelaySlot = DelaySlot;
827 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
828 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
829 class TailCall<Instruction JumpInst> :
830 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
831 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
833 class TailCallReg<RegisterOperand RO, Instruction JRInst,
834 RegisterOperand ResRO = RO> :
835 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
836 PseudoInstExpansion<(JRInst ResRO:$rs)>;
839 class BAL_BR_Pseudo<Instruction RealInst> :
840 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
841 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
843 let isTerminator = 1;
845 let hasDelaySlot = 1;
850 class SYS_FT<string opstr> :
851 InstSE<(outs), (ins uimm20:$code_),
852 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
854 class BRK_FT<string opstr> :
855 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
856 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
860 class ER_FT<string opstr> :
861 InstSE<(outs), (ins),
862 opstr, [], NoItinerary, FrmOther, opstr>;
865 class DEI_FT<string opstr, RegisterOperand RO> :
866 InstSE<(outs RO:$rt), (ins),
867 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
870 class WAIT_FT<string opstr> :
871 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
874 let hasSideEffects = 1 in
875 class SYNC_FT<string opstr> :
876 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
877 NoItinerary, FrmOther, opstr>;
879 class SYNCI_FT<string opstr> :
880 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
881 NoItinerary, FrmOther, opstr> {
882 let hasSideEffects = 1;
883 let DecoderMethod = "DecodeSyncI";
886 let hasSideEffects = 1 in
887 class TEQ_FT<string opstr, RegisterOperand RO> :
888 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
889 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
892 class TEQI_FT<string opstr, RegisterOperand RO> :
893 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
894 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
896 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
897 list<Register> DefRegs> :
898 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
900 let isCommutable = 1;
902 let hasSideEffects = 0;
905 // Pseudo multiply/divide instruction with explicit accumulator register
907 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
908 SDPatternOperator OpNode, InstrItinClass Itin,
909 bit IsComm = 1, bit HasSideEffects = 0,
910 bit UsesCustomInserter = 0> :
911 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
912 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
913 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
914 let isCommutable = IsComm;
915 let hasSideEffects = HasSideEffects;
916 let usesCustomInserter = UsesCustomInserter;
919 // Pseudo multiply add/sub instruction with explicit accumulator register
921 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
923 : PseudoSE<(outs ACC64:$ac),
924 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
926 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
928 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
929 string Constraints = "$acin = $ac";
932 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
933 list<Register> DefRegs> :
934 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
935 [], itin, FrmR, opstr> {
940 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
941 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
942 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
944 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
945 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
948 let hasSideEffects = 0;
951 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
952 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
953 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
956 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
957 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
960 let hasSideEffects = 0;
963 class EffectiveAddress<string opstr, RegisterOperand RO> :
964 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
965 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
966 !strconcat(opstr, "_lea")> {
967 let isCodeGenOnly = 1;
968 let DecoderMethod = "DecodeMem";
971 // Count Leading Ones/Zeros in Word
972 class CountLeading0<string opstr, RegisterOperand RO>:
973 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
974 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
976 class CountLeading1<string opstr, RegisterOperand RO>:
977 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
978 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
980 // Sign Extend in Register.
981 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
982 InstrItinClass itin> :
983 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
984 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
987 class SubwordSwap<string opstr, RegisterOperand RO>:
988 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
989 NoItinerary, FrmR, opstr> {
990 let hasSideEffects = 0;
994 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
995 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
996 II_RDHWR, FrmR, "rdhwr">;
999 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1000 SDPatternOperator Op = null_frag>:
1001 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1002 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1003 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
1004 FrmR, opstr>, ISA_MIPS32R2;
1006 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1007 SDPatternOperator Op = null_frag>:
1008 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1009 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1010 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1011 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
1012 let Constraints = "$src = $rt";
1015 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1016 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1017 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1018 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1020 // Atomic Compare & Swap.
1021 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1022 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1023 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1025 class LLBase<string opstr, RegisterOperand RO> :
1026 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1027 [], NoItinerary, FrmI> {
1028 let DecoderMethod = "DecodeMem";
1032 class SCBase<string opstr, RegisterOperand RO> :
1033 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1034 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1035 let DecoderMethod = "DecodeMem";
1037 let Constraints = "$rt = $dst";
1040 class MFC3OP<string asmstr, RegisterOperand RO> :
1041 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1042 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1044 class TrapBase<Instruction RealInst>
1045 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1046 PseudoInstExpansion<(RealInst 0, 0)> {
1048 let isTerminator = 1;
1049 let isCodeGenOnly = 1;
1052 //===----------------------------------------------------------------------===//
1053 // Pseudo instructions
1054 //===----------------------------------------------------------------------===//
1057 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1058 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1060 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1061 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1062 [(callseq_start timm:$amt)]>;
1063 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1064 [(callseq_end timm:$amt1, timm:$amt2)]>;
1067 let usesCustomInserter = 1 in {
1068 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1069 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1070 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1071 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1072 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1073 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1074 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1075 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1076 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1077 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1078 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1079 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1080 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1081 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1082 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1083 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1084 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1085 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1087 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1088 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1089 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1091 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1092 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1093 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1096 /// Pseudo instructions for loading and storing accumulator registers.
1097 let isPseudo = 1, isCodeGenOnly = 1 in {
1098 def LOAD_ACC64 : Load<"", ACC64>;
1099 def STORE_ACC64 : Store<"", ACC64>;
1102 // We need these two pseudo instructions to avoid offset calculation for long
1103 // branches. See the comment in file MipsLongBranch.cpp for detailed
1106 // Expands to: lui $dst, %hi($tgt - $baltgt)
1107 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1108 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1110 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1111 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1112 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1114 //===----------------------------------------------------------------------===//
1115 // Instruction definition
1116 //===----------------------------------------------------------------------===//
1117 //===----------------------------------------------------------------------===//
1118 // MipsI Instructions
1119 //===----------------------------------------------------------------------===//
1121 /// Arithmetic Instructions (ALU Immediate)
1122 let AdditionalPredicates = [NotInMicroMips] in {
1123 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1124 add>, ADDI_FM<0x9>, IsAsCheapAsAMove;
1126 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1127 ISA_MIPS1_NOT_32R6_64R6;
1128 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1130 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1132 let AdditionalPredicates = [NotInMicroMips] in {
1133 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1136 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1139 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1142 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1143 let AdditionalPredicates = [NotInMicroMips] in {
1144 /// Arithmetic Instructions (3-Operand, R-Type)
1145 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1147 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1150 let Defs = [HI0, LO0] in
1151 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1152 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1153 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1154 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1155 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1156 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1157 let AdditionalPredicates = [NotInMicroMips] in {
1158 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1160 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1162 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1165 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1167 /// Shift Instructions
1168 let AdditionalPredicates = [NotInMicroMips] in {
1169 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1170 immZExt5>, SRA_FM<0, 0>;
1171 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1172 immZExt5>, SRA_FM<2, 0>;
1174 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1175 immZExt5>, SRA_FM<3, 0>;
1176 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1178 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1180 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1183 // Rotate Instructions
1184 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1186 SRA_FM<2, 1>, ISA_MIPS32R2;
1187 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1188 SRLV_FM<6, 1>, ISA_MIPS32R2;
1190 /// Load and Store Instructions
1192 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1193 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1195 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1197 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1198 let AdditionalPredicates = [NotInMicroMips] in {
1199 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1202 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1203 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1204 let AdditionalPredicates = [NotInMicroMips] in {
1205 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1208 /// load/store left/right
1209 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1210 AdditionalPredicates = [NotInMicroMips] in {
1211 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1212 ISA_MIPS1_NOT_32R6_64R6;
1213 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1214 ISA_MIPS1_NOT_32R6_64R6;
1215 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1216 ISA_MIPS1_NOT_32R6_64R6;
1217 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1218 ISA_MIPS1_NOT_32R6_64R6;
1221 let AdditionalPredicates = [NotInMicroMips] in {
1222 // COP2 Memory Instructions
1223 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1224 ISA_MIPS1_NOT_32R6_64R6;
1225 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1226 ISA_MIPS1_NOT_32R6_64R6;
1227 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1228 ISA_MIPS2_NOT_32R6_64R6;
1229 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1230 ISA_MIPS2_NOT_32R6_64R6;
1232 // COP3 Memory Instructions
1233 let DecoderNamespace = "COP3_" in {
1234 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1235 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1236 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1238 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1243 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1244 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1246 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1247 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1248 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1249 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1250 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1251 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1253 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1254 ISA_MIPS2_NOT_32R6_64R6;
1255 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1256 ISA_MIPS2_NOT_32R6_64R6;
1257 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1258 ISA_MIPS2_NOT_32R6_64R6;
1259 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1260 ISA_MIPS2_NOT_32R6_64R6;
1261 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1262 ISA_MIPS2_NOT_32R6_64R6;
1263 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1264 ISA_MIPS2_NOT_32R6_64R6;
1266 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1267 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1268 def TRAP : TrapBase<BREAK>;
1269 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1271 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1272 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1274 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1275 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1277 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1278 AdditionalPredicates = [NotInMicroMips] in {
1279 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1281 /// Load-linked, Store-conditional
1282 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1283 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1286 /// Jump and Branch Instructions
1287 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1288 AdditionalRequires<[RelocStatic]>, IsBranch;
1289 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1290 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1291 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1292 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1293 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1294 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1295 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1296 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1298 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1299 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1300 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1302 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1303 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1304 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1306 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1307 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1308 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1310 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1311 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1312 def B : UncondBranch<BEQ>;
1314 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1315 let AdditionalPredicates = [NotInMicroMips] in {
1316 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1317 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1320 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1321 ISA_MIPS32_NOT_32R6_64R6;
1322 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1323 ISA_MIPS1_NOT_32R6_64R6;
1324 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1325 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1326 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1327 ISA_MIPS1_NOT_32R6_64R6;
1328 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1329 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1330 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1331 def TAILCALL : TailCall<J>;
1332 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1334 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1335 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1336 class PseudoIndirectBranchBase<RegisterOperand RO> :
1337 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1340 let hasDelaySlot = 1;
1342 let isIndirectBranch = 1;
1345 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1347 // Return instructions are matched as a RetRA instruction, then ar expanded
1348 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1349 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1351 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1353 let isTerminator = 1;
1355 let hasDelaySlot = 1;
1357 let isCodeGenOnly = 1;
1359 let hasExtraSrcRegAllocReq = 1;
1362 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1364 // Exception handling related node and instructions.
1365 // The conversion sequence is:
1366 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1367 // MIPSeh_return -> (stack change + indirect branch)
1369 // MIPSeh_return takes the place of regular return instruction
1370 // but takes two arguments (V1, V0) which are used for storing
1371 // the offset and return address respectively.
1372 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1374 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1375 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1377 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1378 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1379 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1380 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1382 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1385 /// Multiply and Divide Instructions.
1386 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1387 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1388 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1389 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1390 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1391 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1392 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1393 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1395 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1396 ISA_MIPS1_NOT_32R6_64R6;
1397 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1398 ISA_MIPS1_NOT_32R6_64R6;
1399 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1400 AdditionalPredicates = [NotInMicroMips] in {
1401 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1402 ISA_MIPS1_NOT_32R6_64R6;
1403 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1404 ISA_MIPS1_NOT_32R6_64R6;
1407 /// Sign Ext In Register Instructions.
1408 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1409 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1410 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1411 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1414 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1415 ISA_MIPS32_NOT_32R6_64R6;
1416 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1417 ISA_MIPS32_NOT_32R6_64R6;
1419 /// Word Swap Bytes Within Halfwords
1420 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1423 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1425 // FrameIndexes are legalized when they are operands from load/store
1426 // instructions. The same not happens for stack address copies, so an
1427 // add op with mem ComplexPattern is used and the stack address copy
1428 // can be matched. It's similar to Sparc LEA_ADDRi
1429 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1432 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1433 ISA_MIPS32_NOT_32R6_64R6;
1434 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1435 ISA_MIPS32_NOT_32R6_64R6;
1436 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1437 ISA_MIPS32_NOT_32R6_64R6;
1438 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1439 ISA_MIPS32_NOT_32R6_64R6;
1441 let AdditionalPredicates = [NotDSP] in {
1442 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1443 ISA_MIPS1_NOT_32R6_64R6;
1444 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1445 ISA_MIPS1_NOT_32R6_64R6;
1446 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1447 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1448 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1449 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1450 ISA_MIPS32_NOT_32R6_64R6;
1451 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1452 ISA_MIPS32_NOT_32R6_64R6;
1453 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1454 ISA_MIPS32_NOT_32R6_64R6;
1455 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1456 ISA_MIPS32_NOT_32R6_64R6;
1459 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1460 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1461 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1462 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1464 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1466 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1467 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1469 /// Move Control Registers From/To CPU Registers
1470 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1471 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1472 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1473 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1475 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1477 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1478 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1479 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1481 // JR_HB and JALR_HB are defined here using the new style naming
1482 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1483 // and because of that it doesn't follow the naming convention of the
1484 // rest of the file. To avoid a mixture of old vs new style, the new
1485 // style was chosen.
1486 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1487 dag OutOperandList = (outs);
1488 dag InOperandList = (ins GPROpnd:$rs);
1489 string AsmString = !strconcat(instr_asm, "\t$rs");
1490 list<dag> Pattern = [];
1493 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1494 dag OutOperandList = (outs GPROpnd:$rd);
1495 dag InOperandList = (ins GPROpnd:$rs);
1496 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1497 list<dag> Pattern = [];
1500 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1501 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1503 let isIndirectBranch=1;
1509 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1510 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1511 let isIndirectBranch=1;
1515 class JR_HB_ENC : JR_HB_FM<8>;
1516 class JALR_HB_ENC : JALR_HB_FM<9>;
1518 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1519 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1521 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1523 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1524 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1525 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1526 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1528 class CacheOp<string instr_asm, Operand MemOpnd> :
1529 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1530 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1532 let DecoderMethod = "DecodeCacheOp";
1535 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1536 INSN_MIPS3_32_NOT_32R6_64R6;
1537 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1538 INSN_MIPS3_32_NOT_32R6_64R6;
1540 //===----------------------------------------------------------------------===//
1541 // Instruction aliases
1542 //===----------------------------------------------------------------------===//
1543 def : MipsInstAlias<"move $dst, $src",
1544 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1546 let AdditionalPredicates = [NotInMicroMips];
1548 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1549 ISA_MIPS1_NOT_32R6_64R6;
1550 def : MipsInstAlias<"addu $rs, $rt, $imm",
1551 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1552 def : MipsInstAlias<"addu $rs, $imm",
1553 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1554 def : MipsInstAlias<"add $rs, $rt, $imm",
1555 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1556 ISA_MIPS1_NOT_32R6_64R6;
1557 def : MipsInstAlias<"add $rs, $imm",
1558 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1559 ISA_MIPS1_NOT_32R6_64R6;
1560 def : MipsInstAlias<"and $rs, $rt, $imm",
1561 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1562 def : MipsInstAlias<"and $rs, $imm",
1563 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1564 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1565 let Predicates = [NotInMicroMips] in {
1566 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1568 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1569 def : MipsInstAlias<"not $rt, $rs",
1570 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1571 def : MipsInstAlias<"neg $rt, $rs",
1572 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1573 def : MipsInstAlias<"negu $rt",
1574 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1575 def : MipsInstAlias<"negu $rt, $rs",
1576 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1577 def : MipsInstAlias<"slt $rs, $rt, $imm",
1578 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1579 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1580 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1581 def : MipsInstAlias<"xor $rs, $rt, $imm",
1582 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1583 def : MipsInstAlias<"or $rs, $rt, $imm",
1584 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1585 def : MipsInstAlias<"or $rs, $imm",
1586 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1587 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1588 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1589 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1590 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1591 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1592 let AdditionalPredicates = [NotInMicroMips] in {
1593 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1595 def : MipsInstAlias<"bnez $rs,$offset",
1596 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1597 def : MipsInstAlias<"beqz $rs,$offset",
1598 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1599 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1601 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1602 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1603 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1604 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1606 def : MipsInstAlias<"teq $rs, $rt",
1607 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1608 def : MipsInstAlias<"tge $rs, $rt",
1609 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1610 def : MipsInstAlias<"tgeu $rs, $rt",
1611 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1612 def : MipsInstAlias<"tlt $rs, $rt",
1613 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1614 def : MipsInstAlias<"tltu $rs, $rt",
1615 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1616 def : MipsInstAlias<"tne $rs, $rt",
1617 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1619 def : MipsInstAlias<"sll $rd, $rt, $rs",
1620 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1621 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1622 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1623 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1624 def : MipsInstAlias<"sub $rs, $imm",
1625 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1626 0>, ISA_MIPS1_NOT_32R6_64R6;
1627 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1628 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1629 InvertedImOperand:$imm), 0>;
1630 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1631 InvertedImOperand:$imm), 0>;
1632 def : MipsInstAlias<"sra $rd, $rt, $rs",
1633 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1634 def : MipsInstAlias<"srl $rd, $rt, $rs",
1635 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1636 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1637 def : MipsInstAlias<"sync",
1638 (SYNC 0), 1>, ISA_MIPS2;
1639 //===----------------------------------------------------------------------===//
1640 // Assembler Pseudo Instructions
1641 //===----------------------------------------------------------------------===//
1643 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1644 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1645 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1646 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1648 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1649 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1650 !strconcat(instr_asm, "\t$rt, $addr")> ;
1651 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1653 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1654 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1655 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1656 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1658 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1660 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1663 //===----------------------------------------------------------------------===//
1664 // Arbitrary patterns that map to one or more instructions
1665 //===----------------------------------------------------------------------===//
1667 // Load/store pattern templates.
1668 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1669 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1671 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1672 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1675 let AdditionalPredicates = [NotInMicroMips] in {
1676 def : MipsPat<(i32 immSExt16:$in),
1677 (ADDiu ZERO, imm:$in)>;
1678 def : MipsPat<(i32 immZExt16:$in),
1679 (ORi ZERO, imm:$in)>;
1681 def : MipsPat<(i32 immLow16Zero:$in),
1682 (LUi (HI16 imm:$in))>;
1684 // Arbitrary immediates
1685 def : MipsPat<(i32 imm:$imm),
1686 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1688 // Carry MipsPatterns
1689 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1690 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1691 let AdditionalPredicates = [NotDSP] in {
1692 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1693 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1694 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1695 (ADDiu GPR32:$src, imm:$imm)>;
1698 // Support multiplication for pre-Mips32 targets that don't have
1699 // the MUL instruction.
1700 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1701 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1702 ISA_MIPS1_NOT_32R6_64R6;
1705 def : MipsPat<(MipsSync (i32 immz)),
1706 (SYNC 0)>, ISA_MIPS2;
1709 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1710 (JAL tglobaladdr:$dst)>;
1711 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1712 (JAL texternalsym:$dst)>;
1713 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1714 // (JALR GPR32:$dst)>;
1717 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1718 (TAILCALL tglobaladdr:$dst)>;
1719 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1720 (TAILCALL texternalsym:$dst)>;
1722 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1723 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1724 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1725 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1726 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1727 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1729 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1730 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1731 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1732 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1733 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1734 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1736 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1737 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1738 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1739 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1740 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1741 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1742 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1743 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1744 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1745 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1748 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1749 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1750 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1751 (ADDiu GPR32:$gp, tconstpool:$in)>;
1754 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1755 MipsPat<(MipsWrapper RC:$gp, node:$in),
1756 (ADDiuOp RC:$gp, node:$in)>;
1758 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1759 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1760 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1761 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1762 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1763 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1765 // Mips does not have "not", so we expand our way
1766 def : MipsPat<(not GPR32:$in),
1767 (NOR GPR32Opnd:$in, ZERO)>;
1770 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1771 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1772 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1775 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1778 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1779 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1780 Instruction SLTiuOp, Register ZEROReg> {
1781 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1782 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1783 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1784 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1786 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1787 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1788 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1789 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1790 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1791 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1792 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1793 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1794 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1795 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1796 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1797 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1799 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1800 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1801 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1802 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1804 def : MipsPat<(brcond RC:$cond, bb:$dst),
1805 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1808 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1810 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1811 (BLEZ i32:$lhs, bb:$dst)>;
1812 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1813 (BGEZ i32:$lhs, bb:$dst)>;
1816 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1817 Instruction SLTuOp, Register ZEROReg> {
1818 def : MipsPat<(seteq RC:$lhs, 0),
1819 (SLTiuOp RC:$lhs, 1)>;
1820 def : MipsPat<(setne RC:$lhs, 0),
1821 (SLTuOp ZEROReg, RC:$lhs)>;
1822 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1823 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1824 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1825 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1828 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1829 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1830 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1831 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1832 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1835 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1836 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1837 (SLTOp RC:$rhs, RC:$lhs)>;
1838 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1839 (SLTuOp RC:$rhs, RC:$lhs)>;
1842 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1843 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1844 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1845 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1846 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1849 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1850 Instruction SLTiuOp> {
1851 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1852 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1853 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1854 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1857 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1858 defm : SetlePats<GPR32, SLT, SLTu>;
1859 defm : SetgtPats<GPR32, SLT, SLTu>;
1860 defm : SetgePats<GPR32, SLT, SLTu>;
1861 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1864 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1866 // Load halfword/word patterns.
1867 let AddedComplexity = 40 in {
1868 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1869 def : LoadRegImmPat<LH, i32, sextloadi16>;
1870 let AdditionalPredicates = [NotInMicroMips] in {
1871 def : LoadRegImmPat<LW, i32, load>;
1875 //===----------------------------------------------------------------------===//
1876 // Floating Point Support
1877 //===----------------------------------------------------------------------===//
1879 include "MipsInstrFPU.td"
1880 include "Mips64InstrInfo.td"
1881 include "MipsCondMov.td"
1883 include "Mips32r6InstrInfo.td"
1884 include "Mips64r6InstrInfo.td"
1889 include "Mips16InstrFormats.td"
1890 include "Mips16InstrInfo.td"
1893 include "MipsDSPInstrFormats.td"
1894 include "MipsDSPInstrInfo.td"
1897 include "MipsMSAInstrFormats.td"
1898 include "MipsMSAInstrInfo.td"
1901 include "MicroMipsInstrFormats.td"
1902 include "MicroMipsInstrInfo.td"
1903 include "MicroMipsInstrFPU.td"