1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
172 AssemblerPredicate<"!FeatureN64">;
173 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
174 AssemblerPredicate<"FeatureMips16">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 // Instruction operand types
239 def jmptarget : Operand<OtherVT> {
240 let EncoderMethod = "getJumpTargetOpValue";
242 def brtarget : Operand<OtherVT> {
243 let EncoderMethod = "getBranchTargetOpValue";
244 let OperandType = "OPERAND_PCREL";
245 let DecoderMethod = "DecodeBranchTarget";
247 def calltarget : Operand<iPTR> {
248 let EncoderMethod = "getJumpTargetOpValue";
251 def simm16 : Operand<i32> {
252 let DecoderMethod= "DecodeSimm16";
255 def simm20 : Operand<i32> {
258 def uimm20 : Operand<i32> {
261 def uimm10 : Operand<i32> {
264 def simm16_64 : Operand<i64> {
265 let DecoderMethod = "DecodeSimm16";
269 def uimm5 : Operand<i32> {
270 let PrintMethod = "printUnsignedImm";
273 def uimm6 : Operand<i32> {
274 let PrintMethod = "printUnsignedImm";
277 def uimm16 : Operand<i32> {
278 let PrintMethod = "printUnsignedImm";
281 def pcrel16 : Operand<i32> {
284 def MipsMemAsmOperand : AsmOperandClass {
286 let ParserMethod = "parseMemOperand";
289 def MipsInvertedImmoperand : AsmOperandClass {
291 let RenderMethod = "addImmOperands";
292 let ParserMethod = "parseInvNum";
295 def PtrRegAsmOperand : AsmOperandClass {
297 let ParserMethod = "parsePtrReg";
301 def InvertedImOperand : Operand<i32> {
302 let ParserMatchClass = MipsInvertedImmoperand;
305 class mem_generic : Operand<iPTR> {
306 let PrintMethod = "printMemOperand";
307 let MIOperandInfo = (ops ptr_rc, simm16);
308 let EncoderMethod = "getMemEncoding";
309 let ParserMatchClass = MipsMemAsmOperand;
310 let OperandType = "OPERAND_MEMORY";
314 def mem : mem_generic;
316 // MSA specific address operand
317 def mem_msa : mem_generic {
318 let EncoderMethod = "getMSAMemEncoding";
321 def mem_ea : Operand<iPTR> {
322 let PrintMethod = "printMemOperandEA";
323 let MIOperandInfo = (ops ptr_rc, simm16);
324 let EncoderMethod = "getMemEncoding";
325 let OperandType = "OPERAND_MEMORY";
328 def PtrRC : Operand<iPTR> {
329 let MIOperandInfo = (ops ptr_rc);
330 let DecoderMethod = "DecodePtrRegisterClass";
331 let ParserMatchClass = PtrRegAsmOperand;
334 // size operand of ext instruction
335 def size_ext : Operand<i32> {
336 let EncoderMethod = "getSizeExtEncoding";
337 let DecoderMethod = "DecodeExtSize";
340 // size operand of ins instruction
341 def size_ins : Operand<i32> {
342 let EncoderMethod = "getSizeInsEncoding";
343 let DecoderMethod = "DecodeInsSize";
346 // Transformation Function - get the lower 16 bits.
347 def LO16 : SDNodeXForm<imm, [{
348 return getImm(N, N->getZExtValue() & 0xFFFF);
351 // Transformation Function - get the higher 16 bits.
352 def HI16 : SDNodeXForm<imm, [{
353 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
357 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
359 // Node immediate fits as 16-bit sign extended on target immediate.
361 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
363 // Node immediate fits as 16-bit sign extended on target immediate.
365 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
367 // Node immediate fits as 15-bit sign extended on target immediate.
369 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
371 // Node immediate fits as 16-bit zero extended on target immediate.
372 // The LO16 param means that only the lower 16 bits of the node
373 // immediate are caught.
375 def immZExt16 : PatLeaf<(imm), [{
376 if (N->getValueType(0) == MVT::i32)
377 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
379 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
382 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
383 def immLow16Zero : PatLeaf<(imm), [{
384 int64_t Val = N->getSExtValue();
385 return isInt<32>(Val) && !(Val & 0xffff);
388 // shamt field must fit in 5 bits.
389 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
391 // True if (N + 1) fits in 16-bit field.
392 def immSExt16Plus1 : PatLeaf<(imm), [{
393 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
396 // Mips Address Mode! SDNode frameindex could possibily be a match
397 // since load and store instructions from stack used it.
399 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
402 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
405 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
408 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
410 //===----------------------------------------------------------------------===//
411 // Instructions specific format
412 //===----------------------------------------------------------------------===//
414 // Arithmetic and logical instructions with 3 register operands.
415 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
416 InstrItinClass Itin = NoItinerary,
417 SDPatternOperator OpNode = null_frag>:
418 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
419 !strconcat(opstr, "\t$rd, $rs, $rt"),
420 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
421 let isCommutable = isComm;
422 let isReMaterializable = 1;
425 // Arithmetic and logical instructions with 2 register operands.
426 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
427 InstrItinClass Itin = NoItinerary,
428 SDPatternOperator imm_type = null_frag,
429 SDPatternOperator OpNode = null_frag> :
430 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
431 !strconcat(opstr, "\t$rt, $rs, $imm16"),
432 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
434 let isReMaterializable = 1;
435 let TwoOperandAliasConstraint = "$rs = $rt";
438 // Arithmetic Multiply ADD/SUB
439 class MArithR<string opstr, bit isComm = 0> :
440 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
441 !strconcat(opstr, "\t$rs, $rt"), [], IIImult, FrmR, opstr> {
442 let Defs = [HI0, LO0];
443 let Uses = [HI0, LO0];
444 let isCommutable = isComm;
448 class LogicNOR<string opstr, RegisterOperand RO>:
449 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
450 !strconcat(opstr, "\t$rd, $rs, $rt"),
451 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], IIArith, FrmR, opstr> {
452 let isCommutable = 1;
456 class shift_rotate_imm<string opstr, Operand ImmOpnd,
457 RegisterOperand RO, SDPatternOperator OpNode = null_frag,
458 SDPatternOperator PF = null_frag> :
459 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
460 !strconcat(opstr, "\t$rd, $rt, $shamt"),
461 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], IIArith, FrmR, opstr>;
463 class shift_rotate_reg<string opstr, RegisterOperand RO,
464 SDPatternOperator OpNode = null_frag>:
465 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
466 !strconcat(opstr, "\t$rd, $rt, $rs"),
467 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], IIArith, FrmR, opstr>;
469 // Load Upper Imediate
470 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
471 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
472 [], IIArith, FrmI, opstr>, IsAsCheapAsAMove {
473 let neverHasSideEffects = 1;
474 let isReMaterializable = 1;
478 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
479 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
480 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
481 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
482 let DecoderMethod = "DecodeMem";
483 let canFoldAsLoad = 1;
487 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
488 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
489 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
490 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
491 let DecoderMethod = "DecodeMem";
495 // Load/Store Left/Right
496 let canFoldAsLoad = 1 in
497 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
498 InstrItinClass Itin> :
499 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
500 !strconcat(opstr, "\t$rt, $addr"),
501 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
502 let DecoderMethod = "DecodeMem";
503 string Constraints = "$src = $rt";
506 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
507 InstrItinClass Itin> :
508 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
509 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
510 let DecoderMethod = "DecodeMem";
513 // Conditional Branch
514 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
515 RegisterOperand RO> :
516 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
517 !strconcat(opstr, "\t$rs, $rt, $offset"),
518 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
521 let isTerminator = 1;
522 let hasDelaySlot = 1;
526 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
527 RegisterOperand RO> :
528 InstSE<(outs), (ins RO:$rs, opnd:$offset),
529 !strconcat(opstr, "\t$rs, $offset"),
530 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
533 let isTerminator = 1;
534 let hasDelaySlot = 1;
539 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
540 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
541 !strconcat(opstr, "\t$rd, $rs, $rt"),
542 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
545 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
547 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
548 !strconcat(opstr, "\t$rt, $rs, $imm16"),
549 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
553 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
554 SDPatternOperator targetoperator, string bopstr> :
555 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
556 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
559 let hasDelaySlot = 1;
560 let DecoderMethod = "DecodeJumpTarget";
564 // Unconditional branch
565 class UncondBranch<Instruction BEQInst> :
566 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
567 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
569 let isTerminator = 1;
571 let hasDelaySlot = 1;
572 let Predicates = [RelocPIC, HasStdEnc];
576 // Base class for indirect branch and return instruction classes.
577 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
578 class JumpFR<string opstr, RegisterOperand RO,
579 SDPatternOperator operator = null_frag>:
580 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
584 class IndirectBranch<string opstr, RegisterOperand RO> :
585 JumpFR<opstr, RO, brind> {
587 let isIndirectBranch = 1;
590 // Return instruction
591 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
593 let isCodeGenOnly = 1;
595 let hasExtraSrcRegAllocReq = 1;
598 // Jump and Link (Call)
599 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
600 class JumpLink<string opstr, DAGOperand opnd> :
601 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
602 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
603 let DecoderMethod = "DecodeJumpTarget";
606 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
607 Register RetReg, RegisterOperand ResRO = RO>:
608 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
609 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
611 class JumpLinkReg<string opstr, RegisterOperand RO>:
612 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
613 [], IIBranch, FrmR, opstr>;
615 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
616 InstSE<(outs), (ins RO:$rs, opnd:$offset),
617 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
621 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
622 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
623 class TailCall<Instruction JumpInst> :
624 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
625 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
627 class TailCallReg<RegisterOperand RO, Instruction JRInst,
628 RegisterOperand ResRO = RO> :
629 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
630 PseudoInstExpansion<(JRInst ResRO:$rs)>;
633 class BAL_BR_Pseudo<Instruction RealInst> :
634 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
635 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
637 let isTerminator = 1;
639 let hasDelaySlot = 1;
644 class SYS_FT<string opstr> :
645 InstSE<(outs), (ins uimm20:$code_),
646 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
648 class BRK_FT<string opstr> :
649 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
650 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
654 class ER_FT<string opstr> :
655 InstSE<(outs), (ins),
656 opstr, [], NoItinerary, FrmOther, opstr>;
659 class DEI_FT<string opstr, RegisterOperand RO> :
660 InstSE<(outs RO:$rt), (ins),
661 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
664 class WAIT_FT<string opstr> :
665 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
668 let hasSideEffects = 1 in
669 class SYNC_FT<string opstr> :
670 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
671 NoItinerary, FrmOther, opstr>;
673 let hasSideEffects = 1 in
674 class TEQ_FT<string opstr, RegisterOperand RO> :
675 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
676 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
679 class TEQI_FT<string opstr, RegisterOperand RO> :
680 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
681 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
683 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
684 list<Register> DefRegs> :
685 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
687 let isCommutable = 1;
689 let neverHasSideEffects = 1;
692 // Pseudo multiply/divide instruction with explicit accumulator register
694 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
695 SDPatternOperator OpNode, InstrItinClass Itin,
696 bit IsComm = 1, bit HasSideEffects = 0,
697 bit UsesCustomInserter = 0> :
698 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
699 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
700 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
701 let isCommutable = IsComm;
702 let hasSideEffects = HasSideEffects;
703 let usesCustomInserter = UsesCustomInserter;
706 // Pseudo multiply add/sub instruction with explicit accumulator register
708 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode>
709 : PseudoSE<(outs ACC64:$ac),
710 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
712 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
714 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
715 string Constraints = "$acin = $ac";
718 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
719 list<Register> DefRegs> :
720 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
721 [], itin, FrmR, opstr> {
726 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
727 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
728 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], IIHiLo>;
730 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
731 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR,
734 let neverHasSideEffects = 1;
737 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
738 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
739 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))], IIHiLo>;
741 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
742 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo,
745 let neverHasSideEffects = 1;
748 class EffectiveAddress<string opstr, RegisterOperand RO> :
749 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
750 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI> {
751 let isCodeGenOnly = 1;
752 let DecoderMethod = "DecodeMem";
755 // Count Leading Ones/Zeros in Word
756 class CountLeading0<string opstr, RegisterOperand RO>:
757 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
758 [(set RO:$rd, (ctlz RO:$rs))], IIArith, FrmR, opstr>,
759 Requires<[HasBitCount, HasStdEnc]>;
761 class CountLeading1<string opstr, RegisterOperand RO>:
762 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
763 [(set RO:$rd, (ctlz (not RO:$rs)))], IIArith, FrmR, opstr>,
764 Requires<[HasBitCount, HasStdEnc]>;
767 // Sign Extend in Register.
768 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO> :
769 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
770 [(set RO:$rd, (sext_inreg RO:$rt, vt))], IIseb, FrmR, opstr> {
771 let Predicates = [HasSEInReg, HasStdEnc];
775 class SubwordSwap<string opstr, RegisterOperand RO>:
776 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
777 NoItinerary, FrmR, opstr> {
778 let Predicates = [HasSwap, HasStdEnc];
779 let neverHasSideEffects = 1;
783 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
784 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
788 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
789 SDPatternOperator Op = null_frag>:
790 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
791 !strconcat(opstr, " $rt, $rs, $pos, $size"),
792 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
794 let Predicates = [HasMips32r2, HasStdEnc];
797 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
798 SDPatternOperator Op = null_frag>:
799 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
800 !strconcat(opstr, " $rt, $rs, $pos, $size"),
801 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
802 NoItinerary, FrmR, opstr> {
803 let Predicates = [HasMips32r2, HasStdEnc];
804 let Constraints = "$src = $rt";
807 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
808 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
809 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
810 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
812 // Atomic Compare & Swap.
813 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
814 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
815 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
817 class LLBase<string opstr, RegisterOperand RO> :
818 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
819 [], NoItinerary, FrmI> {
820 let DecoderMethod = "DecodeMem";
824 class SCBase<string opstr, RegisterOperand RO> :
825 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
826 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
827 let DecoderMethod = "DecodeMem";
829 let Constraints = "$rt = $dst";
832 class MFC3OP<string asmstr, RegisterOperand RO> :
833 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
834 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
836 class TrapBase<Instruction RealInst>
837 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
838 PseudoInstExpansion<(RealInst 0, 0)> {
840 let isTerminator = 1;
841 let isCodeGenOnly = 1;
844 //===----------------------------------------------------------------------===//
845 // Pseudo instructions
846 //===----------------------------------------------------------------------===//
849 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
850 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
852 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
853 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
854 [(callseq_start timm:$amt)]>;
855 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
856 [(callseq_end timm:$amt1, timm:$amt2)]>;
859 let usesCustomInserter = 1 in {
860 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
861 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
862 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
863 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
864 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
865 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
866 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
867 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
868 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
869 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
870 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
871 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
872 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
873 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
874 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
875 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
876 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
877 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
879 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
880 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
881 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
883 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
884 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
885 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
888 /// Pseudo instructions for loading and storing accumulator registers.
889 let isPseudo = 1, isCodeGenOnly = 1 in {
890 def LOAD_ACC64 : Load<"", ACC64>;
891 def STORE_ACC64 : Store<"", ACC64>;
894 //===----------------------------------------------------------------------===//
895 // Instruction definition
896 //===----------------------------------------------------------------------===//
897 //===----------------------------------------------------------------------===//
898 // MipsI Instructions
899 //===----------------------------------------------------------------------===//
901 /// Arithmetic Instructions (ALU Immediate)
902 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, IIArith, immSExt16,
904 ADDI_FM<0x9>, IsAsCheapAsAMove;
905 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
906 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
908 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
910 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, IILogic, immZExt16,
913 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, IILogic, immZExt16,
916 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, IILogic, immZExt16,
919 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
921 /// Arithmetic Instructions (3-Operand, R-Type)
922 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, IIArith, add>,
924 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, IIArith, sub>,
926 let Defs = [HI0, LO0] in
927 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, IIImul, mul>,
929 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
930 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
931 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
932 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
933 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, IILogic, and>,
935 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, IILogic, or>,
937 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, IILogic, xor>,
939 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
941 /// Shift Instructions
942 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, shl, immZExt5>,
944 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, srl, immZExt5>,
946 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, sra, immZExt5>,
948 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, shl>, SRLV_FM<4, 0>;
949 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, srl>, SRLV_FM<6, 0>;
950 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, sra>, SRLV_FM<7, 0>;
952 // Rotate Instructions
953 let Predicates = [HasMips32r2, HasStdEnc] in {
954 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, rotr,
957 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, rotr>,
961 /// Load and Store Instructions
963 def LB : Load<"lb", GPR32Opnd, sextloadi8, IILoad>, MMRel, LW_FM<0x20>;
964 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, IILoad, addrDefault>, MMRel,
966 def LH : Load<"lh", GPR32Opnd, sextloadi16, IILoad, addrDefault>, MMRel,
968 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, IILoad>, MMRel, LW_FM<0x25>;
969 def LW : Load<"lw", GPR32Opnd, load, IILoad, addrDefault>, MMRel,
971 def SB : Store<"sb", GPR32Opnd, truncstorei8, IIStore>, MMRel, LW_FM<0x28>;
972 def SH : Store<"sh", GPR32Opnd, truncstorei16, IIStore>, MMRel, LW_FM<0x29>;
973 def SW : Store<"sw", GPR32Opnd, store, IIStore>, MMRel, LW_FM<0x2b>;
975 /// load/store left/right
976 let Predicates = [NotInMicroMips] in {
977 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, IILoad>, LW_FM<0x22>;
978 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, IILoad>, LW_FM<0x26>;
979 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, IIStore>, LW_FM<0x2a>;
980 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, IIStore>, LW_FM<0x2e>;
983 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
984 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
985 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
986 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
987 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
988 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
989 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
991 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
992 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
993 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
994 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
995 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
996 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
998 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
999 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1000 def TRAP : TrapBase<BREAK>;
1002 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1003 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1005 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1006 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1008 def WAIT : MMRel, WAIT_FT<"wait">, WAIT_FM;
1010 /// Load-linked, Store-conditional
1011 let Predicates = [NotInMicroMips] in {
1012 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1013 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1016 /// Jump and Branch Instructions
1017 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1018 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1019 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1020 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1021 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1022 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1024 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1026 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1028 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1030 def B : UncondBranch<BEQ>;
1032 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1033 def JALR : MMRel, JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1034 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1035 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1036 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1037 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1038 def TAILCALL : TailCall<J>;
1039 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1041 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1043 // Exception handling related node and instructions.
1044 // The conversion sequence is:
1045 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1046 // MIPSeh_return -> (stack change + indirect branch)
1048 // MIPSeh_return takes the place of regular return instruction
1049 // but takes two arguments (V1, V0) which are used for storing
1050 // the offset and return address respectively.
1051 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1053 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1054 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1056 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1057 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1058 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1059 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1061 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1064 /// Multiply and Divide Instructions.
1065 def MULT : MMRel, Mult<"mult", IIImult, GPR32Opnd, [HI0, LO0]>,
1067 def MULTu : MMRel, Mult<"multu", IIImult, GPR32Opnd, [HI0, LO0]>,
1069 def SDIV : MMRel, Div<"div", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1071 def UDIV : MMRel, Div<"divu", IIIdiv, GPR32Opnd, [HI0, LO0]>,
1074 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1075 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1076 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1077 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1079 /// Sign Ext In Register Instructions.
1080 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd>, SEB_FM<0x10, 0x20>;
1081 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd>, SEB_FM<0x18, 0x20>;
1084 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1085 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1087 /// Word Swap Bytes Within Halfwords
1088 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1091 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1093 // FrameIndexes are legalized when they are operands from load/store
1094 // instructions. The same not happens for stack address copies, so an
1095 // add op with mem ComplexPattern is used and the stack address copy
1096 // can be matched. It's similar to Sparc LEA_ADDRi
1097 def LEA_ADDiu : EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1100 def MADD : MMRel, MArithR<"madd", 1>, MULT_FM<0x1c, 0>;
1101 def MADDU : MMRel, MArithR<"maddu", 1>, MULT_FM<0x1c, 1>;
1102 def MSUB : MMRel, MArithR<"msub">, MULT_FM<0x1c, 4>;
1103 def MSUBU : MMRel, MArithR<"msubu">, MULT_FM<0x1c, 5>;
1105 let Predicates = [HasStdEnc, NotDSP] in {
1106 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, IIImult>;
1107 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, IIImult>;
1108 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1109 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1110 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1111 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd>;
1112 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu>;
1113 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub>;
1114 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu>;
1117 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, IIIdiv,
1119 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, IIIdiv,
1122 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1124 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1125 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1127 /// Move Control Registers From/To CPU Registers
1128 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1129 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1130 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1131 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1133 //===----------------------------------------------------------------------===//
1134 // Instruction aliases
1135 //===----------------------------------------------------------------------===//
1136 def : InstAlias<"move $dst, $src",
1137 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1138 Requires<[NotMips64]>;
1139 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1140 def : InstAlias<"addu $rs, $rt, $imm",
1141 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1142 def : InstAlias<"add $rs, $rt, $imm",
1143 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1144 def : InstAlias<"and $rs, $rt, $imm",
1145 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1146 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1147 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1148 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1149 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1150 def : InstAlias<"not $rt, $rs",
1151 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1152 def : InstAlias<"neg $rt, $rs",
1153 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1154 def : InstAlias<"negu $rt, $rs",
1155 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1156 def : InstAlias<"slt $rs, $rt, $imm",
1157 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1158 def : InstAlias<"xor $rs, $rt, $imm",
1159 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1160 def : InstAlias<"or $rs, $rt, $imm",
1161 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1162 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1163 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1164 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1165 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1166 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1167 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1168 def : InstAlias<"bnez $rs,$offset",
1169 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1170 def : InstAlias<"beqz $rs,$offset",
1171 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1172 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1174 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1175 def : InstAlias<"break", (BREAK 0, 0), 1>;
1176 def : InstAlias<"ei", (EI ZERO), 1>;
1177 def : InstAlias<"di", (DI ZERO), 1>;
1179 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1180 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1181 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1182 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1183 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1184 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1185 def : InstAlias<"sub, $rd, $rs, $imm",
1186 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1187 def : InstAlias<"subu, $rd, $rs, $imm",
1188 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1190 //===----------------------------------------------------------------------===//
1191 // Assembler Pseudo Instructions
1192 //===----------------------------------------------------------------------===//
1194 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1195 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1196 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1197 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1199 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1200 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1201 !strconcat(instr_asm, "\t$rt, $addr")> ;
1202 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1204 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1205 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1206 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1207 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1209 //===----------------------------------------------------------------------===//
1210 // Arbitrary patterns that map to one or more instructions
1211 //===----------------------------------------------------------------------===//
1213 // Load/store pattern templates.
1214 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1215 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1217 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1218 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1221 def : MipsPat<(i32 immSExt16:$in),
1222 (ADDiu ZERO, imm:$in)>;
1223 def : MipsPat<(i32 immZExt16:$in),
1224 (ORi ZERO, imm:$in)>;
1225 def : MipsPat<(i32 immLow16Zero:$in),
1226 (LUi (HI16 imm:$in))>;
1228 // Arbitrary immediates
1229 def : MipsPat<(i32 imm:$imm),
1230 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1232 // Carry MipsPatterns
1233 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1234 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1235 let Predicates = [HasStdEnc, NotDSP] in {
1236 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1237 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1238 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1239 (ADDiu GPR32:$src, imm:$imm)>;
1243 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1244 (JAL tglobaladdr:$dst)>;
1245 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1246 (JAL texternalsym:$dst)>;
1247 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1248 // (JALR GPR32:$dst)>;
1251 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1252 (TAILCALL tglobaladdr:$dst)>;
1253 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1254 (TAILCALL texternalsym:$dst)>;
1256 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1257 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1258 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1259 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1260 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1261 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1263 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1264 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1265 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1266 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1267 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1268 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1270 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1271 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1272 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1273 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1274 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1275 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1276 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1277 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1278 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1279 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1282 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1283 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1284 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1285 (ADDiu GPR32:$gp, tconstpool:$in)>;
1288 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1289 MipsPat<(MipsWrapper RC:$gp, node:$in),
1290 (ADDiuOp RC:$gp, node:$in)>;
1292 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1293 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1294 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1295 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1296 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1297 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1299 // Mips does not have "not", so we expand our way
1300 def : MipsPat<(not GPR32:$in),
1301 (NOR GPR32Opnd:$in, ZERO)>;
1304 let Predicates = [HasStdEnc] in {
1305 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1306 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1307 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1311 let Predicates = [HasStdEnc] in
1312 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1315 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1316 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1317 Instruction SLTiuOp, Register ZEROReg> {
1318 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1319 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1320 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1321 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1323 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1324 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1325 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1326 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1327 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1328 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1329 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1330 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1331 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1332 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1333 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1334 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1336 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1337 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1338 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1339 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1341 def : MipsPat<(brcond RC:$cond, bb:$dst),
1342 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1345 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1347 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1348 (BLEZ i32:$lhs, bb:$dst)>;
1349 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1350 (BGEZ i32:$lhs, bb:$dst)>;
1353 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1354 Instruction SLTuOp, Register ZEROReg> {
1355 def : MipsPat<(seteq RC:$lhs, 0),
1356 (SLTiuOp RC:$lhs, 1)>;
1357 def : MipsPat<(setne RC:$lhs, 0),
1358 (SLTuOp ZEROReg, RC:$lhs)>;
1359 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1360 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1361 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1362 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1365 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1366 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1367 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1368 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1369 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1372 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1373 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1374 (SLTOp RC:$rhs, RC:$lhs)>;
1375 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1376 (SLTuOp RC:$rhs, RC:$lhs)>;
1379 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1380 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1381 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1382 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1383 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1386 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1387 Instruction SLTiuOp> {
1388 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1389 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1390 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1391 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1394 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1395 defm : SetlePats<GPR32, SLT, SLTu>;
1396 defm : SetgtPats<GPR32, SLT, SLTu>;
1397 defm : SetgePats<GPR32, SLT, SLTu>;
1398 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1401 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1403 // Load halfword/word patterns.
1404 let AddedComplexity = 40 in {
1405 let Predicates = [HasStdEnc] in {
1406 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1407 def : LoadRegImmPat<LH, i32, sextloadi16>;
1408 def : LoadRegImmPat<LW, i32, load>;
1412 //===----------------------------------------------------------------------===//
1413 // Floating Point Support
1414 //===----------------------------------------------------------------------===//
1416 include "MipsInstrFPU.td"
1417 include "Mips64InstrInfo.td"
1418 include "MipsCondMov.td"
1423 include "Mips16InstrFormats.td"
1424 include "Mips16InstrInfo.td"
1427 include "MipsDSPInstrFormats.td"
1428 include "MipsDSPInstrInfo.td"
1431 include "MipsMSAInstrFormats.td"
1432 include "MipsMSAInstrInfo.td"
1435 include "MicroMipsInstrFormats.td"
1436 include "MicroMipsInstrInfo.td"