1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone, [SDNPHasChain, SDNPOptInGlue]>;
77 // These are target-independent nodes, but have target-specific formats.
78 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
79 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
80 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
81 [SDNPHasChain, SDNPSideEffect,
82 SDNPOptInGlue, SDNPOutGlue]>;
85 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
86 [SDNPOptInGlue, SDNPOutGlue]>;
87 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
88 [SDNPOptInGlue, SDNPOutGlue]>;
89 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
90 [SDNPOptInGlue, SDNPOutGlue]>;
91 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
92 [SDNPOptInGlue, SDNPOutGlue]>;
95 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
97 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
100 // Target constant nodes that are not part of any isel patterns and remain
101 // unchanged can cause instructions with illegal operands to be emitted.
102 // Wrapper node patterns give the instruction selector a chance to replace
103 // target constant nodes that would otherwise remain unchanged with ADDiu
104 // nodes. Without these wrapper node patterns, the following conditional move
105 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
107 // movn %got(d)($gp), %got(c)($gp), $4
108 // This instruction is illegal since movn can take only register operands.
110 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
112 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
114 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
115 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
117 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
118 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
119 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
120 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
121 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
122 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
123 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
124 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
125 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
126 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
127 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
128 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
129 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
130 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
131 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
132 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
134 //===----------------------------------------------------------------------===//
135 // Mips Instruction Predicate Definitions.
136 //===----------------------------------------------------------------------===//
137 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
138 AssemblerPredicate<"FeatureSEInReg">;
139 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
140 AssemblerPredicate<"FeatureBitCount">;
141 def HasSwap : Predicate<"Subtarget.hasSwap()">,
142 AssemblerPredicate<"FeatureSwap">;
143 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
144 AssemblerPredicate<"FeatureCondMov">;
145 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
146 AssemblerPredicate<"FeatureFPIdx">;
147 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
148 AssemblerPredicate<"FeatureMips32">;
149 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
150 AssemblerPredicate<"FeatureMips32r2">;
151 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
152 AssemblerPredicate<"FeatureMips64">;
153 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
154 AssemblerPredicate<"!FeatureMips64">;
155 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
156 AssemblerPredicate<"FeatureMips64r2">;
157 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
158 AssemblerPredicate<"FeatureN64">;
159 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
160 AssemblerPredicate<"!FeatureN64">;
161 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
162 AssemblerPredicate<"FeatureMips16">;
163 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
164 AssemblerPredicate<"FeatureMips32">;
165 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
166 AssemblerPredicate<"FeatureMips32">;
167 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
168 AssemblerPredicate<"FeatureMips32">;
169 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
170 AssemblerPredicate<"!FeatureMips16">;
172 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
173 let Predicates = [HasStdEnc];
177 bit isCommutable = 1;
194 bit isTerminator = 1;
197 bit hasExtraSrcRegAllocReq = 1;
198 bit isCodeGenOnly = 1;
201 class IsAsCheapAsAMove {
202 bit isAsCheapAsAMove = 1;
205 class NeverHasSideEffects {
206 bit neverHasSideEffects = 1;
209 //===----------------------------------------------------------------------===//
210 // Instruction format superclass
211 //===----------------------------------------------------------------------===//
213 include "MipsInstrFormats.td"
215 //===----------------------------------------------------------------------===//
216 // Mips Operand, Complex Patterns and Transformations Definitions.
217 //===----------------------------------------------------------------------===//
219 // Instruction operand types
220 def jmptarget : Operand<OtherVT> {
221 let EncoderMethod = "getJumpTargetOpValue";
223 def brtarget : Operand<OtherVT> {
224 let EncoderMethod = "getBranchTargetOpValue";
225 let OperandType = "OPERAND_PCREL";
226 let DecoderMethod = "DecodeBranchTarget";
228 def calltarget : Operand<iPTR> {
229 let EncoderMethod = "getJumpTargetOpValue";
231 def calltarget64: Operand<i64>;
232 def simm16 : Operand<i32> {
233 let DecoderMethod= "DecodeSimm16";
235 def simm16_64 : Operand<i64>;
236 def shamt : Operand<i32>;
239 def uimm16 : Operand<i32> {
240 let PrintMethod = "printUnsignedImm";
243 def MipsMemAsmOperand : AsmOperandClass {
245 let ParserMethod = "parseMemOperand";
249 def mem : Operand<i32> {
250 let PrintMethod = "printMemOperand";
251 let MIOperandInfo = (ops CPURegs, simm16);
252 let EncoderMethod = "getMemEncoding";
253 let ParserMatchClass = MipsMemAsmOperand;
256 def mem64 : Operand<i64> {
257 let PrintMethod = "printMemOperand";
258 let MIOperandInfo = (ops CPU64Regs, simm16_64);
259 let EncoderMethod = "getMemEncoding";
260 let ParserMatchClass = MipsMemAsmOperand;
263 def mem_ea : Operand<i32> {
264 let PrintMethod = "printMemOperandEA";
265 let MIOperandInfo = (ops CPURegs, simm16);
266 let EncoderMethod = "getMemEncoding";
269 def mem_ea_64 : Operand<i64> {
270 let PrintMethod = "printMemOperandEA";
271 let MIOperandInfo = (ops CPU64Regs, simm16_64);
272 let EncoderMethod = "getMemEncoding";
275 // size operand of ext instruction
276 def size_ext : Operand<i32> {
277 let EncoderMethod = "getSizeExtEncoding";
278 let DecoderMethod = "DecodeExtSize";
281 // size operand of ins instruction
282 def size_ins : Operand<i32> {
283 let EncoderMethod = "getSizeInsEncoding";
284 let DecoderMethod = "DecodeInsSize";
287 // Transformation Function - get the lower 16 bits.
288 def LO16 : SDNodeXForm<imm, [{
289 return getImm(N, N->getZExtValue() & 0xFFFF);
292 // Transformation Function - get the higher 16 bits.
293 def HI16 : SDNodeXForm<imm, [{
294 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
297 // Node immediate fits as 16-bit sign extended on target immediate.
299 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
301 // Node immediate fits as 16-bit zero extended on target immediate.
302 // The LO16 param means that only the lower 16 bits of the node
303 // immediate are caught.
305 def immZExt16 : PatLeaf<(imm), [{
306 if (N->getValueType(0) == MVT::i32)
307 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
309 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
312 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
313 def immLow16Zero : PatLeaf<(imm), [{
314 int64_t Val = N->getSExtValue();
315 return isInt<32>(Val) && !(Val & 0xffff);
318 // shamt field must fit in 5 bits.
319 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
321 // Mips Address Mode! SDNode frameindex could possibily be a match
322 // since load and store instructions from stack used it.
324 ComplexPattern<iPTR, 2, "SelectAddr", [frameindex], [SDNPWantParent]>;
326 //===----------------------------------------------------------------------===//
327 // Instructions specific format
328 //===----------------------------------------------------------------------===//
330 /// Move Control Registers From/To CPU Registers
331 def MFC0_3OP : MFC3OP<0x10, 0, (outs CPURegs:$rt),
332 (ins CPURegs:$rd, uimm16:$sel),"mfc0\t$rt, $rd, $sel">;
333 def : InstAlias<"mfc0 $rt, $rd", (MFC0_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
335 def MTC0_3OP : MFC3OP<0x10, 4, (outs CPURegs:$rd, uimm16:$sel),
336 (ins CPURegs:$rt),"mtc0\t$rt, $rd, $sel">;
337 def : InstAlias<"mtc0 $rt, $rd", (MTC0_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
339 def MFC2_3OP : MFC3OP<0x12, 0, (outs CPURegs:$rt),
340 (ins CPURegs:$rd, uimm16:$sel),"mfc2\t$rt, $rd, $sel">;
341 def : InstAlias<"mfc2 $rt, $rd", (MFC2_3OP CPURegs:$rt, CPURegs:$rd, 0)>;
343 def MTC2_3OP : MFC3OP<0x12, 4, (outs CPURegs:$rd, uimm16:$sel),
344 (ins CPURegs:$rt),"mtc2\t$rt, $rd, $sel">;
345 def : InstAlias<"mtc2 $rt, $rd", (MTC2_3OP CPURegs:$rd, 0, CPURegs:$rt)>;
347 // Arithmetic and logical instructions with 3 register operands.
348 class ArithLogicR<string opstr, RegisterClass RC, bit isComm = 0,
349 InstrItinClass Itin = NoItinerary,
350 SDPatternOperator OpNode = null_frag>:
351 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
352 !strconcat(opstr, "\t$rd, $rs, $rt"),
353 [(set RC:$rd, (OpNode RC:$rs, RC:$rt))], Itin, FrmR> {
354 let isCommutable = isComm;
355 let isReMaterializable = 1;
358 // Arithmetic and logical instructions with 2 register operands.
359 class ArithLogicI<string opstr, Operand Od, RegisterClass RC,
360 SDPatternOperator imm_type = null_frag,
361 SDPatternOperator OpNode = null_frag> :
362 InstSE<(outs RC:$rt), (ins RC:$rs, Od:$imm16),
363 !strconcat(opstr, "\t$rt, $rs, $imm16"),
364 [(set RC:$rt, (OpNode RC:$rs, imm_type:$imm16))], IIAlu, FrmI> {
365 let isReMaterializable = 1;
368 // Arithmetic Multiply ADD/SUB
369 let rd = 0, shamt = 0, Defs = [HI, LO], Uses = [HI, LO] in
370 class MArithR<bits<6> func, string instr_asm, SDNode op, bit isComm = 0> :
371 FR<0x1c, func, (outs), (ins CPURegs:$rs, CPURegs:$rt),
372 !strconcat(instr_asm, "\t$rs, $rt"),
373 [(op CPURegs:$rs, CPURegs:$rt, LO, HI)], IIImul> {
376 let isCommutable = isComm;
380 class LogicNOR<bits<6> op, bits<6> func, string instr_asm, RegisterClass RC>:
381 FR<op, func, (outs RC:$rd), (ins RC:$rs, RC:$rt),
382 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
383 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu> {
385 let isCommutable = 1;
389 class shift_rotate_imm<string opstr, PatFrag PF, Operand ImmOpnd,
390 RegisterClass RC, SDPatternOperator OpNode> :
391 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
392 !strconcat(opstr, "\t$rd, $rt, $shamt"),
393 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
395 // 32-bit shift instructions.
396 class shift_rotate_imm32<string opstr, SDPatternOperator OpNode = null_frag> :
397 shift_rotate_imm<opstr, immZExt5, shamt, CPURegs, OpNode>;
399 class shift_rotate_reg<string opstr, SDNode OpNode, RegisterClass RC>:
400 InstSE<(outs RC:$rd), (ins CPURegs:$rs, RC:$rt),
401 !strconcat(opstr, "\t$rd, $rt, $rs"),
402 [(set RC:$rd, (OpNode RC:$rt, CPURegs:$rs))], IIAlu, FrmR>;
404 // Load Upper Imediate
405 class LoadUpper<bits<6> op, string instr_asm, RegisterClass RC, Operand Imm>:
406 FI<op, (outs RC:$rt), (ins Imm:$imm16),
407 !strconcat(instr_asm, "\t$rt, $imm16"), [], IIAlu>, IsAsCheapAsAMove {
409 let neverHasSideEffects = 1;
410 let isReMaterializable = 1;
413 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
414 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
416 let Inst{25-21} = addr{20-16};
417 let Inst{15-0} = addr{15-0};
418 let DecoderMethod = "DecodeMem";
422 let canFoldAsLoad = 1 in
423 class LoadM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
424 Operand MemOpnd, bit Pseudo>:
425 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr),
426 !strconcat(instr_asm, "\t$rt, $addr"),
427 [(set RC:$rt, (OpNode addr:$addr))], IILoad> {
428 let isPseudo = Pseudo;
431 class StoreM<bits<6> op, string instr_asm, PatFrag OpNode, RegisterClass RC,
432 Operand MemOpnd, bit Pseudo>:
433 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
434 !strconcat(instr_asm, "\t$rt, $addr"),
435 [(OpNode RC:$rt, addr:$addr)], IIStore> {
436 let isPseudo = Pseudo;
440 multiclass LoadM32<bits<6> op, string instr_asm, PatFrag OpNode,
442 def #NAME# : LoadM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
443 Requires<[NotN64, HasStdEnc]>;
444 def _P8 : LoadM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
445 Requires<[IsN64, HasStdEnc]> {
446 let DecoderNamespace = "Mips64";
447 let isCodeGenOnly = 1;
452 multiclass LoadM64<bits<6> op, string instr_asm, PatFrag OpNode,
454 def #NAME# : LoadM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
455 Requires<[NotN64, HasStdEnc]>;
456 def _P8 : LoadM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
457 Requires<[IsN64, HasStdEnc]> {
458 let DecoderNamespace = "Mips64";
459 let isCodeGenOnly = 1;
464 multiclass StoreM32<bits<6> op, string instr_asm, PatFrag OpNode,
466 def #NAME# : StoreM<op, instr_asm, OpNode, CPURegs, mem, Pseudo>,
467 Requires<[NotN64, HasStdEnc]>;
468 def _P8 : StoreM<op, instr_asm, OpNode, CPURegs, mem64, Pseudo>,
469 Requires<[IsN64, HasStdEnc]> {
470 let DecoderNamespace = "Mips64";
471 let isCodeGenOnly = 1;
476 multiclass StoreM64<bits<6> op, string instr_asm, PatFrag OpNode,
478 def #NAME# : StoreM<op, instr_asm, OpNode, CPU64Regs, mem, Pseudo>,
479 Requires<[NotN64, HasStdEnc]>;
480 def _P8 : StoreM<op, instr_asm, OpNode, CPU64Regs, mem64, Pseudo>,
481 Requires<[IsN64, HasStdEnc]> {
482 let DecoderNamespace = "Mips64";
483 let isCodeGenOnly = 1;
487 // Load/Store Left/Right
488 let canFoldAsLoad = 1 in
489 class LoadLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
490 RegisterClass RC, Operand MemOpnd> :
491 FMem<op, (outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
492 !strconcat(instr_asm, "\t$rt, $addr"),
493 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], IILoad> {
494 string Constraints = "$src = $rt";
497 class StoreLeftRight<bits<6> op, string instr_asm, SDNode OpNode,
498 RegisterClass RC, Operand MemOpnd>:
499 FMem<op, (outs), (ins RC:$rt, MemOpnd:$addr),
500 !strconcat(instr_asm, "\t$rt, $addr"), [(OpNode RC:$rt, addr:$addr)],
503 // 32-bit load left/right.
504 multiclass LoadLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
505 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
506 Requires<[NotN64, HasStdEnc]>;
507 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
508 Requires<[IsN64, HasStdEnc]> {
509 let DecoderNamespace = "Mips64";
510 let isCodeGenOnly = 1;
514 // 64-bit load left/right.
515 multiclass LoadLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
516 def #NAME# : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
517 Requires<[NotN64, HasStdEnc]>;
518 def _P8 : LoadLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
519 Requires<[IsN64, HasStdEnc]> {
520 let DecoderNamespace = "Mips64";
521 let isCodeGenOnly = 1;
525 // 32-bit store left/right.
526 multiclass StoreLeftRightM32<bits<6> op, string instr_asm, SDNode OpNode> {
527 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem>,
528 Requires<[NotN64, HasStdEnc]>;
529 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPURegs, mem64>,
530 Requires<[IsN64, HasStdEnc]> {
531 let DecoderNamespace = "Mips64";
532 let isCodeGenOnly = 1;
536 // 64-bit store left/right.
537 multiclass StoreLeftRightM64<bits<6> op, string instr_asm, SDNode OpNode> {
538 def #NAME# : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem>,
539 Requires<[NotN64, HasStdEnc]>;
540 def _P8 : StoreLeftRight<op, instr_asm, OpNode, CPU64Regs, mem64>,
541 Requires<[IsN64, HasStdEnc]> {
542 let DecoderNamespace = "Mips64";
543 let isCodeGenOnly = 1;
547 // Conditional Branch
548 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
549 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
550 !strconcat(opstr, "\t$rs, $rt, $offset"),
551 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
554 let isTerminator = 1;
555 let hasDelaySlot = 1;
559 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
560 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
561 !strconcat(opstr, "\t$rs, $offset"),
562 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
564 let isTerminator = 1;
565 let hasDelaySlot = 1;
570 class SetCC_R<bits<6> op, bits<6> func, string instr_asm, PatFrag cond_op,
572 FR<op, func, (outs CPURegs:$rd), (ins RC:$rs, RC:$rt),
573 !strconcat(instr_asm, "\t$rd, $rs, $rt"),
574 [(set CPURegs:$rd, (cond_op RC:$rs, RC:$rt))],
579 class SetCC_I<bits<6> op, string instr_asm, PatFrag cond_op, Operand Od,
580 PatLeaf imm_type, RegisterClass RC>:
581 FI<op, (outs CPURegs:$rt), (ins RC:$rs, Od:$imm16),
582 !strconcat(instr_asm, "\t$rt, $rs, $imm16"),
583 [(set CPURegs:$rt, (cond_op RC:$rs, imm_type:$imm16))],
587 class JumpFJ<bits<6> op, DAGOperand opnd, string instr_asm,
588 SDPatternOperator operator, SDPatternOperator targetoperator>:
589 FJ<op, (outs), (ins opnd:$target), !strconcat(instr_asm, "\t$target"),
590 [(operator targetoperator:$target)], IIBranch> {
593 let hasDelaySlot = 1;
594 let DecoderMethod = "DecodeJumpTarget";
598 // Unconditional branch
599 class UncondBranch<string opstr> :
600 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
601 [(br bb:$offset)], IIBranch, FrmI> {
603 let isTerminator = 1;
605 let hasDelaySlot = 1;
606 let Predicates = [RelocPIC, HasStdEnc];
610 // Base class for indirect branch and return instruction classes.
611 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
612 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
613 FR<0, 0x8, (outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch> {
620 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
622 let isIndirectBranch = 1;
625 // Return instruction
626 class RetBase<RegisterClass RC>: JumpFR<RC> {
628 let isCodeGenOnly = 1;
630 let hasExtraSrcRegAllocReq = 1;
633 // Jump and Link (Call)
634 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
635 class JumpLink<bits<6> op, string instr_asm>:
636 FJ<op, (outs), (ins calltarget:$target),
637 !strconcat(instr_asm, "\t$target"), [(MipsJmpLink imm:$target)],
639 let DecoderMethod = "DecodeJumpTarget";
642 class JumpLinkReg<bits<6> op, bits<6> func, string instr_asm,
644 FR<op, func, (outs), (ins RC:$rs),
645 !strconcat(instr_asm, "\t$rs"), [(MipsJmpLink RC:$rs)], IIBranch> {
651 class BranchLink<string instr_asm, bits<5> _rt, RegisterClass RC>:
652 FI<0x1, (outs), (ins RC:$rs, brtarget:$imm16),
653 !strconcat(instr_asm, "\t$rs, $imm16"), [], IIBranch> {
659 class Mult<bits<6> func, string instr_asm, InstrItinClass itin,
660 RegisterClass RC, list<Register> DefRegs>:
661 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
662 !strconcat(instr_asm, "\t$rs, $rt"), [], itin> {
665 let isCommutable = 1;
667 let neverHasSideEffects = 1;
670 class Mult32<bits<6> func, string instr_asm, InstrItinClass itin>:
671 Mult<func, instr_asm, itin, CPURegs, [HI, LO]>;
673 class Div<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin,
674 RegisterClass RC, list<Register> DefRegs>:
675 FR<0x00, func, (outs), (ins RC:$rs, RC:$rt),
676 !strconcat(instr_asm, "\t$$zero, $rs, $rt"),
677 [(op RC:$rs, RC:$rt)], itin> {
683 class Div32<SDNode op, bits<6> func, string instr_asm, InstrItinClass itin>:
684 Div<op, func, instr_asm, itin, CPURegs, [HI, LO]>;
687 class MoveFromLOHI<bits<6> func, string instr_asm, RegisterClass RC,
688 list<Register> UseRegs>:
689 FR<0x00, func, (outs RC:$rd), (ins),
690 !strconcat(instr_asm, "\t$rd"), [], IIHiLo> {
695 let neverHasSideEffects = 1;
698 class MoveToLOHI<bits<6> func, string instr_asm, RegisterClass RC,
699 list<Register> DefRegs>:
700 FR<0x00, func, (outs), (ins RC:$rs),
701 !strconcat(instr_asm, "\t$rs"), [], IIHiLo> {
706 let neverHasSideEffects = 1;
709 class EffectiveAddress<bits<6> opc, string instr_asm, RegisterClass RC, Operand Mem> :
710 FMem<opc, (outs RC:$rt), (ins Mem:$addr),
711 instr_asm, [(set RC:$rt, addr:$addr)], IIAlu> {
712 let isCodeGenOnly = 1;
715 // Count Leading Ones/Zeros in Word
716 class CountLeading0<bits<6> func, string instr_asm, RegisterClass RC>:
717 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
718 !strconcat(instr_asm, "\t$rd, $rs"),
719 [(set RC:$rd, (ctlz RC:$rs))], IIAlu>,
720 Requires<[HasBitCount, HasStdEnc]> {
725 class CountLeading1<bits<6> func, string instr_asm, RegisterClass RC>:
726 FR<0x1c, func, (outs RC:$rd), (ins RC:$rs),
727 !strconcat(instr_asm, "\t$rd, $rs"),
728 [(set RC:$rd, (ctlz (not RC:$rs)))], IIAlu>,
729 Requires<[HasBitCount, HasStdEnc]> {
734 // Sign Extend in Register.
735 class SignExtInReg<bits<5> sa, string instr_asm, ValueType vt,
737 FR<0x1f, 0x20, (outs RC:$rd), (ins RC:$rt),
738 !strconcat(instr_asm, "\t$rd, $rt"),
739 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary> {
742 let Predicates = [HasSEInReg, HasStdEnc];
746 class SubwordSwap<bits<6> func, bits<5> sa, string instr_asm, RegisterClass RC>:
747 FR<0x1f, func, (outs RC:$rd), (ins RC:$rt),
748 !strconcat(instr_asm, "\t$rd, $rt"), [], NoItinerary> {
751 let Predicates = [HasSwap, HasStdEnc];
752 let neverHasSideEffects = 1;
756 class ReadHardware<RegisterClass CPURegClass, RegisterClass HWRegClass>
757 : FR<0x1f, 0x3b, (outs CPURegClass:$rt), (ins HWRegClass:$rd),
758 "rdhwr\t$rt, $rd", [], IIAlu> {
764 class ExtBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
765 FR<0x1f, _funct, (outs RC:$rt), (ins RC:$rs, uimm16:$pos, size_ext:$sz),
766 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
767 [(set RC:$rt, (MipsExt RC:$rs, imm:$pos, imm:$sz))], NoItinerary> {
772 let Predicates = [HasMips32r2, HasStdEnc];
775 class InsBase<bits<6> _funct, string instr_asm, RegisterClass RC>:
776 FR<0x1f, _funct, (outs RC:$rt),
777 (ins RC:$rs, uimm16:$pos, size_ins:$sz, RC:$src),
778 !strconcat(instr_asm, " $rt, $rs, $pos, $sz"),
779 [(set RC:$rt, (MipsIns RC:$rs, imm:$pos, imm:$sz, RC:$src))],
785 let Predicates = [HasMips32r2, HasStdEnc];
786 let Constraints = "$src = $rt";
789 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
790 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
791 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
792 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
794 multiclass Atomic2Ops32<PatFrag Op> {
795 def #NAME# : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
796 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
797 Requires<[IsN64, HasStdEnc]> {
798 let DecoderNamespace = "Mips64";
802 // Atomic Compare & Swap.
803 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
804 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
805 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
807 multiclass AtomicCmpSwap32<PatFrag Op> {
808 def #NAME# : AtomicCmpSwap<Op, CPURegs, CPURegs>,
809 Requires<[NotN64, HasStdEnc]>;
810 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
811 Requires<[IsN64, HasStdEnc]> {
812 let DecoderNamespace = "Mips64";
816 class LLBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
817 FMem<Opc, (outs RC:$rt), (ins Mem:$addr),
818 !strconcat(opstring, "\t$rt, $addr"), [], IILoad> {
822 class SCBase<bits<6> Opc, string opstring, RegisterClass RC, Operand Mem> :
823 FMem<Opc, (outs RC:$dst), (ins RC:$rt, Mem:$addr),
824 !strconcat(opstring, "\t$rt, $addr"), [], IIStore> {
826 let Constraints = "$rt = $dst";
829 //===----------------------------------------------------------------------===//
830 // Pseudo instructions
831 //===----------------------------------------------------------------------===//
834 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
835 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
837 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
838 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
839 [(callseq_start timm:$amt)]>;
840 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
841 [(callseq_end timm:$amt1, timm:$amt2)]>;
844 let usesCustomInserter = 1 in {
845 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
846 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
847 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
848 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
849 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
850 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
851 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
852 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
853 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
854 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
855 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
856 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
857 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
858 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
859 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
860 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
861 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
862 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
864 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
865 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
866 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
868 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
869 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
870 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
873 //===----------------------------------------------------------------------===//
874 // Instruction definition
875 //===----------------------------------------------------------------------===//
877 class LoadImm32< string instr_asm, Operand Od, RegisterClass RC> :
878 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
879 !strconcat(instr_asm, "\t$rt, $imm32")> ;
880 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegs>;
882 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterClass RC> :
883 MipsAsmPseudoInst<(outs RC:$rt), (ins MemOpnd:$addr),
884 !strconcat(instr_asm, "\t$rt, $addr")> ;
885 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegs>;
887 class LoadAddressImm<string instr_asm, Operand Od, RegisterClass RC> :
888 MipsAsmPseudoInst<(outs RC:$rt), (ins Od:$imm32),
889 !strconcat(instr_asm, "\t$rt, $imm32")> ;
890 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegs>;
892 //===----------------------------------------------------------------------===//
893 // MipsI Instructions
894 //===----------------------------------------------------------------------===//
896 /// Arithmetic Instructions (ALU Immediate)
897 def ADDiu : ArithLogicI<"addiu", simm16, CPURegs, immSExt16, add>,
898 ADDI_FM<0x9>, IsAsCheapAsAMove;
899 def ADDi : ArithLogicI<"addi", simm16, CPURegs>, ADDI_FM<0x8>;
900 def SLTi : SetCC_I<0x0a, "slti", setlt, simm16, immSExt16, CPURegs>;
901 def SLTiu : SetCC_I<0x0b, "sltiu", setult, simm16, immSExt16, CPURegs>;
902 def ANDi : ArithLogicI<"andi", uimm16, CPURegs, immZExt16, and>, ADDI_FM<0xc>;
903 def ORi : ArithLogicI<"ori", uimm16, CPURegs, immZExt16, or>, ADDI_FM<0xd>;
904 def XORi : ArithLogicI<"xori", uimm16, CPURegs, immZExt16, xor>, ADDI_FM<0xe>;
905 def LUi : LoadUpper<0x0f, "lui", CPURegs, uimm16>;
907 /// Arithmetic Instructions (3-Operand, R-Type)
908 def ADDu : ArithLogicR<"addu", CPURegs, 1, IIAlu, add>, ADD_FM<0, 0x21>;
909 def SUBu : ArithLogicR<"subu", CPURegs, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
910 def ADD : ArithLogicR<"add", CPURegs>, ADD_FM<0, 0x20>;
911 def SUB : ArithLogicR<"sub", CPURegs>, ADD_FM<0, 0x22>;
912 def SLT : SetCC_R<0x00, 0x2a, "slt", setlt, CPURegs>;
913 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
914 def AND : ArithLogicR<"and", CPURegs, 1, IIAlu, and>, ADD_FM<0, 0x24>;
915 def OR : ArithLogicR<"or", CPURegs, 1, IIAlu, or>, ADD_FM<0, 0x25>;
916 def XOR : ArithLogicR<"xor", CPURegs, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
917 def NOR : LogicNOR<0x00, 0x27, "nor", CPURegs>;
919 /// Shift Instructions
920 def SLL : shift_rotate_imm32<"sll", shl>, SRA_FM<0, 0>;
921 def SRL : shift_rotate_imm32<"srl", srl>, SRA_FM<2, 0>;
922 def SRA : shift_rotate_imm32<"sra", sra>, SRA_FM<3, 0>;
923 def SLLV : shift_rotate_reg<"sllv", shl, CPURegs>, SRLV_FM<4, 0>;
924 def SRLV : shift_rotate_reg<"srlv", srl, CPURegs>, SRLV_FM<6, 0>;
925 def SRAV : shift_rotate_reg<"srav", sra, CPURegs>, SRLV_FM<7, 0>;
927 // Rotate Instructions
928 let Predicates = [HasMips32r2, HasStdEnc] in {
929 def ROTR : shift_rotate_imm32<"rotr", rotr>, SRA_FM<2, 1>;
930 def ROTRV : shift_rotate_reg<"rotrv", rotr, CPURegs>, SRLV_FM<6, 1>;
933 /// Load and Store Instructions
935 defm LB : LoadM32<0x20, "lb", sextloadi8>;
936 defm LBu : LoadM32<0x24, "lbu", zextloadi8>;
937 defm LH : LoadM32<0x21, "lh", sextloadi16>;
938 defm LHu : LoadM32<0x25, "lhu", zextloadi16>;
939 defm LW : LoadM32<0x23, "lw", load>;
940 defm SB : StoreM32<0x28, "sb", truncstorei8>;
941 defm SH : StoreM32<0x29, "sh", truncstorei16>;
942 defm SW : StoreM32<0x2b, "sw", store>;
944 /// load/store left/right
945 defm LWL : LoadLeftRightM32<0x22, "lwl", MipsLWL>;
946 defm LWR : LoadLeftRightM32<0x26, "lwr", MipsLWR>;
947 defm SWL : StoreLeftRightM32<0x2a, "swl", MipsSWL>;
948 defm SWR : StoreLeftRightM32<0x2e, "swr", MipsSWR>;
950 let hasSideEffects = 1 in
951 def SYNC : InstSE<(outs), (ins i32imm:$stype), "sync $stype",
952 [(MipsSync imm:$stype)], NoItinerary, FrmOther>
957 let Inst{10-6} = stype;
961 /// Load-linked, Store-conditional
962 def LL : LLBase<0x30, "ll", CPURegs, mem>,
963 Requires<[NotN64, HasStdEnc]>;
964 def LL_P8 : LLBase<0x30, "ll", CPURegs, mem64>,
965 Requires<[IsN64, HasStdEnc]> {
966 let DecoderNamespace = "Mips64";
969 def SC : SCBase<0x38, "sc", CPURegs, mem>,
970 Requires<[NotN64, HasStdEnc]>;
971 def SC_P8 : SCBase<0x38, "sc", CPURegs, mem64>,
972 Requires<[IsN64, HasStdEnc]> {
973 let DecoderNamespace = "Mips64";
976 /// Jump and Branch Instructions
977 def J : JumpFJ<0x02, jmptarget, "j", br, bb>,
978 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
979 def JR : IndirectBranch<CPURegs>;
980 def B : UncondBranch<"b">, B_FM;
981 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
982 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
983 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
984 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
985 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
986 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
988 let rt = 0, rs = 0, isBranch = 1, isTerminator = 1, isBarrier = 1,
989 hasDelaySlot = 1, Defs = [RA] in
990 def BAL_BR: FI<0x1, (outs), (ins brtarget:$imm16), "bal\t$imm16", [], IIBranch>;
992 def JAL : JumpLink<0x03, "jal">;
993 def JALR : JumpLinkReg<0x00, 0x09, "jalr", CPURegs>;
994 def BGEZAL : BranchLink<"bgezal", 0x11, CPURegs>;
995 def BLTZAL : BranchLink<"bltzal", 0x10, CPURegs>;
996 def TAILCALL : JumpFJ<0x02, calltarget, "j", MipsTailCall, imm>, IsTailCall;
997 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, IsTailCall;
999 def RET : RetBase<CPURegs>;
1001 /// Multiply and Divide Instructions.
1002 def MULT : Mult32<0x18, "mult", IIImul>;
1003 def MULTu : Mult32<0x19, "multu", IIImul>;
1004 def SDIV : Div32<MipsDivRem, 0x1a, "div", IIIdiv>;
1005 def UDIV : Div32<MipsDivRemU, 0x1b, "divu", IIIdiv>;
1007 def MTHI : MoveToLOHI<0x11, "mthi", CPURegs, [HI]>;
1008 def MTLO : MoveToLOHI<0x13, "mtlo", CPURegs, [LO]>;
1009 def MFHI : MoveFromLOHI<0x10, "mfhi", CPURegs, [HI]>;
1010 def MFLO : MoveFromLOHI<0x12, "mflo", CPURegs, [LO]>;
1012 /// Sign Ext In Register Instructions.
1013 def SEB : SignExtInReg<0x10, "seb", i8, CPURegs>;
1014 def SEH : SignExtInReg<0x18, "seh", i16, CPURegs>;
1017 def CLZ : CountLeading0<0x20, "clz", CPURegs>;
1018 def CLO : CountLeading1<0x21, "clo", CPURegs>;
1020 /// Word Swap Bytes Within Halfwords
1021 def WSBH : SubwordSwap<0x20, 0x2, "wsbh", CPURegs>;
1025 def NOP : FJ<0, (outs), (ins), "nop", [], IIAlu>;
1027 // FrameIndexes are legalized when they are operands from load/store
1028 // instructions. The same not happens for stack address copies, so an
1029 // add op with mem ComplexPattern is used and the stack address copy
1030 // can be matched. It's similar to Sparc LEA_ADDRi
1031 def LEA_ADDiu : EffectiveAddress<0x09,"addiu\t$rt, $addr", CPURegs, mem_ea>;
1034 def MADD : MArithR<0, "madd", MipsMAdd, 1>;
1035 def MADDU : MArithR<1, "maddu", MipsMAddu, 1>;
1036 def MSUB : MArithR<4, "msub", MipsMSub>;
1037 def MSUBU : MArithR<5, "msubu", MipsMSubu>;
1039 // MUL is a assembly macro in the current used ISAs. In recent ISA's
1040 // it is a real instruction.
1041 def MUL : ArithLogicR<"mul", CPURegs, 1, IIImul, mul>, ADD_FM<0x1c, 0x02>;
1043 def RDHWR : ReadHardware<CPURegs, HWRegs>;
1045 def EXT : ExtBase<0, "ext", CPURegs>;
1046 def INS : InsBase<4, "ins", CPURegs>;
1048 //===----------------------------------------------------------------------===//
1049 // Instruction aliases
1050 //===----------------------------------------------------------------------===//
1051 def : InstAlias<"move $dst,$src", (ADD CPURegs:$dst,CPURegs:$src,ZERO)>;
1052 def : InstAlias<"bal $offset", (BGEZAL RA,brtarget:$offset)>;
1053 def : InstAlias<"addu $rs,$rt,$imm",
1054 (ADDiu CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1055 def : InstAlias<"add $rs,$rt,$imm",
1056 (ADDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1057 def : InstAlias<"and $rs,$rt,$imm",
1058 (ANDi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1059 def : InstAlias<"j $rs", (JR CPURegs:$rs)>;
1060 def : InstAlias<"not $rt,$rs", (NOR CPURegs:$rt,CPURegs:$rs,ZERO)>;
1061 def : InstAlias<"neg $rt,$rs", (SUB CPURegs:$rt,ZERO,CPURegs:$rs)>;
1062 def : InstAlias<"negu $rt,$rs", (SUBu CPURegs:$rt,ZERO,CPURegs:$rs)>;
1063 def : InstAlias<"slt $rs,$rt,$imm",
1064 (SLTi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1065 def : InstAlias<"xor $rs,$rt,$imm",
1066 (XORi CPURegs:$rs,CPURegs:$rt,simm16:$imm)>;
1068 //===----------------------------------------------------------------------===//
1069 // Arbitrary patterns that map to one or more instructions
1070 //===----------------------------------------------------------------------===//
1073 def : MipsPat<(i32 immSExt16:$in),
1074 (ADDiu ZERO, imm:$in)>;
1075 def : MipsPat<(i32 immZExt16:$in),
1076 (ORi ZERO, imm:$in)>;
1077 def : MipsPat<(i32 immLow16Zero:$in),
1078 (LUi (HI16 imm:$in))>;
1080 // Arbitrary immediates
1081 def : MipsPat<(i32 imm:$imm),
1082 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1084 // Carry MipsPatterns
1085 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1086 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1087 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1088 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1089 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1090 (ADDiu CPURegs:$src, imm:$imm)>;
1093 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1094 (JAL tglobaladdr:$dst)>;
1095 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1096 (JAL texternalsym:$dst)>;
1097 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1098 // (JALR CPURegs:$dst)>;
1101 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1102 (TAILCALL tglobaladdr:$dst)>;
1103 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1104 (TAILCALL texternalsym:$dst)>;
1106 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1107 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1108 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1109 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1110 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1111 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1113 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1114 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1115 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1116 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1117 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1118 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1120 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1121 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1122 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1123 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1124 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1125 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1126 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1127 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1128 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1129 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1132 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1133 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1134 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1135 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1138 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1139 MipsPat<(MipsWrapper RC:$gp, node:$in),
1140 (ADDiuOp RC:$gp, node:$in)>;
1142 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1143 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1144 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1145 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1146 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1147 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1149 // Mips does not have "not", so we expand our way
1150 def : MipsPat<(not CPURegs:$in),
1151 (NOR CPURegs:$in, ZERO)>;
1154 let Predicates = [NotN64, HasStdEnc] in {
1155 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1156 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1157 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1159 let Predicates = [IsN64, HasStdEnc] in {
1160 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1161 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1162 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1166 let Predicates = [NotN64, HasStdEnc] in {
1167 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1169 let Predicates = [IsN64, HasStdEnc] in {
1170 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1174 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1175 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1176 Instruction SLTiuOp, Register ZEROReg> {
1177 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1178 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1179 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1180 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1182 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1183 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1184 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1185 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1186 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1187 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1188 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1189 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1191 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1192 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1193 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1194 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1196 def : MipsPat<(brcond RC:$cond, bb:$dst),
1197 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1200 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1203 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1204 Instruction SLTuOp, Register ZEROReg> {
1205 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1206 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1207 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1208 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1211 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1212 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1213 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1214 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1215 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1218 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1219 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1220 (SLTOp RC:$rhs, RC:$lhs)>;
1221 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1222 (SLTuOp RC:$rhs, RC:$lhs)>;
1225 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1226 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1227 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1228 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1229 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1232 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1233 Instruction SLTiuOp> {
1234 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1235 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1236 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1237 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1240 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1241 defm : SetlePats<CPURegs, SLT, SLTu>;
1242 defm : SetgtPats<CPURegs, SLT, SLTu>;
1243 defm : SetgePats<CPURegs, SLT, SLTu>;
1244 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1247 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1249 //===----------------------------------------------------------------------===//
1250 // Floating Point Support
1251 //===----------------------------------------------------------------------===//
1253 include "MipsInstrFPU.td"
1254 include "Mips64InstrInfo.td"
1255 include "MipsCondMov.td"
1260 include "Mips16InstrFormats.td"
1261 include "Mips16InstrInfo.td"
1264 include "MipsDSPInstrFormats.td"
1265 include "MipsDSPInstrInfo.td"