1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def NotMips4_32 : Predicate<"!Subtarget->hasMips4_32()">,
160 AssemblerPredicate<"FeatureMips4_32">;
161 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
162 AssemblerPredicate<"FeatureMips4_32r2">;
163 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
164 AssemblerPredicate<"FeatureMips5_32r2">;
165 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
166 AssemblerPredicate<"FeatureMips32">;
167 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
168 AssemblerPredicate<"FeatureMips32r2">;
169 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"FeatureMips32r6">;
171 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
172 AssemblerPredicate<"!FeatureMips32r6">;
173 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
174 AssemblerPredicate<"FeatureGP64Bit">;
175 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
176 AssemblerPredicate<"!FeatureGP64Bit">;
177 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
178 AssemblerPredicate<"FeatureMips64">;
179 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
180 AssemblerPredicate<"FeatureMips64r2">;
181 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"FeatureMips64r6">;
183 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
184 AssemblerPredicate<"!FeatureMips64r6">;
185 def HasMicroMips32r6 : Predicate<"Subtarget->inMicroMips32r6Mode()">,
186 AssemblerPredicate<"FeatureMicroMips,FeatureMips32r6">;
187 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
188 AssemblerPredicate<"FeatureMips16">;
189 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
190 AssemblerPredicate<"FeatureCnMips">;
191 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">;
192 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_4_32 {
224 list<Predicate> InsnPredicates = [NotMips4_32];
226 class ISA_MIPS1_NOT_32R6_64R6 {
227 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
229 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
230 class ISA_MIPS2_NOT_32R6_64R6 {
231 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
233 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
234 class ISA_MIPS3_NOT_32R6_64R6 {
235 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
237 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
238 class ISA_MIPS32_NOT_32R6_64R6 {
239 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
241 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
242 class ISA_MIPS32R2_NOT_32R6_64R6 {
243 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
245 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
246 class ISA_MIPS64_NOT_64R6 {
247 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
249 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
250 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
251 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
252 class ISA_MICROMIPS32R6 {
253 list<Predicate> InsnPredicates = [HasMicroMips32r6];
256 // The portions of MIPS-III that were also added to MIPS32
257 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
259 // The portions of MIPS-III that were also added to MIPS32 but were removed in
260 // MIPS32r6 and MIPS64r6.
261 class INSN_MIPS3_32_NOT_32R6_64R6 {
262 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
265 // The portions of MIPS-III that were also added to MIPS32
266 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
268 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
280 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
281 // MIPS32r6 and MIPS64r6.
282 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
283 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
286 //===----------------------------------------------------------------------===//
288 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
289 let EncodingPredicates = [HasStdEnc];
292 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
293 InstAlias<Asm, Result, Emit>, PredicateControl;
296 bit isCommutable = 1;
313 bit isTerminator = 1;
316 bit hasExtraSrcRegAllocReq = 1;
317 bit isCodeGenOnly = 1;
320 class IsAsCheapAsAMove {
321 bit isAsCheapAsAMove = 1;
324 class NeverHasSideEffects {
325 bit hasSideEffects = 0;
328 //===----------------------------------------------------------------------===//
329 // Instruction format superclass
330 //===----------------------------------------------------------------------===//
332 include "MipsInstrFormats.td"
334 //===----------------------------------------------------------------------===//
335 // Mips Operand, Complex Patterns and Transformations Definitions.
336 //===----------------------------------------------------------------------===//
338 def MipsJumpTargetAsmOperand : AsmOperandClass {
339 let Name = "JumpTarget";
340 let ParserMethod = "parseJumpTarget";
341 let PredicateMethod = "isImm";
342 let RenderMethod = "addImmOperands";
345 // Instruction operand types
346 def jmptarget : Operand<OtherVT> {
347 let EncoderMethod = "getJumpTargetOpValue";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def brtarget : Operand<OtherVT> {
351 let EncoderMethod = "getBranchTargetOpValue";
352 let OperandType = "OPERAND_PCREL";
353 let DecoderMethod = "DecodeBranchTarget";
354 let ParserMatchClass = MipsJumpTargetAsmOperand;
356 def calltarget : Operand<iPTR> {
357 let EncoderMethod = "getJumpTargetOpValue";
358 let ParserMatchClass = MipsJumpTargetAsmOperand;
361 def simm9 : Operand<i32>;
362 def simm10 : Operand<i32>;
363 def simm11 : Operand<i32>;
365 def simm16 : Operand<i32> {
366 let DecoderMethod= "DecodeSimm16";
369 def simm19_lsl2 : Operand<i32> {
370 let EncoderMethod = "getSimm19Lsl2Encoding";
371 let DecoderMethod = "DecodeSimm19Lsl2";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm18_lsl3 : Operand<i32> {
376 let EncoderMethod = "getSimm18Lsl3Encoding";
377 let DecoderMethod = "DecodeSimm18Lsl3";
378 let ParserMatchClass = MipsJumpTargetAsmOperand;
381 def simm20 : Operand<i32> {
384 def uimm20 : Operand<i32> {
387 def uimm10 : Operand<i32> {
390 def simm16_64 : Operand<i64> {
391 let DecoderMethod = "DecodeSimm16";
395 def uimmz : Operand<i32> {
396 let PrintMethod = "printUnsignedImm";
400 def uimm2 : Operand<i32> {
401 let PrintMethod = "printUnsignedImm";
404 def uimm3 : Operand<i32> {
405 let PrintMethod = "printUnsignedImm";
408 def uimm5 : Operand<i32> {
409 let PrintMethod = "printUnsignedImm";
412 def uimm6 : Operand<i32> {
413 let PrintMethod = "printUnsignedImm";
416 def uimm16 : Operand<i32> {
417 let PrintMethod = "printUnsignedImm";
420 def pcrel16 : Operand<i32> {
423 def MipsMemAsmOperand : AsmOperandClass {
425 let ParserMethod = "parseMemOperand";
428 def MipsMemSimm11AsmOperand : AsmOperandClass {
429 let Name = "MemOffsetSimm11";
430 let SuperClasses = [MipsMemAsmOperand];
431 let RenderMethod = "addMemOperands";
432 let ParserMethod = "parseMemOperand";
433 let PredicateMethod = "isMemWithSimmOffset<11>";
436 def MipsMemSimm16AsmOperand : AsmOperandClass {
437 let Name = "MemOffsetSimm16";
438 let SuperClasses = [MipsMemAsmOperand];
439 let RenderMethod = "addMemOperands";
440 let ParserMethod = "parseMemOperand";
441 let PredicateMethod = "isMemWithSimmOffset<16>";
444 def MipsInvertedImmoperand : AsmOperandClass {
446 let RenderMethod = "addImmOperands";
447 let ParserMethod = "parseInvNum";
450 def InvertedImOperand : Operand<i32> {
451 let ParserMatchClass = MipsInvertedImmoperand;
454 def InvertedImOperand64 : Operand<i64> {
455 let ParserMatchClass = MipsInvertedImmoperand;
458 class mem_generic : Operand<iPTR> {
459 let PrintMethod = "printMemOperand";
460 let MIOperandInfo = (ops ptr_rc, simm16);
461 let EncoderMethod = "getMemEncoding";
462 let ParserMatchClass = MipsMemAsmOperand;
463 let OperandType = "OPERAND_MEMORY";
467 def mem : mem_generic;
469 // MSA specific address operand
470 def mem_msa : mem_generic {
471 let MIOperandInfo = (ops ptr_rc, simm10);
472 let EncoderMethod = "getMSAMemEncoding";
475 def mem_simm9 : mem_generic {
476 let MIOperandInfo = (ops ptr_rc, simm9);
477 let EncoderMethod = "getMemEncoding";
480 def mem_simm11 : mem_generic {
481 let MIOperandInfo = (ops ptr_rc, simm11);
482 let EncoderMethod = "getMemEncoding";
483 let ParserMatchClass = MipsMemSimm11AsmOperand;
486 def mem_simm16 : mem_generic {
487 let MIOperandInfo = (ops ptr_rc, simm16);
488 let EncoderMethod = "getMemEncoding";
489 let ParserMatchClass = MipsMemSimm16AsmOperand;
492 def mem_ea : Operand<iPTR> {
493 let PrintMethod = "printMemOperandEA";
494 let MIOperandInfo = (ops ptr_rc, simm16);
495 let EncoderMethod = "getMemEncoding";
496 let OperandType = "OPERAND_MEMORY";
499 def PtrRC : Operand<iPTR> {
500 let MIOperandInfo = (ops ptr_rc);
501 let DecoderMethod = "DecodePtrRegisterClass";
502 let ParserMatchClass = GPR32AsmOperand;
505 // size operand of ext instruction
506 def size_ext : Operand<i32> {
507 let EncoderMethod = "getSizeExtEncoding";
508 let DecoderMethod = "DecodeExtSize";
511 // size operand of ins instruction
512 def size_ins : Operand<i32> {
513 let EncoderMethod = "getSizeInsEncoding";
514 let DecoderMethod = "DecodeInsSize";
517 // Transformation Function - get the lower 16 bits.
518 def LO16 : SDNodeXForm<imm, [{
519 return getImm(N, N->getZExtValue() & 0xFFFF);
522 // Transformation Function - get the higher 16 bits.
523 def HI16 : SDNodeXForm<imm, [{
524 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
528 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
530 // Node immediate is zero (e.g. insve.d)
531 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
533 // Node immediate fits as 16-bit sign extended on target immediate.
535 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
537 // Node immediate fits as 16-bit sign extended on target immediate.
539 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
541 // Node immediate fits as 15-bit sign extended on target immediate.
543 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
545 // Node immediate fits as 16-bit zero extended on target immediate.
546 // The LO16 param means that only the lower 16 bits of the node
547 // immediate are caught.
549 def immZExt16 : PatLeaf<(imm), [{
550 if (N->getValueType(0) == MVT::i32)
551 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
553 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
556 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
557 def immLow16Zero : PatLeaf<(imm), [{
558 int64_t Val = N->getSExtValue();
559 return isInt<32>(Val) && !(Val & 0xffff);
562 // shamt field must fit in 5 bits.
563 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
565 // True if (N + 1) fits in 16-bit field.
566 def immSExt16Plus1 : PatLeaf<(imm), [{
567 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
570 // Mips Address Mode! SDNode frameindex could possibily be a match
571 // since load and store instructions from stack used it.
573 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
576 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
579 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
582 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
584 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
586 //===----------------------------------------------------------------------===//
587 // Instructions specific format
588 //===----------------------------------------------------------------------===//
590 // Arithmetic and logical instructions with 3 register operands.
591 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
592 InstrItinClass Itin = NoItinerary,
593 SDPatternOperator OpNode = null_frag>:
594 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
595 !strconcat(opstr, "\t$rd, $rs, $rt"),
596 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
597 let isCommutable = isComm;
598 let isReMaterializable = 1;
599 let TwoOperandAliasConstraint = "$rd = $rs";
602 // Arithmetic and logical instructions with 2 register operands.
603 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
604 InstrItinClass Itin = NoItinerary,
605 SDPatternOperator imm_type = null_frag,
606 SDPatternOperator OpNode = null_frag> :
607 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
608 !strconcat(opstr, "\t$rt, $rs, $imm16"),
609 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
611 let isReMaterializable = 1;
612 let TwoOperandAliasConstraint = "$rs = $rt";
615 // Arithmetic Multiply ADD/SUB
616 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
617 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
618 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
619 let Defs = [HI0, LO0];
620 let Uses = [HI0, LO0];
621 let isCommutable = isComm;
625 class LogicNOR<string opstr, RegisterOperand RO>:
626 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
627 !strconcat(opstr, "\t$rd, $rs, $rt"),
628 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
629 let isCommutable = 1;
633 class shift_rotate_imm<string opstr, Operand ImmOpnd,
634 RegisterOperand RO, InstrItinClass itin,
635 SDPatternOperator OpNode = null_frag,
636 SDPatternOperator PF = null_frag> :
637 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
638 !strconcat(opstr, "\t$rd, $rt, $shamt"),
639 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
640 let TwoOperandAliasConstraint = "$rt = $rd";
643 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
644 SDPatternOperator OpNode = null_frag>:
645 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
646 !strconcat(opstr, "\t$rd, $rt, $rs"),
647 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
650 // Load Upper Imediate
651 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
652 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
653 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
654 let hasSideEffects = 0;
655 let isReMaterializable = 1;
659 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
660 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
661 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
662 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
663 let DecoderMethod = "DecodeMem";
664 let canFoldAsLoad = 1;
668 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
669 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
671 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
672 let DecoderMethod = "DecodeMem";
676 // Load/Store Left/Right
677 let canFoldAsLoad = 1 in
678 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
679 InstrItinClass Itin> :
680 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
681 !strconcat(opstr, "\t$rt, $addr"),
682 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
683 let DecoderMethod = "DecodeMem";
684 string Constraints = "$src = $rt";
687 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
688 InstrItinClass Itin> :
689 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
690 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
691 let DecoderMethod = "DecodeMem";
695 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
696 SDPatternOperator OpNode= null_frag> :
697 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
698 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
699 let DecoderMethod = "DecodeFMem2";
703 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
704 SDPatternOperator OpNode= null_frag> :
705 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
706 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
707 let DecoderMethod = "DecodeFMem2";
712 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
713 SDPatternOperator OpNode= null_frag> :
714 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
715 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
716 let DecoderMethod = "DecodeFMem3";
720 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
721 SDPatternOperator OpNode= null_frag> :
722 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
723 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
724 let DecoderMethod = "DecodeFMem3";
728 // Conditional Branch
729 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
730 RegisterOperand RO, bit DelaySlot = 1> :
731 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
732 !strconcat(opstr, "\t$rs, $rt, $offset"),
733 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
736 let isTerminator = 1;
737 let hasDelaySlot = DelaySlot;
741 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
742 RegisterOperand RO, bit DelaySlot = 1> :
743 InstSE<(outs), (ins RO:$rs, opnd:$offset),
744 !strconcat(opstr, "\t$rs, $offset"),
745 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
748 let isTerminator = 1;
749 let hasDelaySlot = DelaySlot;
754 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
755 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
756 !strconcat(opstr, "\t$rd, $rs, $rt"),
757 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
758 II_SLT_SLTU, FrmR, opstr>;
760 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
762 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
763 !strconcat(opstr, "\t$rt, $rs, $imm16"),
764 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
765 II_SLTI_SLTIU, FrmI, opstr>;
768 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
769 SDPatternOperator targetoperator, string bopstr> :
770 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
771 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
774 let hasDelaySlot = 1;
775 let DecoderMethod = "DecodeJumpTarget";
779 // Unconditional branch
780 class UncondBranch<Instruction BEQInst> :
781 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
782 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
784 let isTerminator = 1;
786 let hasDelaySlot = 1;
787 let AdditionalPredicates = [RelocPIC];
791 // Base class for indirect branch and return instruction classes.
792 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
793 class JumpFR<string opstr, RegisterOperand RO,
794 SDPatternOperator operator = null_frag>:
795 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
799 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
801 let isIndirectBranch = 1;
804 // Jump and Link (Call)
805 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
806 class JumpLink<string opstr, DAGOperand opnd> :
807 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
808 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
809 let DecoderMethod = "DecodeJumpTarget";
812 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
813 Register RetReg, RegisterOperand ResRO = RO>:
814 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
815 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
817 class JumpLinkReg<string opstr, RegisterOperand RO>:
818 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
821 class BGEZAL_FT<string opstr, DAGOperand opnd,
822 RegisterOperand RO, bit DelaySlot = 1> :
823 InstSE<(outs), (ins RO:$rs, opnd:$offset),
824 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
825 let hasDelaySlot = DelaySlot;
830 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
831 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
832 class TailCall<Instruction JumpInst> :
833 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
834 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
836 class TailCallReg<RegisterOperand RO, Instruction JRInst,
837 RegisterOperand ResRO = RO> :
838 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
839 PseudoInstExpansion<(JRInst ResRO:$rs)>;
842 class BAL_BR_Pseudo<Instruction RealInst> :
843 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
844 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
846 let isTerminator = 1;
848 let hasDelaySlot = 1;
853 class SYS_FT<string opstr> :
854 InstSE<(outs), (ins uimm20:$code_),
855 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
857 class BRK_FT<string opstr> :
858 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
859 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
863 class ER_FT<string opstr> :
864 InstSE<(outs), (ins),
865 opstr, [], NoItinerary, FrmOther, opstr>;
868 class DEI_FT<string opstr, RegisterOperand RO> :
869 InstSE<(outs RO:$rt), (ins),
870 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
873 class WAIT_FT<string opstr> :
874 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
877 let hasSideEffects = 1 in
878 class SYNC_FT<string opstr> :
879 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
880 NoItinerary, FrmOther, opstr>;
882 class SYNCI_FT<string opstr> :
883 InstSE<(outs), (ins mem_simm16:$addr), !strconcat(opstr, "\t$addr"), [],
884 NoItinerary, FrmOther, opstr> {
885 let hasSideEffects = 1;
886 let DecoderMethod = "DecodeSyncI";
889 let hasSideEffects = 1 in
890 class TEQ_FT<string opstr, RegisterOperand RO> :
891 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
892 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
895 class TEQI_FT<string opstr, RegisterOperand RO> :
896 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
897 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
899 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
900 list<Register> DefRegs> :
901 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
903 let isCommutable = 1;
905 let hasSideEffects = 0;
908 // Pseudo multiply/divide instruction with explicit accumulator register
910 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
911 SDPatternOperator OpNode, InstrItinClass Itin,
912 bit IsComm = 1, bit HasSideEffects = 0,
913 bit UsesCustomInserter = 0> :
914 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
915 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
916 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
917 let isCommutable = IsComm;
918 let hasSideEffects = HasSideEffects;
919 let usesCustomInserter = UsesCustomInserter;
922 // Pseudo multiply add/sub instruction with explicit accumulator register
924 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
926 : PseudoSE<(outs ACC64:$ac),
927 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
929 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
931 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
932 string Constraints = "$acin = $ac";
935 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
936 list<Register> DefRegs> :
937 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
938 [], itin, FrmR, opstr> {
943 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
944 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
945 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
947 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
948 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
951 let hasSideEffects = 0;
954 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
955 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
956 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
959 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
960 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
963 let hasSideEffects = 0;
966 class EffectiveAddress<string opstr, RegisterOperand RO> :
967 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
968 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
969 !strconcat(opstr, "_lea")> {
970 let isCodeGenOnly = 1;
971 let DecoderMethod = "DecodeMem";
974 // Count Leading Ones/Zeros in Word
975 class CountLeading0<string opstr, RegisterOperand RO>:
976 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
977 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
979 class CountLeading1<string opstr, RegisterOperand RO>:
980 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
981 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
983 // Sign Extend in Register.
984 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
985 InstrItinClass itin> :
986 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
987 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
990 class SubwordSwap<string opstr, RegisterOperand RO>:
991 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
992 NoItinerary, FrmR, opstr> {
993 let hasSideEffects = 0;
997 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
998 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
999 II_RDHWR, FrmR, "rdhwr">;
1002 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1003 SDPatternOperator Op = null_frag>:
1004 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
1005 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1006 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], II_EXT,
1007 FrmR, opstr>, ISA_MIPS32R2;
1009 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
1010 SDPatternOperator Op = null_frag>:
1011 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
1012 !strconcat(opstr, " $rt, $rs, $pos, $size"),
1013 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
1014 II_INS, FrmR, opstr>, ISA_MIPS32R2 {
1015 let Constraints = "$src = $rt";
1018 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
1019 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
1020 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
1021 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
1023 // Atomic Compare & Swap.
1024 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
1025 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1026 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1028 class LLBase<string opstr, RegisterOperand RO> :
1029 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1030 [], NoItinerary, FrmI> {
1031 let DecoderMethod = "DecodeMem";
1035 class SCBase<string opstr, RegisterOperand RO> :
1036 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1037 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1038 let DecoderMethod = "DecodeMem";
1040 let Constraints = "$rt = $dst";
1043 class MFC3OP<string asmstr, RegisterOperand RO> :
1044 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1045 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1047 class TrapBase<Instruction RealInst>
1048 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1049 PseudoInstExpansion<(RealInst 0, 0)> {
1051 let isTerminator = 1;
1052 let isCodeGenOnly = 1;
1055 //===----------------------------------------------------------------------===//
1056 // Pseudo instructions
1057 //===----------------------------------------------------------------------===//
1060 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1061 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1063 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1064 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1065 [(callseq_start timm:$amt)]>;
1066 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1067 [(callseq_end timm:$amt1, timm:$amt2)]>;
1070 let usesCustomInserter = 1 in {
1071 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1072 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1073 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1074 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1075 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1076 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1077 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1078 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1079 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1080 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1081 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1082 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1083 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1084 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1085 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1086 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1087 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1088 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1090 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1091 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1092 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1094 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1095 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1096 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1099 /// Pseudo instructions for loading and storing accumulator registers.
1100 let isPseudo = 1, isCodeGenOnly = 1 in {
1101 def LOAD_ACC64 : Load<"", ACC64>;
1102 def STORE_ACC64 : Store<"", ACC64>;
1105 // We need these two pseudo instructions to avoid offset calculation for long
1106 // branches. See the comment in file MipsLongBranch.cpp for detailed
1109 // Expands to: lui $dst, %hi($tgt - $baltgt)
1110 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1111 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1113 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1114 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1115 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1117 //===----------------------------------------------------------------------===//
1118 // Instruction definition
1119 //===----------------------------------------------------------------------===//
1120 //===----------------------------------------------------------------------===//
1121 // MipsI Instructions
1122 //===----------------------------------------------------------------------===//
1124 /// Arithmetic Instructions (ALU Immediate)
1125 let AdditionalPredicates = [NotInMicroMips] in {
1126 def ADDiu : MMRel, StdMMR6Rel, ArithLogicI<"addiu", simm16, GPR32Opnd,
1127 II_ADDIU, immSExt16, add>,
1128 ADDI_FM<0x9>, IsAsCheapAsAMove;
1130 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1131 ISA_MIPS1_NOT_32R6_64R6;
1132 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1134 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1136 let AdditionalPredicates = [NotInMicroMips] in {
1137 def ANDi : MMRel, StdMMR6Rel,
1138 ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16, and>,
1141 def ORi : MMRel, StdMMR6Rel,
1142 ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16, or>,
1144 def XORi : MMRel, StdMMR6Rel,
1145 ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16, xor>,
1147 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1148 let AdditionalPredicates = [NotInMicroMips] in {
1149 /// Arithmetic Instructions (3-Operand, R-Type)
1150 def ADDu : MMRel, StdMMR6Rel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1152 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1155 let Defs = [HI0, LO0] in
1156 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1157 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1158 def ADD : MMRel, StdMMR6Rel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1159 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1160 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1161 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1162 let AdditionalPredicates = [NotInMicroMips] in {
1163 def AND : MMRel, StdMMR6Rel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1165 def OR : MMRel, StdMMR6Rel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1167 def XOR : MMRel, StdMMR6Rel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1170 def NOR : MMRel, StdMMR6Rel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1172 /// Shift Instructions
1173 let AdditionalPredicates = [NotInMicroMips] in {
1174 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1175 immZExt5>, SRA_FM<0, 0>;
1176 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1177 immZExt5>, SRA_FM<2, 0>;
1179 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1180 immZExt5>, SRA_FM<3, 0>;
1181 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1183 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1185 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1188 // Rotate Instructions
1189 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1191 SRA_FM<2, 1>, ISA_MIPS32R2;
1192 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1193 SRLV_FM<6, 1>, ISA_MIPS32R2;
1195 /// Load and Store Instructions
1197 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1198 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1200 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1202 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1203 let AdditionalPredicates = [NotInMicroMips] in {
1204 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1207 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1208 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1209 let AdditionalPredicates = [NotInMicroMips] in {
1210 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1213 /// load/store left/right
1214 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1215 AdditionalPredicates = [NotInMicroMips] in {
1216 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1217 ISA_MIPS1_NOT_32R6_64R6;
1218 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1219 ISA_MIPS1_NOT_32R6_64R6;
1220 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1221 ISA_MIPS1_NOT_32R6_64R6;
1222 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1223 ISA_MIPS1_NOT_32R6_64R6;
1226 let AdditionalPredicates = [NotInMicroMips] in {
1227 // COP2 Memory Instructions
1228 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1229 ISA_MIPS1_NOT_32R6_64R6;
1230 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1231 ISA_MIPS1_NOT_32R6_64R6;
1232 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1233 ISA_MIPS2_NOT_32R6_64R6;
1234 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1235 ISA_MIPS2_NOT_32R6_64R6;
1237 // COP3 Memory Instructions
1238 let DecoderNamespace = "COP3_" in {
1239 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1240 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1241 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1243 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1248 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1249 def SYNCI : MMRel, SYNCI_FT<"synci">, SYNCI_FM, ISA_MIPS32R2;
1251 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1252 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1253 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1254 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1255 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1256 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1258 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1259 ISA_MIPS2_NOT_32R6_64R6;
1260 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1261 ISA_MIPS2_NOT_32R6_64R6;
1262 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1263 ISA_MIPS2_NOT_32R6_64R6;
1264 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1265 ISA_MIPS2_NOT_32R6_64R6;
1266 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1267 ISA_MIPS2_NOT_32R6_64R6;
1268 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1269 ISA_MIPS2_NOT_32R6_64R6;
1271 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1272 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1273 def TRAP : TrapBase<BREAK>;
1274 def SDBBP : MMRel, SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1276 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1277 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1279 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1280 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1282 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1283 AdditionalPredicates = [NotInMicroMips] in {
1284 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1286 /// Load-linked, Store-conditional
1287 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1288 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1291 /// Jump and Branch Instructions
1292 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1293 AdditionalRequires<[RelocStatic]>, IsBranch;
1294 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1295 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1296 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1297 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1298 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1299 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1300 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1301 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1303 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1304 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1305 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1307 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1308 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1309 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1311 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1312 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1313 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1315 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1316 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1317 def B : UncondBranch<BEQ>;
1319 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1320 let AdditionalPredicates = [NotInMicroMips] in {
1321 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1322 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1325 def JALX : MMRel, JumpLink<"jalx", calltarget>, FJ<0x1D>,
1326 ISA_MIPS32_NOT_32R6_64R6;
1327 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1328 ISA_MIPS1_NOT_32R6_64R6;
1329 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1330 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1331 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1332 ISA_MIPS1_NOT_32R6_64R6;
1333 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1334 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1335 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1336 def TAILCALL : TailCall<J>;
1337 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1339 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1340 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1341 class PseudoIndirectBranchBase<RegisterOperand RO> :
1342 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1345 let hasDelaySlot = 1;
1347 let isIndirectBranch = 1;
1350 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1352 // Return instructions are matched as a RetRA instruction, then ar expanded
1353 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1354 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1356 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1358 let isTerminator = 1;
1360 let hasDelaySlot = 1;
1362 let isCodeGenOnly = 1;
1364 let hasExtraSrcRegAllocReq = 1;
1367 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1369 // Exception handling related node and instructions.
1370 // The conversion sequence is:
1371 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1372 // MIPSeh_return -> (stack change + indirect branch)
1374 // MIPSeh_return takes the place of regular return instruction
1375 // but takes two arguments (V1, V0) which are used for storing
1376 // the offset and return address respectively.
1377 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1379 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1380 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1382 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1383 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1384 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1385 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1387 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1390 /// Multiply and Divide Instructions.
1391 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1392 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1393 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1394 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1395 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1396 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1397 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1398 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1400 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1401 ISA_MIPS1_NOT_32R6_64R6;
1402 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1403 ISA_MIPS1_NOT_32R6_64R6;
1404 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1405 AdditionalPredicates = [NotInMicroMips] in {
1406 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1407 ISA_MIPS1_NOT_32R6_64R6;
1408 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1409 ISA_MIPS1_NOT_32R6_64R6;
1412 /// Sign Ext In Register Instructions.
1413 def SEB : MMRel, StdMMR6Rel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1414 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1415 def SEH : MMRel, StdMMR6Rel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1416 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1419 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1420 ISA_MIPS32_NOT_32R6_64R6;
1421 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1422 ISA_MIPS32_NOT_32R6_64R6;
1424 /// Word Swap Bytes Within Halfwords
1425 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1428 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1430 // FrameIndexes are legalized when they are operands from load/store
1431 // instructions. The same not happens for stack address copies, so an
1432 // add op with mem ComplexPattern is used and the stack address copy
1433 // can be matched. It's similar to Sparc LEA_ADDRi
1434 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1437 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1438 ISA_MIPS32_NOT_32R6_64R6;
1439 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1440 ISA_MIPS32_NOT_32R6_64R6;
1441 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1442 ISA_MIPS32_NOT_32R6_64R6;
1443 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1444 ISA_MIPS32_NOT_32R6_64R6;
1446 let AdditionalPredicates = [NotDSP] in {
1447 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1448 ISA_MIPS1_NOT_32R6_64R6;
1449 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1450 ISA_MIPS1_NOT_32R6_64R6;
1451 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1452 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1453 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1454 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1455 ISA_MIPS32_NOT_32R6_64R6;
1456 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1457 ISA_MIPS32_NOT_32R6_64R6;
1458 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1459 ISA_MIPS32_NOT_32R6_64R6;
1460 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1461 ISA_MIPS32_NOT_32R6_64R6;
1464 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1465 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1466 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1467 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1469 def RDHWR : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1471 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1472 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1474 /// Move Control Registers From/To CPU Registers
1475 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1476 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1477 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1478 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1480 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1482 def SSNOP : MMRel, Barrier<"ssnop">, BARRIER_FM<1>;
1483 def EHB : MMRel, Barrier<"ehb">, BARRIER_FM<3>;
1484 def PAUSE : MMRel, Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1486 // JR_HB and JALR_HB are defined here using the new style naming
1487 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1488 // and because of that it doesn't follow the naming convention of the
1489 // rest of the file. To avoid a mixture of old vs new style, the new
1490 // style was chosen.
1491 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1492 dag OutOperandList = (outs);
1493 dag InOperandList = (ins GPROpnd:$rs);
1494 string AsmString = !strconcat(instr_asm, "\t$rs");
1495 list<dag> Pattern = [];
1498 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1499 dag OutOperandList = (outs GPROpnd:$rd);
1500 dag InOperandList = (ins GPROpnd:$rs);
1501 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1502 list<dag> Pattern = [];
1505 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1506 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1508 let isIndirectBranch=1;
1514 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1515 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1516 let isIndirectBranch=1;
1520 class JR_HB_ENC : JR_HB_FM<8>;
1521 class JALR_HB_ENC : JALR_HB_FM<9>;
1523 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1524 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1526 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1528 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1529 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1530 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1531 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1533 class CacheOp<string instr_asm, Operand MemOpnd> :
1534 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1535 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther,
1537 let DecoderMethod = "DecodeCacheOp";
1540 def CACHE : MMRel, CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1541 INSN_MIPS3_32_NOT_32R6_64R6;
1542 def PREF : MMRel, CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1543 INSN_MIPS3_32_NOT_32R6_64R6;
1545 //===----------------------------------------------------------------------===//
1546 // Instruction aliases
1547 //===----------------------------------------------------------------------===//
1548 def : MipsInstAlias<"move $dst, $src",
1549 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1551 let AdditionalPredicates = [NotInMicroMips];
1553 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1554 ISA_MIPS1_NOT_32R6_64R6;
1555 def : MipsInstAlias<"addu $rs, $rt, $imm",
1556 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1557 def : MipsInstAlias<"addu $rs, $imm",
1558 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1559 def : MipsInstAlias<"add $rs, $rt, $imm",
1560 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1561 ISA_MIPS1_NOT_32R6_64R6;
1562 def : MipsInstAlias<"add $rs, $imm",
1563 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1564 ISA_MIPS1_NOT_32R6_64R6;
1565 def : MipsInstAlias<"and $rs, $rt, $imm",
1566 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1567 def : MipsInstAlias<"and $rs, $imm",
1568 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1569 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1570 let Predicates = [NotInMicroMips] in {
1571 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1573 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1574 def : MipsInstAlias<"not $rt, $rs",
1575 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1576 def : MipsInstAlias<"neg $rt, $rs",
1577 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1578 def : MipsInstAlias<"negu $rt",
1579 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1580 def : MipsInstAlias<"negu $rt, $rs",
1581 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1582 def : MipsInstAlias<"slt $rs, $rt, $imm",
1583 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1584 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1585 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1586 def : MipsInstAlias<"xor $rs, $rt, $imm",
1587 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1588 def : MipsInstAlias<"xor $rs, $imm",
1589 (XORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1590 def : MipsInstAlias<"or $rs, $rt, $imm",
1591 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1592 def : MipsInstAlias<"or $rs, $imm",
1593 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1594 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1595 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1596 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1597 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1598 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1599 let AdditionalPredicates = [NotInMicroMips] in {
1600 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1602 def : MipsInstAlias<"bnez $rs,$offset",
1603 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1604 def : MipsInstAlias<"bnezl $rs,$offset",
1605 (BNEL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1606 def : MipsInstAlias<"beqz $rs,$offset",
1607 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1608 def : MipsInstAlias<"beqzl $rs,$offset",
1609 (BEQL GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1610 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1612 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1613 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1614 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1615 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1617 def : MipsInstAlias<"teq $rs, $rt",
1618 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1619 def : MipsInstAlias<"tge $rs, $rt",
1620 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1621 def : MipsInstAlias<"tgeu $rs, $rt",
1622 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1623 def : MipsInstAlias<"tlt $rs, $rt",
1624 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1625 def : MipsInstAlias<"tltu $rs, $rt",
1626 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1627 def : MipsInstAlias<"tne $rs, $rt",
1628 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1630 def : MipsInstAlias<"sll $rd, $rt, $rs",
1631 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1632 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1633 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1634 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1635 def : MipsInstAlias<"sub $rs, $imm",
1636 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1637 0>, ISA_MIPS1_NOT_32R6_64R6;
1638 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1639 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1640 InvertedImOperand:$imm), 0>;
1641 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1642 InvertedImOperand:$imm), 0>;
1643 def : MipsInstAlias<"sra $rd, $rt, $rs",
1644 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1645 def : MipsInstAlias<"srl $rd, $rt, $rs",
1646 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1647 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1648 def : MipsInstAlias<"sync",
1649 (SYNC 0), 1>, ISA_MIPS2;
1650 //===----------------------------------------------------------------------===//
1651 // Assembler Pseudo Instructions
1652 //===----------------------------------------------------------------------===//
1654 class LoadImmediate32<string instr_asm, Operand Od, RegisterOperand RO> :
1655 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1656 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1657 def LoadImm32 : LoadImmediate32<"li", uimm5, GPR32Opnd>;
1659 class LoadAddressFromReg32<string instr_asm, Operand MemOpnd,
1660 RegisterOperand RO> :
1661 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1662 !strconcat(instr_asm, "\t$rt, $addr")> ;
1663 def LoadAddrReg32 : LoadAddressFromReg32<"la", mem, GPR32Opnd>;
1665 class LoadAddressFromImm32<string instr_asm, Operand Od, RegisterOperand RO> :
1666 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1667 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1668 def LoadAddrImm32 : LoadAddressFromImm32<"la", uimm5, GPR32Opnd>;
1670 def JalTwoReg : MipsAsmPseudoInst<(outs GPR32Opnd:$rd), (ins GPR32Opnd:$rs),
1672 def JalOneReg : MipsAsmPseudoInst<(outs), (ins GPR32Opnd:$rs),
1675 //===----------------------------------------------------------------------===//
1676 // Arbitrary patterns that map to one or more instructions
1677 //===----------------------------------------------------------------------===//
1679 // Load/store pattern templates.
1680 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1681 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1683 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1684 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1687 let AdditionalPredicates = [NotInMicroMips] in {
1688 def : MipsPat<(i32 immSExt16:$in),
1689 (ADDiu ZERO, imm:$in)>;
1690 def : MipsPat<(i32 immZExt16:$in),
1691 (ORi ZERO, imm:$in)>;
1693 def : MipsPat<(i32 immLow16Zero:$in),
1694 (LUi (HI16 imm:$in))>;
1696 // Arbitrary immediates
1697 def : MipsPat<(i32 imm:$imm),
1698 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1700 // Carry MipsPatterns
1701 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1702 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1703 let AdditionalPredicates = [NotDSP] in {
1704 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1705 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1706 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1707 (ADDiu GPR32:$src, imm:$imm)>;
1710 // Support multiplication for pre-Mips32 targets that don't have
1711 // the MUL instruction.
1712 def : MipsPat<(mul GPR32:$lhs, GPR32:$rhs),
1713 (PseudoMFLO (PseudoMULT GPR32:$lhs, GPR32:$rhs))>,
1714 ISA_MIPS1_NOT_32R6_64R6;
1717 def : MipsPat<(MipsSync (i32 immz)),
1718 (SYNC 0)>, ISA_MIPS2;
1721 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1722 (JAL tglobaladdr:$dst)>;
1723 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1724 (JAL texternalsym:$dst)>;
1725 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1726 // (JALR GPR32:$dst)>;
1729 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1730 (TAILCALL tglobaladdr:$dst)>;
1731 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1732 (TAILCALL texternalsym:$dst)>;
1734 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1735 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1736 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1737 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1738 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1739 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1741 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1742 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1743 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1744 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1745 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1746 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1748 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1749 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1750 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1751 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1752 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1753 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1754 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1755 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1756 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1757 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1760 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1761 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1762 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1763 (ADDiu GPR32:$gp, tconstpool:$in)>;
1766 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1767 MipsPat<(MipsWrapper RC:$gp, node:$in),
1768 (ADDiuOp RC:$gp, node:$in)>;
1770 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1771 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1772 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1773 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1774 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1775 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1777 let AdditionalPredicates = [NotInMicroMips] in {
1778 // Mips does not have "not", so we expand our way
1779 def : MipsPat<(not GPR32:$in),
1780 (NOR GPR32Opnd:$in, ZERO)>;
1784 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1785 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1786 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1789 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1792 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1793 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1794 Instruction SLTiuOp, Register ZEROReg> {
1795 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1796 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1797 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1798 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1800 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1801 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1802 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1803 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1804 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1805 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1806 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1807 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1808 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1809 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1810 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1811 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1813 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1814 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1815 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1816 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1818 def : MipsPat<(brcond RC:$cond, bb:$dst),
1819 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1822 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1824 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1825 (BLEZ i32:$lhs, bb:$dst)>;
1826 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1827 (BGEZ i32:$lhs, bb:$dst)>;
1830 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1831 Instruction SLTuOp, Register ZEROReg> {
1832 def : MipsPat<(seteq RC:$lhs, 0),
1833 (SLTiuOp RC:$lhs, 1)>;
1834 def : MipsPat<(setne RC:$lhs, 0),
1835 (SLTuOp ZEROReg, RC:$lhs)>;
1836 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1837 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1838 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1839 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1842 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1843 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1844 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1845 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1846 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1849 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1850 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1851 (SLTOp RC:$rhs, RC:$lhs)>;
1852 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1853 (SLTuOp RC:$rhs, RC:$lhs)>;
1856 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1857 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1858 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1859 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1860 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1863 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1864 Instruction SLTiuOp> {
1865 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1866 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1867 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1868 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1871 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1872 defm : SetlePats<GPR32, SLT, SLTu>;
1873 defm : SetgtPats<GPR32, SLT, SLTu>;
1874 defm : SetgePats<GPR32, SLT, SLTu>;
1875 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1878 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1880 // Load halfword/word patterns.
1881 let AddedComplexity = 40 in {
1882 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1883 def : LoadRegImmPat<LH, i32, sextloadi16>;
1884 let AdditionalPredicates = [NotInMicroMips] in {
1885 def : LoadRegImmPat<LW, i32, load>;
1889 //===----------------------------------------------------------------------===//
1890 // Floating Point Support
1891 //===----------------------------------------------------------------------===//
1893 include "MipsInstrFPU.td"
1894 include "Mips64InstrInfo.td"
1895 include "MipsCondMov.td"
1897 include "Mips32r6InstrInfo.td"
1898 include "Mips64r6InstrInfo.td"
1903 include "Mips16InstrFormats.td"
1904 include "Mips16InstrInfo.td"
1907 include "MipsDSPInstrFormats.td"
1908 include "MipsDSPInstrInfo.td"
1911 include "MipsMSAInstrFormats.td"
1912 include "MipsMSAInstrInfo.td"
1915 include "MicroMipsInstrFormats.td"
1916 include "MicroMipsInstrInfo.td"
1917 include "MicroMipsInstrFPU.td"
1920 include "MicroMips32r6InstrFormats.td"
1921 include "MicroMips32r6InstrInfo.td"