1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def IsGP64bit : Predicate<"Subtarget.isGP64bit()">,
164 AssemblerPredicate<"FeatureGP64Bit">;
165 def IsGP32bit : Predicate<"!Subtarget.isGP64bit()">,
166 AssemblerPredicate<"!FeatureGP64Bit">;
167 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
168 AssemblerPredicate<"FeatureMips64">;
169 def IsGP32 : Predicate<"!Subtarget.isGP64()">,
170 AssemblerPredicate<"!FeatureGP64Bit">;
171 def IsGP64 : Predicate<"Subtarget.isGP64()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
174 AssemblerPredicate<"FeatureMips64r2">;
175 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
176 AssemblerPredicate<"FeatureN64">;
177 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
178 AssemblerPredicate<"FeatureMips16">;
179 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
180 AssemblerPredicate<"FeatureCnMips">;
181 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
182 AssemblerPredicate<"FeatureMips32">;
183 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
184 AssemblerPredicate<"FeatureMips32">;
185 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
186 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
187 AssemblerPredicate<"!FeatureMips16">;
188 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
189 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
190 AssemblerPredicate<"FeatureMicroMips">;
191 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
192 AssemblerPredicate<"!FeatureMicroMips">;
193 def IsLE : Predicate<"Subtarget.isLittle()">;
194 def IsBE : Predicate<"!Subtarget.isLittle()">;
195 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
197 //===----------------------------------------------------------------------===//
198 // Mips GPR size adjectives.
199 // They are mutually exclusive.
200 //===----------------------------------------------------------------------===//
202 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
204 //===----------------------------------------------------------------------===//
205 // Mips ISA/ASE membership and instruction group membership adjectives.
206 // They are mutually exclusive.
207 //===----------------------------------------------------------------------===//
209 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
210 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
212 class INSN_SWAP { list<Predicate> InsnPredicates = [HasSwap]; }
213 class INSN_SEINREG { list<Predicate> InsnPredicates = [HasSEInReg]; }
215 //===----------------------------------------------------------------------===//
217 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
218 let EncodingPredicates = [HasStdEnc];
222 bit isCommutable = 1;
239 bit isTerminator = 1;
242 bit hasExtraSrcRegAllocReq = 1;
243 bit isCodeGenOnly = 1;
246 class IsAsCheapAsAMove {
247 bit isAsCheapAsAMove = 1;
250 class NeverHasSideEffects {
251 bit neverHasSideEffects = 1;
254 //===----------------------------------------------------------------------===//
255 // Instruction format superclass
256 //===----------------------------------------------------------------------===//
258 include "MipsInstrFormats.td"
260 //===----------------------------------------------------------------------===//
261 // Mips Operand, Complex Patterns and Transformations Definitions.
262 //===----------------------------------------------------------------------===//
264 def MipsJumpTargetAsmOperand : AsmOperandClass {
265 let Name = "JumpTarget";
266 let ParserMethod = "ParseJumpTarget";
267 let PredicateMethod = "isImm";
268 let RenderMethod = "addImmOperands";
271 // Instruction operand types
272 def jmptarget : Operand<OtherVT> {
273 let EncoderMethod = "getJumpTargetOpValue";
274 let ParserMatchClass = MipsJumpTargetAsmOperand;
276 def brtarget : Operand<OtherVT> {
277 let EncoderMethod = "getBranchTargetOpValue";
278 let OperandType = "OPERAND_PCREL";
279 let DecoderMethod = "DecodeBranchTarget";
280 let ParserMatchClass = MipsJumpTargetAsmOperand;
282 def calltarget : Operand<iPTR> {
283 let EncoderMethod = "getJumpTargetOpValue";
284 let ParserMatchClass = MipsJumpTargetAsmOperand;
287 def simm10 : Operand<i32>;
289 def simm16 : Operand<i32> {
290 let DecoderMethod= "DecodeSimm16";
293 def simm20 : Operand<i32> {
296 def uimm20 : Operand<i32> {
299 def uimm10 : Operand<i32> {
302 def simm16_64 : Operand<i64> {
303 let DecoderMethod = "DecodeSimm16";
307 def uimmz : Operand<i32> {
308 let PrintMethod = "printUnsignedImm";
312 def uimm5 : Operand<i32> {
313 let PrintMethod = "printUnsignedImm";
316 def uimm6 : Operand<i32> {
317 let PrintMethod = "printUnsignedImm";
320 def uimm16 : Operand<i32> {
321 let PrintMethod = "printUnsignedImm";
324 def pcrel16 : Operand<i32> {
327 def MipsMemAsmOperand : AsmOperandClass {
329 let ParserMethod = "parseMemOperand";
332 def MipsInvertedImmoperand : AsmOperandClass {
334 let RenderMethod = "addImmOperands";
335 let ParserMethod = "parseInvNum";
338 def InvertedImOperand : Operand<i32> {
339 let ParserMatchClass = MipsInvertedImmoperand;
342 def InvertedImOperand64 : Operand<i64> {
343 let ParserMatchClass = MipsInvertedImmoperand;
346 class mem_generic : Operand<iPTR> {
347 let PrintMethod = "printMemOperand";
348 let MIOperandInfo = (ops ptr_rc, simm16);
349 let EncoderMethod = "getMemEncoding";
350 let ParserMatchClass = MipsMemAsmOperand;
351 let OperandType = "OPERAND_MEMORY";
355 def mem : mem_generic;
357 // MSA specific address operand
358 def mem_msa : mem_generic {
359 let MIOperandInfo = (ops ptr_rc, simm10);
360 let EncoderMethod = "getMSAMemEncoding";
363 def mem_ea : Operand<iPTR> {
364 let PrintMethod = "printMemOperandEA";
365 let MIOperandInfo = (ops ptr_rc, simm16);
366 let EncoderMethod = "getMemEncoding";
367 let OperandType = "OPERAND_MEMORY";
370 def PtrRC : Operand<iPTR> {
371 let MIOperandInfo = (ops ptr_rc);
372 let DecoderMethod = "DecodePtrRegisterClass";
373 let ParserMatchClass = GPR32AsmOperand;
376 // size operand of ext instruction
377 def size_ext : Operand<i32> {
378 let EncoderMethod = "getSizeExtEncoding";
379 let DecoderMethod = "DecodeExtSize";
382 // size operand of ins instruction
383 def size_ins : Operand<i32> {
384 let EncoderMethod = "getSizeInsEncoding";
385 let DecoderMethod = "DecodeInsSize";
388 // Transformation Function - get the lower 16 bits.
389 def LO16 : SDNodeXForm<imm, [{
390 return getImm(N, N->getZExtValue() & 0xFFFF);
393 // Transformation Function - get the higher 16 bits.
394 def HI16 : SDNodeXForm<imm, [{
395 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
399 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
401 // Node immediate is zero (e.g. insve.d)
402 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
404 // Node immediate fits as 16-bit sign extended on target immediate.
406 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
408 // Node immediate fits as 16-bit sign extended on target immediate.
410 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
412 // Node immediate fits as 15-bit sign extended on target immediate.
414 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
416 // Node immediate fits as 16-bit zero extended on target immediate.
417 // The LO16 param means that only the lower 16 bits of the node
418 // immediate are caught.
420 def immZExt16 : PatLeaf<(imm), [{
421 if (N->getValueType(0) == MVT::i32)
422 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
424 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
427 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
428 def immLow16Zero : PatLeaf<(imm), [{
429 int64_t Val = N->getSExtValue();
430 return isInt<32>(Val) && !(Val & 0xffff);
433 // shamt field must fit in 5 bits.
434 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
436 // True if (N + 1) fits in 16-bit field.
437 def immSExt16Plus1 : PatLeaf<(imm), [{
438 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
441 // Mips Address Mode! SDNode frameindex could possibily be a match
442 // since load and store instructions from stack used it.
444 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
447 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
450 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
453 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
455 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
457 //===----------------------------------------------------------------------===//
458 // Instructions specific format
459 //===----------------------------------------------------------------------===//
461 // Arithmetic and logical instructions with 3 register operands.
462 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
463 InstrItinClass Itin = NoItinerary,
464 SDPatternOperator OpNode = null_frag>:
465 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
466 !strconcat(opstr, "\t$rd, $rs, $rt"),
467 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
468 let isCommutable = isComm;
469 let isReMaterializable = 1;
470 let TwoOperandAliasConstraint = "$rd = $rs";
473 // Arithmetic and logical instructions with 2 register operands.
474 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
475 InstrItinClass Itin = NoItinerary,
476 SDPatternOperator imm_type = null_frag,
477 SDPatternOperator OpNode = null_frag> :
478 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
479 !strconcat(opstr, "\t$rt, $rs, $imm16"),
480 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
482 let isReMaterializable = 1;
483 let TwoOperandAliasConstraint = "$rs = $rt";
486 // Arithmetic Multiply ADD/SUB
487 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
488 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
489 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
490 let Defs = [HI0, LO0];
491 let Uses = [HI0, LO0];
492 let isCommutable = isComm;
496 class LogicNOR<string opstr, RegisterOperand RO>:
497 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
498 !strconcat(opstr, "\t$rd, $rs, $rt"),
499 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
500 let isCommutable = 1;
504 class shift_rotate_imm<string opstr, Operand ImmOpnd,
505 RegisterOperand RO, InstrItinClass itin,
506 SDPatternOperator OpNode = null_frag,
507 SDPatternOperator PF = null_frag> :
508 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
509 !strconcat(opstr, "\t$rd, $rt, $shamt"),
510 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
511 let TwoOperandAliasConstraint = "$rt = $rd";
514 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
515 SDPatternOperator OpNode = null_frag>:
516 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
517 !strconcat(opstr, "\t$rd, $rt, $rs"),
518 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
521 // Load Upper Imediate
522 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
523 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
524 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
525 let neverHasSideEffects = 1;
526 let isReMaterializable = 1;
530 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
531 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
532 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
533 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
534 let DecoderMethod = "DecodeMem";
535 let canFoldAsLoad = 1;
539 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
540 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
541 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
542 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
543 let DecoderMethod = "DecodeMem";
547 // Load/Store Left/Right
548 let canFoldAsLoad = 1 in
549 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
550 InstrItinClass Itin> :
551 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
552 !strconcat(opstr, "\t$rt, $addr"),
553 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
554 let DecoderMethod = "DecodeMem";
555 string Constraints = "$src = $rt";
558 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
559 InstrItinClass Itin> :
560 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
561 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
562 let DecoderMethod = "DecodeMem";
565 // Conditional Branch
566 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
567 RegisterOperand RO> :
568 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
569 !strconcat(opstr, "\t$rs, $rt, $offset"),
570 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
573 let isTerminator = 1;
574 let hasDelaySlot = 1;
578 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
579 RegisterOperand RO> :
580 InstSE<(outs), (ins RO:$rs, opnd:$offset),
581 !strconcat(opstr, "\t$rs, $offset"),
582 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
585 let isTerminator = 1;
586 let hasDelaySlot = 1;
591 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
592 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
593 !strconcat(opstr, "\t$rd, $rs, $rt"),
594 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
595 II_SLT_SLTU, FrmR, opstr>;
597 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
599 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
600 !strconcat(opstr, "\t$rt, $rs, $imm16"),
601 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
602 II_SLTI_SLTIU, FrmI, opstr>;
605 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
606 SDPatternOperator targetoperator, string bopstr> :
607 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
608 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
611 let hasDelaySlot = 1;
612 let DecoderMethod = "DecodeJumpTarget";
616 // Unconditional branch
617 class UncondBranch<Instruction BEQInst> :
618 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
619 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
621 let isTerminator = 1;
623 let hasDelaySlot = 1;
624 let AdditionalPredicates = [RelocPIC];
628 // Base class for indirect branch and return instruction classes.
629 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
630 class JumpFR<string opstr, RegisterOperand RO,
631 SDPatternOperator operator = null_frag>:
632 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
636 class IndirectBranch<string opstr, RegisterOperand RO> :
637 JumpFR<opstr, RO, brind> {
639 let isIndirectBranch = 1;
642 // Return instruction
643 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
645 let isCodeGenOnly = 1;
647 let hasExtraSrcRegAllocReq = 1;
650 // Jump and Link (Call)
651 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
652 class JumpLink<string opstr, DAGOperand opnd> :
653 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
654 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
655 let DecoderMethod = "DecodeJumpTarget";
658 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
659 Register RetReg, RegisterOperand ResRO = RO>:
660 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
661 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
663 class JumpLinkReg<string opstr, RegisterOperand RO>:
664 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
667 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
668 InstSE<(outs), (ins RO:$rs, opnd:$offset),
669 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
673 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
674 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
675 class TailCall<Instruction JumpInst> :
676 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
677 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
679 class TailCallReg<RegisterOperand RO, Instruction JRInst,
680 RegisterOperand ResRO = RO> :
681 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
682 PseudoInstExpansion<(JRInst ResRO:$rs)>;
685 class BAL_BR_Pseudo<Instruction RealInst> :
686 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
687 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
689 let isTerminator = 1;
691 let hasDelaySlot = 1;
696 class SYS_FT<string opstr> :
697 InstSE<(outs), (ins uimm20:$code_),
698 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
700 class BRK_FT<string opstr> :
701 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
702 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
706 class ER_FT<string opstr> :
707 InstSE<(outs), (ins),
708 opstr, [], NoItinerary, FrmOther, opstr>;
711 class DEI_FT<string opstr, RegisterOperand RO> :
712 InstSE<(outs RO:$rt), (ins),
713 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
716 class WAIT_FT<string opstr> :
717 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
720 let hasSideEffects = 1 in
721 class SYNC_FT<string opstr> :
722 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
723 NoItinerary, FrmOther, opstr>;
725 let hasSideEffects = 1 in
726 class TEQ_FT<string opstr, RegisterOperand RO> :
727 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
728 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
731 class TEQI_FT<string opstr, RegisterOperand RO> :
732 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
733 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
735 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
736 list<Register> DefRegs> :
737 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
739 let isCommutable = 1;
741 let neverHasSideEffects = 1;
744 // Pseudo multiply/divide instruction with explicit accumulator register
746 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
747 SDPatternOperator OpNode, InstrItinClass Itin,
748 bit IsComm = 1, bit HasSideEffects = 0,
749 bit UsesCustomInserter = 0> :
750 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
751 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
752 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
753 let isCommutable = IsComm;
754 let hasSideEffects = HasSideEffects;
755 let usesCustomInserter = UsesCustomInserter;
758 // Pseudo multiply add/sub instruction with explicit accumulator register
760 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
762 : PseudoSE<(outs ACC64:$ac),
763 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
765 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
767 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
768 string Constraints = "$acin = $ac";
771 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
772 list<Register> DefRegs> :
773 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
774 [], itin, FrmR, opstr> {
779 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
780 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
781 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
783 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
784 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
787 let neverHasSideEffects = 1;
790 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
791 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
792 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
795 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
796 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
799 let neverHasSideEffects = 1;
802 class EffectiveAddress<string opstr, RegisterOperand RO> :
803 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
804 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
805 !strconcat(opstr, "_lea")> {
806 let isCodeGenOnly = 1;
807 let DecoderMethod = "DecodeMem";
810 // Count Leading Ones/Zeros in Word
811 class CountLeading0<string opstr, RegisterOperand RO>:
812 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
813 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
814 AdditionalRequires<[HasBitCount]>;
816 class CountLeading1<string opstr, RegisterOperand RO>:
817 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
818 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
819 AdditionalRequires<[HasBitCount]>;
821 // Sign Extend in Register.
822 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
823 InstrItinClass itin> :
824 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
825 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>,
829 class SubwordSwap<string opstr, RegisterOperand RO>:
830 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
831 NoItinerary, FrmR, opstr>, INSN_SWAP {
832 let neverHasSideEffects = 1;
836 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
837 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
841 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
842 SDPatternOperator Op = null_frag>:
843 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
844 !strconcat(opstr, " $rt, $rs, $pos, $size"),
845 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
846 FrmR, opstr>, ISA_MIPS32R2;
848 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
849 SDPatternOperator Op = null_frag>:
850 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
851 !strconcat(opstr, " $rt, $rs, $pos, $size"),
852 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
853 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
854 let Constraints = "$src = $rt";
857 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
858 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
859 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
860 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
862 // Atomic Compare & Swap.
863 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
864 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
865 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
867 class LLBase<string opstr, RegisterOperand RO> :
868 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
869 [], NoItinerary, FrmI> {
870 let DecoderMethod = "DecodeMem";
874 class SCBase<string opstr, RegisterOperand RO> :
875 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
876 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
877 let DecoderMethod = "DecodeMem";
879 let Constraints = "$rt = $dst";
882 class MFC3OP<string asmstr, RegisterOperand RO> :
883 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
884 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
886 class TrapBase<Instruction RealInst>
887 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
888 PseudoInstExpansion<(RealInst 0, 0)> {
890 let isTerminator = 1;
891 let isCodeGenOnly = 1;
894 //===----------------------------------------------------------------------===//
895 // Pseudo instructions
896 //===----------------------------------------------------------------------===//
899 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
900 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
902 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
903 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
904 [(callseq_start timm:$amt)]>;
905 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
906 [(callseq_end timm:$amt1, timm:$amt2)]>;
909 let usesCustomInserter = 1 in {
910 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
911 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
912 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
913 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
914 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
915 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
916 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
917 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
918 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
919 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
920 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
921 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
922 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
923 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
924 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
925 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
926 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
927 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
929 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
930 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
931 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
933 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
934 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
935 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
938 /// Pseudo instructions for loading and storing accumulator registers.
939 let isPseudo = 1, isCodeGenOnly = 1 in {
940 def LOAD_ACC64 : Load<"", ACC64>;
941 def STORE_ACC64 : Store<"", ACC64>;
944 // We need these two pseudo instructions to avoid offset calculation for long
945 // branches. See the comment in file MipsLongBranch.cpp for detailed
948 // Expands to: lui $dst, %hi($tgt - $baltgt)
949 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
950 (ins brtarget:$tgt, brtarget:$baltgt), []>;
952 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
953 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
954 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
956 //===----------------------------------------------------------------------===//
957 // Instruction definition
958 //===----------------------------------------------------------------------===//
959 //===----------------------------------------------------------------------===//
960 // MipsI Instructions
961 //===----------------------------------------------------------------------===//
963 /// Arithmetic Instructions (ALU Immediate)
964 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
966 ADDI_FM<0x9>, IsAsCheapAsAMove;
967 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
968 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
970 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
972 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
975 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
978 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
981 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
983 /// Arithmetic Instructions (3-Operand, R-Type)
984 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
986 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
988 let Defs = [HI0, LO0] in
989 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
991 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
992 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
993 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
994 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
995 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
997 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
999 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1001 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1003 /// Shift Instructions
1004 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1005 immZExt5>, SRA_FM<0, 0>;
1006 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1007 immZExt5>, SRA_FM<2, 0>;
1008 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1009 immZExt5>, SRA_FM<3, 0>;
1010 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1012 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1014 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1017 // Rotate Instructions
1018 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1020 SRA_FM<2, 1>, ISA_MIPS32R2;
1021 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1022 SRLV_FM<6, 1>, ISA_MIPS32R2;
1024 /// Load and Store Instructions
1026 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1027 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1029 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1031 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1032 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1034 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1035 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1036 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1038 /// load/store left/right
1039 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1040 AdditionalPredicates = [NotInMicroMips] in {
1041 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1042 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1043 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1044 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1047 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1048 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1049 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1050 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1051 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1052 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1053 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1055 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1056 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1057 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1058 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1059 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1060 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1062 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1063 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1064 def TRAP : TrapBase<BREAK>;
1066 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1067 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1069 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1070 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1072 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1073 AdditionalPredicates = [NotInMicroMips] in {
1074 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1076 /// Load-linked, Store-conditional
1077 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1078 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1081 /// Jump and Branch Instructions
1082 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1083 AdditionalRequires<[RelocStatic]>, IsBranch;
1084 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1085 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1086 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1087 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1089 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1091 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1093 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1095 def B : UncondBranch<BEQ>;
1097 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1098 let AdditionalPredicates = [NotInMicroMips] in {
1099 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1100 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1102 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1103 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1104 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1105 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1106 def TAILCALL : TailCall<J>;
1107 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1109 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1111 // Exception handling related node and instructions.
1112 // The conversion sequence is:
1113 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1114 // MIPSeh_return -> (stack change + indirect branch)
1116 // MIPSeh_return takes the place of regular return instruction
1117 // but takes two arguments (V1, V0) which are used for storing
1118 // the offset and return address respectively.
1119 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1121 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1122 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1124 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1125 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1126 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1127 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1129 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1132 /// Multiply and Divide Instructions.
1133 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1135 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1137 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1139 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1142 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1143 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1144 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1145 AdditionalPredicates = [NotInMicroMips] in {
1146 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1147 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1150 /// Sign Ext In Register Instructions.
1151 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1152 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1155 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1156 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1158 /// Word Swap Bytes Within Halfwords
1159 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1162 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1164 // FrameIndexes are legalized when they are operands from load/store
1165 // instructions. The same not happens for stack address copies, so an
1166 // add op with mem ComplexPattern is used and the stack address copy
1167 // can be matched. It's similar to Sparc LEA_ADDRi
1168 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1171 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1172 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1173 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1174 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1176 let AdditionalPredicates = [NotDSP] in {
1177 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1178 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1179 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1180 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1181 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1182 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1183 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1184 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1185 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1188 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1190 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1193 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1195 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1196 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1198 /// Move Control Registers From/To CPU Registers
1199 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1200 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1201 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1202 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1204 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1206 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1207 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1208 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1210 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1212 def TLBP : TLB<"tlbp">, COP0_TLB_FM<0x08>;
1213 def TLBR : TLB<"tlbr">, COP0_TLB_FM<0x01>;
1214 def TLBWI : TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1215 def TLBWR : TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1217 //===----------------------------------------------------------------------===//
1218 // Instruction aliases
1219 //===----------------------------------------------------------------------===//
1220 def : InstAlias<"move $dst, $src",
1221 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1222 Requires<[IsGP32, NotInMicroMips]>;
1223 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1224 def : InstAlias<"addu $rs, $rt, $imm",
1225 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1226 def : InstAlias<"add $rs, $rt, $imm",
1227 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1228 def : InstAlias<"and $rs, $rt, $imm",
1229 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1230 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1231 let Predicates = [NotInMicroMips] in {
1232 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1234 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1235 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1236 def : InstAlias<"not $rt, $rs",
1237 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1238 def : InstAlias<"neg $rt, $rs",
1239 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1240 def : InstAlias<"negu $rt",
1241 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1242 def : InstAlias<"negu $rt, $rs",
1243 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1244 def : InstAlias<"slt $rs, $rt, $imm",
1245 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1246 def : InstAlias<"sltu $rt, $rs, $imm",
1247 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1248 def : InstAlias<"xor $rs, $rt, $imm",
1249 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1250 def : InstAlias<"or $rs, $rt, $imm",
1251 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1252 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1253 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1254 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1255 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1256 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1257 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1258 def : InstAlias<"bnez $rs,$offset",
1259 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1260 def : InstAlias<"beqz $rs,$offset",
1261 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1262 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1264 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1265 def : InstAlias<"break", (BREAK 0, 0), 1>;
1266 def : InstAlias<"ei", (EI ZERO), 1>;
1267 def : InstAlias<"di", (DI ZERO), 1>;
1269 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1270 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1271 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1272 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1273 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1274 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1275 def : InstAlias<"sll $rd, $rt, $rs",
1276 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1277 def : InstAlias<"sub, $rd, $rs, $imm",
1278 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1279 def : InstAlias<"sub $rs, $imm",
1280 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1282 def : InstAlias<"subu, $rd, $rs, $imm",
1283 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1284 def : InstAlias<"subu $rs, $imm",
1285 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1287 def : InstAlias<"srl $rd, $rt, $rs",
1288 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1289 //===----------------------------------------------------------------------===//
1290 // Assembler Pseudo Instructions
1291 //===----------------------------------------------------------------------===//
1293 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1294 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1295 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1296 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1298 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1299 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1300 !strconcat(instr_asm, "\t$rt, $addr")> ;
1301 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1303 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1304 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1305 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1306 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1308 //===----------------------------------------------------------------------===//
1309 // Arbitrary patterns that map to one or more instructions
1310 //===----------------------------------------------------------------------===//
1312 // Load/store pattern templates.
1313 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1314 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1316 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1317 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1320 def : MipsPat<(i32 immSExt16:$in),
1321 (ADDiu ZERO, imm:$in)>;
1322 def : MipsPat<(i32 immZExt16:$in),
1323 (ORi ZERO, imm:$in)>;
1324 def : MipsPat<(i32 immLow16Zero:$in),
1325 (LUi (HI16 imm:$in))>;
1327 // Arbitrary immediates
1328 def : MipsPat<(i32 imm:$imm),
1329 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1331 // Carry MipsPatterns
1332 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1333 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1334 let AdditionalPredicates = [NotDSP] in {
1335 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1336 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1337 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1338 (ADDiu GPR32:$src, imm:$imm)>;
1342 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1343 (JAL tglobaladdr:$dst)>;
1344 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1345 (JAL texternalsym:$dst)>;
1346 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1347 // (JALR GPR32:$dst)>;
1350 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1351 (TAILCALL tglobaladdr:$dst)>;
1352 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1353 (TAILCALL texternalsym:$dst)>;
1355 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1356 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1357 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1358 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1359 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1360 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1362 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1363 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1364 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1365 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1366 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1367 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1369 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1370 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1371 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1372 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1373 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1374 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1375 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1376 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1377 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1378 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1381 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1382 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1383 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1384 (ADDiu GPR32:$gp, tconstpool:$in)>;
1387 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1388 MipsPat<(MipsWrapper RC:$gp, node:$in),
1389 (ADDiuOp RC:$gp, node:$in)>;
1391 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1392 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1393 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1394 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1395 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1396 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1398 // Mips does not have "not", so we expand our way
1399 def : MipsPat<(not GPR32:$in),
1400 (NOR GPR32Opnd:$in, ZERO)>;
1403 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1404 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1405 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1408 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1411 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1412 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1413 Instruction SLTiuOp, Register ZEROReg> {
1414 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1415 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1416 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1417 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1419 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1420 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1421 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1422 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1423 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1424 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1425 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1426 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1427 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1428 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1429 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1430 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1432 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1433 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1434 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1435 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1437 def : MipsPat<(brcond RC:$cond, bb:$dst),
1438 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1441 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1443 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1444 (BLEZ i32:$lhs, bb:$dst)>;
1445 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1446 (BGEZ i32:$lhs, bb:$dst)>;
1449 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1450 Instruction SLTuOp, Register ZEROReg> {
1451 def : MipsPat<(seteq RC:$lhs, 0),
1452 (SLTiuOp RC:$lhs, 1)>;
1453 def : MipsPat<(setne RC:$lhs, 0),
1454 (SLTuOp ZEROReg, RC:$lhs)>;
1455 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1456 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1457 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1458 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1461 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1462 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1463 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1464 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1465 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1468 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1469 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1470 (SLTOp RC:$rhs, RC:$lhs)>;
1471 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1472 (SLTuOp RC:$rhs, RC:$lhs)>;
1475 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1476 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1477 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1478 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1479 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1482 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1483 Instruction SLTiuOp> {
1484 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1485 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1486 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1487 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1490 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1491 defm : SetlePats<GPR32, SLT, SLTu>;
1492 defm : SetgtPats<GPR32, SLT, SLTu>;
1493 defm : SetgePats<GPR32, SLT, SLTu>;
1494 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1497 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1499 // Load halfword/word patterns.
1500 let AddedComplexity = 40 in {
1501 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1502 def : LoadRegImmPat<LH, i32, sextloadi16>;
1503 def : LoadRegImmPat<LW, i32, load>;
1506 //===----------------------------------------------------------------------===//
1507 // Floating Point Support
1508 //===----------------------------------------------------------------------===//
1510 include "MipsInstrFPU.td"
1511 include "Mips64InstrInfo.td"
1512 include "MipsCondMov.td"
1517 include "Mips16InstrFormats.td"
1518 include "Mips16InstrInfo.td"
1521 include "MipsDSPInstrFormats.td"
1522 include "MipsDSPInstrInfo.td"
1525 include "MipsMSAInstrFormats.td"
1526 include "MipsMSAInstrInfo.td"
1529 include "MicroMipsInstrFormats.td"
1530 include "MicroMipsInstrInfo.td"
1531 include "MicroMipsInstrFPU.td"