1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
172 AssemblerPredicate<"FeatureMips16">;
173 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
174 AssemblerPredicate<"FeatureCnMips">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
180 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
181 AssemblerPredicate<"!FeatureMips16">;
182 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
183 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
184 AssemblerPredicate<"FeatureMicroMips">;
185 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
186 AssemblerPredicate<"!FeatureMicroMips">;
187 def IsLE : Predicate<"Subtarget.isLittle()">;
188 def IsBE : Predicate<"!Subtarget.isLittle()">;
189 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
191 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
192 let Predicates = [HasStdEnc];
196 bit isCommutable = 1;
213 bit isTerminator = 1;
216 bit hasExtraSrcRegAllocReq = 1;
217 bit isCodeGenOnly = 1;
220 class IsAsCheapAsAMove {
221 bit isAsCheapAsAMove = 1;
224 class NeverHasSideEffects {
225 bit neverHasSideEffects = 1;
228 //===----------------------------------------------------------------------===//
229 // Instruction format superclass
230 //===----------------------------------------------------------------------===//
232 include "MipsInstrFormats.td"
234 //===----------------------------------------------------------------------===//
235 // Mips Operand, Complex Patterns and Transformations Definitions.
236 //===----------------------------------------------------------------------===//
238 def MipsJumpTargetAsmOperand : AsmOperandClass {
239 let Name = "JumpTarget";
240 let ParserMethod = "ParseJumpTarget";
241 let PredicateMethod = "isImm";
242 let RenderMethod = "addImmOperands";
245 // Instruction operand types
246 def jmptarget : Operand<OtherVT> {
247 let EncoderMethod = "getJumpTargetOpValue";
248 let ParserMatchClass = MipsJumpTargetAsmOperand;
250 def brtarget : Operand<OtherVT> {
251 let EncoderMethod = "getBranchTargetOpValue";
252 let OperandType = "OPERAND_PCREL";
253 let DecoderMethod = "DecodeBranchTarget";
254 let ParserMatchClass = MipsJumpTargetAsmOperand;
256 def calltarget : Operand<iPTR> {
257 let EncoderMethod = "getJumpTargetOpValue";
258 let ParserMatchClass = MipsJumpTargetAsmOperand;
261 def simm10 : Operand<i32>;
263 def simm16 : Operand<i32> {
264 let DecoderMethod= "DecodeSimm16";
267 def simm20 : Operand<i32> {
270 def uimm20 : Operand<i32> {
273 def uimm10 : Operand<i32> {
276 def simm16_64 : Operand<i64> {
277 let DecoderMethod = "DecodeSimm16";
281 def uimmz : Operand<i32> {
282 let PrintMethod = "printUnsignedImm";
286 def uimm5 : Operand<i32> {
287 let PrintMethod = "printUnsignedImm";
290 def uimm6 : Operand<i32> {
291 let PrintMethod = "printUnsignedImm";
294 def uimm16 : Operand<i32> {
295 let PrintMethod = "printUnsignedImm";
298 def pcrel16 : Operand<i32> {
301 def MipsMemAsmOperand : AsmOperandClass {
303 let ParserMethod = "parseMemOperand";
306 def MipsInvertedImmoperand : AsmOperandClass {
308 let RenderMethod = "addImmOperands";
309 let ParserMethod = "parseInvNum";
312 def InvertedImOperand : Operand<i32> {
313 let ParserMatchClass = MipsInvertedImmoperand;
316 class mem_generic : Operand<iPTR> {
317 let PrintMethod = "printMemOperand";
318 let MIOperandInfo = (ops ptr_rc, simm16);
319 let EncoderMethod = "getMemEncoding";
320 let ParserMatchClass = MipsMemAsmOperand;
321 let OperandType = "OPERAND_MEMORY";
325 def mem : mem_generic;
327 // MSA specific address operand
328 def mem_msa : mem_generic {
329 let MIOperandInfo = (ops ptr_rc, simm10);
330 let EncoderMethod = "getMSAMemEncoding";
333 def mem_ea : Operand<iPTR> {
334 let PrintMethod = "printMemOperandEA";
335 let MIOperandInfo = (ops ptr_rc, simm16);
336 let EncoderMethod = "getMemEncoding";
337 let OperandType = "OPERAND_MEMORY";
340 def PtrRC : Operand<iPTR> {
341 let MIOperandInfo = (ops ptr_rc);
342 let DecoderMethod = "DecodePtrRegisterClass";
343 let ParserMatchClass = GPR32AsmOperand;
346 // size operand of ext instruction
347 def size_ext : Operand<i32> {
348 let EncoderMethod = "getSizeExtEncoding";
349 let DecoderMethod = "DecodeExtSize";
352 // size operand of ins instruction
353 def size_ins : Operand<i32> {
354 let EncoderMethod = "getSizeInsEncoding";
355 let DecoderMethod = "DecodeInsSize";
358 // Transformation Function - get the lower 16 bits.
359 def LO16 : SDNodeXForm<imm, [{
360 return getImm(N, N->getZExtValue() & 0xFFFF);
363 // Transformation Function - get the higher 16 bits.
364 def HI16 : SDNodeXForm<imm, [{
365 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
369 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
371 // Node immediate is zero (e.g. insve.d)
372 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
374 // Node immediate fits as 16-bit sign extended on target immediate.
376 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
378 // Node immediate fits as 16-bit sign extended on target immediate.
380 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
382 // Node immediate fits as 15-bit sign extended on target immediate.
384 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
386 // Node immediate fits as 16-bit zero extended on target immediate.
387 // The LO16 param means that only the lower 16 bits of the node
388 // immediate are caught.
390 def immZExt16 : PatLeaf<(imm), [{
391 if (N->getValueType(0) == MVT::i32)
392 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
394 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
397 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
398 def immLow16Zero : PatLeaf<(imm), [{
399 int64_t Val = N->getSExtValue();
400 return isInt<32>(Val) && !(Val & 0xffff);
403 // shamt field must fit in 5 bits.
404 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
406 // True if (N + 1) fits in 16-bit field.
407 def immSExt16Plus1 : PatLeaf<(imm), [{
408 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
411 // Mips Address Mode! SDNode frameindex could possibily be a match
412 // since load and store instructions from stack used it.
414 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
417 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
420 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
423 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
425 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
427 //===----------------------------------------------------------------------===//
428 // Instructions specific format
429 //===----------------------------------------------------------------------===//
431 // Arithmetic and logical instructions with 3 register operands.
432 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
433 InstrItinClass Itin = NoItinerary,
434 SDPatternOperator OpNode = null_frag>:
435 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
436 !strconcat(opstr, "\t$rd, $rs, $rt"),
437 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
438 let isCommutable = isComm;
439 let isReMaterializable = 1;
440 let TwoOperandAliasConstraint = "$rd = $rs";
443 // Arithmetic and logical instructions with 2 register operands.
444 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
445 InstrItinClass Itin = NoItinerary,
446 SDPatternOperator imm_type = null_frag,
447 SDPatternOperator OpNode = null_frag> :
448 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
449 !strconcat(opstr, "\t$rt, $rs, $imm16"),
450 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
452 let isReMaterializable = 1;
453 let TwoOperandAliasConstraint = "$rs = $rt";
456 // Arithmetic Multiply ADD/SUB
457 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
458 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
459 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
460 let Defs = [HI0, LO0];
461 let Uses = [HI0, LO0];
462 let isCommutable = isComm;
466 class LogicNOR<string opstr, RegisterOperand RO>:
467 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
468 !strconcat(opstr, "\t$rd, $rs, $rt"),
469 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
470 let isCommutable = 1;
474 class shift_rotate_imm<string opstr, Operand ImmOpnd,
475 RegisterOperand RO, InstrItinClass itin,
476 SDPatternOperator OpNode = null_frag,
477 SDPatternOperator PF = null_frag> :
478 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
479 !strconcat(opstr, "\t$rd, $rt, $shamt"),
480 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
482 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
483 SDPatternOperator OpNode = null_frag>:
484 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
485 !strconcat(opstr, "\t$rd, $rt, $rs"),
486 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
489 // Load Upper Imediate
490 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
491 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
492 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
493 let neverHasSideEffects = 1;
494 let isReMaterializable = 1;
498 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
499 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
500 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
501 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
502 let DecoderMethod = "DecodeMem";
503 let canFoldAsLoad = 1;
507 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
508 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
509 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
510 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
511 let DecoderMethod = "DecodeMem";
515 // Load/Store Left/Right
516 let canFoldAsLoad = 1 in
517 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
518 InstrItinClass Itin> :
519 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
520 !strconcat(opstr, "\t$rt, $addr"),
521 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
522 let DecoderMethod = "DecodeMem";
523 string Constraints = "$src = $rt";
526 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
527 InstrItinClass Itin> :
528 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
529 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
530 let DecoderMethod = "DecodeMem";
533 // Conditional Branch
534 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
535 RegisterOperand RO> :
536 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
537 !strconcat(opstr, "\t$rs, $rt, $offset"),
538 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
541 let isTerminator = 1;
542 let hasDelaySlot = 1;
546 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
547 RegisterOperand RO> :
548 InstSE<(outs), (ins RO:$rs, opnd:$offset),
549 !strconcat(opstr, "\t$rs, $offset"),
550 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
553 let isTerminator = 1;
554 let hasDelaySlot = 1;
559 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
560 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
561 !strconcat(opstr, "\t$rd, $rs, $rt"),
562 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
563 II_SLT_SLTU, FrmR, opstr>;
565 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
567 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
568 !strconcat(opstr, "\t$rt, $rs, $imm16"),
569 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
570 II_SLTI_SLTIU, FrmI, opstr>;
573 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
574 SDPatternOperator targetoperator, string bopstr> :
575 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
576 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
579 let hasDelaySlot = 1;
580 let DecoderMethod = "DecodeJumpTarget";
584 // Unconditional branch
585 class UncondBranch<Instruction BEQInst> :
586 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
587 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
589 let isTerminator = 1;
591 let hasDelaySlot = 1;
592 let Predicates = [RelocPIC, HasStdEnc];
596 // Base class for indirect branch and return instruction classes.
597 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
598 class JumpFR<string opstr, RegisterOperand RO,
599 SDPatternOperator operator = null_frag>:
600 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
604 class IndirectBranch<string opstr, RegisterOperand RO> :
605 JumpFR<opstr, RO, brind> {
607 let isIndirectBranch = 1;
610 // Return instruction
611 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
613 let isCodeGenOnly = 1;
615 let hasExtraSrcRegAllocReq = 1;
618 // Jump and Link (Call)
619 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
620 class JumpLink<string opstr, DAGOperand opnd> :
621 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
622 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
623 let DecoderMethod = "DecodeJumpTarget";
626 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
627 Register RetReg, RegisterOperand ResRO = RO>:
628 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
629 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
631 class JumpLinkReg<string opstr, RegisterOperand RO>:
632 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
635 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
636 InstSE<(outs), (ins RO:$rs, opnd:$offset),
637 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
641 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
642 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
643 class TailCall<Instruction JumpInst> :
644 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
645 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
647 class TailCallReg<RegisterOperand RO, Instruction JRInst,
648 RegisterOperand ResRO = RO> :
649 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
650 PseudoInstExpansion<(JRInst ResRO:$rs)>;
653 class BAL_BR_Pseudo<Instruction RealInst> :
654 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
655 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
657 let isTerminator = 1;
659 let hasDelaySlot = 1;
664 class SYS_FT<string opstr> :
665 InstSE<(outs), (ins uimm20:$code_),
666 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
668 class BRK_FT<string opstr> :
669 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
670 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
674 class ER_FT<string opstr> :
675 InstSE<(outs), (ins),
676 opstr, [], NoItinerary, FrmOther, opstr>;
679 class DEI_FT<string opstr, RegisterOperand RO> :
680 InstSE<(outs RO:$rt), (ins),
681 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
684 class WAIT_FT<string opstr> :
685 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
688 let hasSideEffects = 1 in
689 class SYNC_FT<string opstr> :
690 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
691 NoItinerary, FrmOther, opstr>;
693 let hasSideEffects = 1 in
694 class TEQ_FT<string opstr, RegisterOperand RO> :
695 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
696 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
699 class TEQI_FT<string opstr, RegisterOperand RO> :
700 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
701 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
703 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
704 list<Register> DefRegs> :
705 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
707 let isCommutable = 1;
709 let neverHasSideEffects = 1;
712 // Pseudo multiply/divide instruction with explicit accumulator register
714 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
715 SDPatternOperator OpNode, InstrItinClass Itin,
716 bit IsComm = 1, bit HasSideEffects = 0,
717 bit UsesCustomInserter = 0> :
718 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
719 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
720 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
721 let isCommutable = IsComm;
722 let hasSideEffects = HasSideEffects;
723 let usesCustomInserter = UsesCustomInserter;
726 // Pseudo multiply add/sub instruction with explicit accumulator register
728 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
730 : PseudoSE<(outs ACC64:$ac),
731 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
733 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
735 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
736 string Constraints = "$acin = $ac";
739 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
740 list<Register> DefRegs> :
741 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
742 [], itin, FrmR, opstr> {
747 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
748 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
749 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
751 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
752 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
755 let neverHasSideEffects = 1;
758 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
759 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
760 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
763 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
764 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
767 let neverHasSideEffects = 1;
770 class EffectiveAddress<string opstr, RegisterOperand RO> :
771 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
772 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
773 !strconcat(opstr, "_lea")> {
774 let isCodeGenOnly = 1;
775 let DecoderMethod = "DecodeMem";
778 // Count Leading Ones/Zeros in Word
779 class CountLeading0<string opstr, RegisterOperand RO>:
780 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
781 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
782 Requires<[HasBitCount, HasStdEnc]>;
784 class CountLeading1<string opstr, RegisterOperand RO>:
785 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
786 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
787 Requires<[HasBitCount, HasStdEnc]>;
789 // Sign Extend in Register.
790 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
791 InstrItinClass itin> :
792 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
793 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
794 let Predicates = [HasSEInReg, HasStdEnc];
798 class SubwordSwap<string opstr, RegisterOperand RO>:
799 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
800 NoItinerary, FrmR, opstr> {
801 let Predicates = [HasSwap, HasStdEnc];
802 let neverHasSideEffects = 1;
806 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
807 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
811 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
812 SDPatternOperator Op = null_frag>:
813 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
814 !strconcat(opstr, " $rt, $rs, $pos, $size"),
815 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
817 let Predicates = [HasMips32r2, HasStdEnc];
820 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
821 SDPatternOperator Op = null_frag>:
822 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
823 !strconcat(opstr, " $rt, $rs, $pos, $size"),
824 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
825 NoItinerary, FrmR, opstr> {
826 let Predicates = [HasMips32r2, HasStdEnc];
827 let Constraints = "$src = $rt";
830 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
831 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
832 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
833 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
835 // Atomic Compare & Swap.
836 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
837 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
838 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
840 class LLBase<string opstr, RegisterOperand RO> :
841 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
842 [], NoItinerary, FrmI> {
843 let DecoderMethod = "DecodeMem";
847 class SCBase<string opstr, RegisterOperand RO> :
848 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
849 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
850 let DecoderMethod = "DecodeMem";
852 let Constraints = "$rt = $dst";
855 class MFC3OP<string asmstr, RegisterOperand RO> :
856 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
857 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
859 class TrapBase<Instruction RealInst>
860 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
861 PseudoInstExpansion<(RealInst 0, 0)> {
863 let isTerminator = 1;
864 let isCodeGenOnly = 1;
867 //===----------------------------------------------------------------------===//
868 // Pseudo instructions
869 //===----------------------------------------------------------------------===//
872 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
873 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
875 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
876 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
877 [(callseq_start timm:$amt)]>;
878 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
879 [(callseq_end timm:$amt1, timm:$amt2)]>;
882 let usesCustomInserter = 1 in {
883 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
884 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
885 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
886 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
887 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
888 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
889 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
890 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
891 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
892 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
893 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
894 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
895 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
896 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
897 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
898 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
899 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
900 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
902 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
903 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
904 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
906 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
907 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
908 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
911 /// Pseudo instructions for loading and storing accumulator registers.
912 let isPseudo = 1, isCodeGenOnly = 1 in {
913 def LOAD_ACC64 : Load<"", ACC64>;
914 def STORE_ACC64 : Store<"", ACC64>;
917 //===----------------------------------------------------------------------===//
918 // Instruction definition
919 //===----------------------------------------------------------------------===//
920 //===----------------------------------------------------------------------===//
921 // MipsI Instructions
922 //===----------------------------------------------------------------------===//
924 /// Arithmetic Instructions (ALU Immediate)
925 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
927 ADDI_FM<0x9>, IsAsCheapAsAMove;
928 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
929 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
931 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
933 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
936 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
939 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
942 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
944 /// Arithmetic Instructions (3-Operand, R-Type)
945 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
947 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
949 let Defs = [HI0, LO0] in
950 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
952 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
953 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
954 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
955 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
956 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
958 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
960 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
962 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
964 /// Shift Instructions
965 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
966 immZExt5>, SRA_FM<0, 0>;
967 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
968 immZExt5>, SRA_FM<2, 0>;
969 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
970 immZExt5>, SRA_FM<3, 0>;
971 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
973 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
975 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
978 // Rotate Instructions
979 let Predicates = [HasMips32r2, HasStdEnc] in {
980 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
981 immZExt5>, SRA_FM<2, 1>;
982 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
986 /// Load and Store Instructions
988 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
989 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
991 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
993 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
994 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
996 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
997 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
998 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1000 /// load/store left/right
1001 let Predicates = [NotInMicroMips] in {
1002 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
1003 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
1004 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
1005 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
1008 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
1009 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
1010 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
1011 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1012 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1013 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1014 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1016 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1017 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1018 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1019 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1020 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1021 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1023 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1024 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1025 def TRAP : TrapBase<BREAK>;
1027 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1028 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1030 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1031 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1033 let Predicates = [NotInMicroMips] in {
1034 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1036 /// Load-linked, Store-conditional
1037 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1038 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1041 /// Jump and Branch Instructions
1042 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1043 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1044 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1045 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1046 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1047 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1049 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1051 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1053 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1055 def B : UncondBranch<BEQ>;
1057 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1058 let Predicates = [NotInMicroMips, HasStdEnc] in {
1059 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1060 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1062 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1063 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1064 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1065 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1066 def TAILCALL : TailCall<J>;
1067 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1069 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1071 // Exception handling related node and instructions.
1072 // The conversion sequence is:
1073 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1074 // MIPSeh_return -> (stack change + indirect branch)
1076 // MIPSeh_return takes the place of regular return instruction
1077 // but takes two arguments (V1, V0) which are used for storing
1078 // the offset and return address respectively.
1079 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1081 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1082 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1084 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1085 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1086 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1087 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1089 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1092 /// Multiply and Divide Instructions.
1093 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1095 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1097 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1099 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1102 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1103 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1104 let Predicates = [NotInMicroMips] in {
1105 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1106 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1109 /// Sign Ext In Register Instructions.
1110 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1111 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1114 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1115 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1117 /// Word Swap Bytes Within Halfwords
1118 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1121 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1123 // FrameIndexes are legalized when they are operands from load/store
1124 // instructions. The same not happens for stack address copies, so an
1125 // add op with mem ComplexPattern is used and the stack address copy
1126 // can be matched. It's similar to Sparc LEA_ADDRi
1127 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1130 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1131 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1132 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1133 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1135 let Predicates = [HasStdEnc, NotDSP] in {
1136 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1137 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1138 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1139 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1140 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1141 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1142 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1143 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1144 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1147 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1149 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1152 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1154 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1155 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1157 /// Move Control Registers From/To CPU Registers
1158 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1159 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1160 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1161 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1163 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1165 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1166 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1167 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, Requires<[HasMips32r2]>;
1169 //===----------------------------------------------------------------------===//
1170 // Instruction aliases
1171 //===----------------------------------------------------------------------===//
1172 def : InstAlias<"move $dst, $src",
1173 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1174 Requires<[NotMips64, NotInMicroMips]>;
1175 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1176 def : InstAlias<"addu $rs, $rt, $imm",
1177 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1178 def : InstAlias<"add $rs, $rt, $imm",
1179 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1180 def : InstAlias<"and $rs, $rt, $imm",
1181 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1182 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1183 let Predicates = [NotInMicroMips] in {
1184 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1186 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1187 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1188 def : InstAlias<"not $rt, $rs",
1189 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1190 def : InstAlias<"neg $rt, $rs",
1191 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1192 def : InstAlias<"negu $rt, $rs",
1193 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1194 def : InstAlias<"slt $rs, $rt, $imm",
1195 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1196 def : InstAlias<"xor $rs, $rt, $imm",
1197 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1198 def : InstAlias<"or $rs, $rt, $imm",
1199 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1200 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1201 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1202 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1203 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1204 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1205 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1206 def : InstAlias<"bnez $rs,$offset",
1207 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1208 def : InstAlias<"beqz $rs,$offset",
1209 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1210 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1212 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1213 def : InstAlias<"break", (BREAK 0, 0), 1>;
1214 def : InstAlias<"ei", (EI ZERO), 1>;
1215 def : InstAlias<"di", (DI ZERO), 1>;
1217 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1218 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1219 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1220 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1221 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1222 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1223 def : InstAlias<"sub, $rd, $rs, $imm",
1224 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1225 def : InstAlias<"subu, $rd, $rs, $imm",
1226 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1228 //===----------------------------------------------------------------------===//
1229 // Assembler Pseudo Instructions
1230 //===----------------------------------------------------------------------===//
1232 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1233 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1234 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1235 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1237 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1238 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1239 !strconcat(instr_asm, "\t$rt, $addr")> ;
1240 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1242 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1243 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1244 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1245 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1247 //===----------------------------------------------------------------------===//
1248 // Arbitrary patterns that map to one or more instructions
1249 //===----------------------------------------------------------------------===//
1251 // Load/store pattern templates.
1252 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1253 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1255 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1256 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1259 def : MipsPat<(i32 immSExt16:$in),
1260 (ADDiu ZERO, imm:$in)>;
1261 def : MipsPat<(i32 immZExt16:$in),
1262 (ORi ZERO, imm:$in)>;
1263 def : MipsPat<(i32 immLow16Zero:$in),
1264 (LUi (HI16 imm:$in))>;
1266 // Arbitrary immediates
1267 def : MipsPat<(i32 imm:$imm),
1268 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1270 // Carry MipsPatterns
1271 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1272 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1273 let Predicates = [HasStdEnc, NotDSP] in {
1274 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1275 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1276 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1277 (ADDiu GPR32:$src, imm:$imm)>;
1281 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1282 (JAL tglobaladdr:$dst)>;
1283 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1284 (JAL texternalsym:$dst)>;
1285 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1286 // (JALR GPR32:$dst)>;
1289 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1290 (TAILCALL tglobaladdr:$dst)>;
1291 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1292 (TAILCALL texternalsym:$dst)>;
1294 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1295 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1296 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1297 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1298 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1299 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1301 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1302 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1303 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1304 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1305 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1306 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1308 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1309 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1310 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1311 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1312 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1313 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1314 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1315 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1316 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1317 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1320 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1321 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1322 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1323 (ADDiu GPR32:$gp, tconstpool:$in)>;
1326 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1327 MipsPat<(MipsWrapper RC:$gp, node:$in),
1328 (ADDiuOp RC:$gp, node:$in)>;
1330 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1331 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1332 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1333 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1334 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1335 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1337 // Mips does not have "not", so we expand our way
1338 def : MipsPat<(not GPR32:$in),
1339 (NOR GPR32Opnd:$in, ZERO)>;
1342 let Predicates = [HasStdEnc] in {
1343 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1344 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1345 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1349 let Predicates = [HasStdEnc] in
1350 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1353 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1354 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1355 Instruction SLTiuOp, Register ZEROReg> {
1356 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1357 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1358 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1359 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1361 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1362 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1363 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1364 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1365 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1366 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1367 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1368 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1369 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1370 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1371 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1372 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1374 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1375 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1376 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1377 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1379 def : MipsPat<(brcond RC:$cond, bb:$dst),
1380 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1383 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1385 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1386 (BLEZ i32:$lhs, bb:$dst)>;
1387 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1388 (BGEZ i32:$lhs, bb:$dst)>;
1391 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1392 Instruction SLTuOp, Register ZEROReg> {
1393 def : MipsPat<(seteq RC:$lhs, 0),
1394 (SLTiuOp RC:$lhs, 1)>;
1395 def : MipsPat<(setne RC:$lhs, 0),
1396 (SLTuOp ZEROReg, RC:$lhs)>;
1397 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1398 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1399 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1400 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1403 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1404 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1405 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1406 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1407 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1410 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1411 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1412 (SLTOp RC:$rhs, RC:$lhs)>;
1413 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1414 (SLTuOp RC:$rhs, RC:$lhs)>;
1417 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1418 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1419 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1420 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1421 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1424 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1425 Instruction SLTiuOp> {
1426 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1427 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1428 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1429 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1432 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1433 defm : SetlePats<GPR32, SLT, SLTu>;
1434 defm : SetgtPats<GPR32, SLT, SLTu>;
1435 defm : SetgePats<GPR32, SLT, SLTu>;
1436 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1439 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1441 // Load halfword/word patterns.
1442 let AddedComplexity = 40 in {
1443 let Predicates = [HasStdEnc] in {
1444 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1445 def : LoadRegImmPat<LH, i32, sextloadi16>;
1446 def : LoadRegImmPat<LW, i32, load>;
1450 //===----------------------------------------------------------------------===//
1451 // Floating Point Support
1452 //===----------------------------------------------------------------------===//
1454 include "MipsInstrFPU.td"
1455 include "Mips64InstrInfo.td"
1456 include "MipsCondMov.td"
1461 include "Mips16InstrFormats.td"
1462 include "Mips16InstrInfo.td"
1465 include "MipsDSPInstrFormats.td"
1466 include "MipsDSPInstrInfo.td"
1469 include "MipsMSAInstrFormats.td"
1470 include "MipsMSAInstrInfo.td"
1473 include "MicroMipsInstrFormats.td"
1474 include "MicroMipsInstrInfo.td"
1475 include "MicroMipsInstrFPU.td"