1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasMips2 : Predicate<"Subtarget->hasMips2()">,
150 AssemblerPredicate<"FeatureMips2">;
151 def HasMips3_32 : Predicate<"Subtarget->hasMips3_32()">,
152 AssemblerPredicate<"FeatureMips3_32">;
153 def HasMips3_32r2 : Predicate<"Subtarget->hasMips3_32r2()">,
154 AssemblerPredicate<"FeatureMips3_32r2">;
155 def HasMips3 : Predicate<"Subtarget->hasMips3()">,
156 AssemblerPredicate<"FeatureMips3">;
157 def HasMips4_32 : Predicate<"Subtarget->hasMips4_32()">,
158 AssemblerPredicate<"FeatureMips4_32">;
159 def HasMips4_32r2 : Predicate<"Subtarget->hasMips4_32r2()">,
160 AssemblerPredicate<"FeatureMips4_32r2">;
161 def HasMips5_32r2 : Predicate<"Subtarget->hasMips5_32r2()">,
162 AssemblerPredicate<"FeatureMips5_32r2">;
163 def HasMips32 : Predicate<"Subtarget->hasMips32()">,
164 AssemblerPredicate<"FeatureMips32">;
165 def HasMips32r2 : Predicate<"Subtarget->hasMips32r2()">,
166 AssemblerPredicate<"FeatureMips32r2">;
167 def HasMips32r6 : Predicate<"Subtarget->hasMips32r6()">,
168 AssemblerPredicate<"FeatureMips32r6">;
169 def NotMips32r6 : Predicate<"!Subtarget->hasMips32r6()">,
170 AssemblerPredicate<"!FeatureMips32r6">;
171 def IsGP64bit : Predicate<"Subtarget->isGP64bit()">,
172 AssemblerPredicate<"FeatureGP64Bit">;
173 def IsGP32bit : Predicate<"!Subtarget->isGP64bit()">,
174 AssemblerPredicate<"!FeatureGP64Bit">;
175 def HasMips64 : Predicate<"Subtarget->hasMips64()">,
176 AssemblerPredicate<"FeatureMips64">;
177 def HasMips64r2 : Predicate<"Subtarget->hasMips64r2()">,
178 AssemblerPredicate<"FeatureMips64r2">;
179 def HasMips64r6 : Predicate<"Subtarget->hasMips64r6()">,
180 AssemblerPredicate<"FeatureMips64r6">;
181 def NotMips64r6 : Predicate<"!Subtarget->hasMips64r6()">,
182 AssemblerPredicate<"!FeatureMips64r6">;
183 def IsN64 : Predicate<"Subtarget->isABI_N64()">,
184 AssemblerPredicate<"FeatureN64">;
185 def InMips16Mode : Predicate<"Subtarget->inMips16Mode()">,
186 AssemblerPredicate<"FeatureMips16">;
187 def HasCnMips : Predicate<"Subtarget->hasCnMips()">,
188 AssemblerPredicate<"FeatureCnMips">;
189 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
190 AssemblerPredicate<"FeatureMips32">;
191 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
192 AssemblerPredicate<"FeatureMips32">;
193 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">;
194 def HasStdEnc : Predicate<"Subtarget->hasStandardEncoding()">,
195 AssemblerPredicate<"!FeatureMips16">;
196 def NotDSP : Predicate<"!Subtarget->hasDSP()">;
197 def InMicroMips : Predicate<"Subtarget->inMicroMipsMode()">,
198 AssemblerPredicate<"FeatureMicroMips">;
199 def NotInMicroMips : Predicate<"!Subtarget->inMicroMipsMode()">,
200 AssemblerPredicate<"!FeatureMicroMips">;
201 def IsLE : Predicate<"Subtarget->isLittle()">;
202 def IsBE : Predicate<"!Subtarget->isLittle()">;
203 def IsNotNaCl : Predicate<"!Subtarget->isTargetNaCl()">;
205 //===----------------------------------------------------------------------===//
206 // Mips GPR size adjectives.
207 // They are mutually exclusive.
208 //===----------------------------------------------------------------------===//
210 class GPR_32 { list<Predicate> GPRPredicates = [IsGP32bit]; }
211 class GPR_64 { list<Predicate> GPRPredicates = [IsGP64bit]; }
213 //===----------------------------------------------------------------------===//
214 // Mips ISA/ASE membership and instruction group membership adjectives.
215 // They are mutually exclusive.
216 //===----------------------------------------------------------------------===//
218 // FIXME: I'd prefer to use additive predicates to build the instruction sets
219 // but we are short on assembler feature bits at the moment. Using a
220 // subtractive predicate will hopefully keep us under the 32 predicate
221 // limit long enough to develop an alternative way to handle P1||P2
223 class ISA_MIPS1_NOT_32R6_64R6 {
224 list<Predicate> InsnPredicates = [NotMips32r6, NotMips64r6];
226 class ISA_MIPS2 { list<Predicate> InsnPredicates = [HasMips2]; }
227 class ISA_MIPS2_NOT_32R6_64R6 {
228 list<Predicate> InsnPredicates = [HasMips2, NotMips32r6, NotMips64r6];
230 class ISA_MIPS3 { list<Predicate> InsnPredicates = [HasMips3]; }
231 class ISA_MIPS3_NOT_32R6_64R6 {
232 list<Predicate> InsnPredicates = [HasMips3, NotMips32r6, NotMips64r6];
234 class ISA_MIPS32 { list<Predicate> InsnPredicates = [HasMips32]; }
235 class ISA_MIPS32_NOT_32R6_64R6 {
236 list<Predicate> InsnPredicates = [HasMips32, NotMips32r6, NotMips64r6];
238 class ISA_MIPS32R2 { list<Predicate> InsnPredicates = [HasMips32r2]; }
239 class ISA_MIPS32R2_NOT_32R6_64R6 {
240 list<Predicate> InsnPredicates = [HasMips32r2, NotMips32r6, NotMips64r6];
242 class ISA_MIPS64 { list<Predicate> InsnPredicates = [HasMips64]; }
243 class ISA_MIPS64_NOT_64R6 {
244 list<Predicate> InsnPredicates = [HasMips64, NotMips64r6];
246 class ISA_MIPS64R2 { list<Predicate> InsnPredicates = [HasMips64r2]; }
247 class ISA_MIPS32R6 { list<Predicate> InsnPredicates = [HasMips32r6]; }
248 class ISA_MIPS64R6 { list<Predicate> InsnPredicates = [HasMips64r6]; }
250 // The portions of MIPS-III that were also added to MIPS32
251 class INSN_MIPS3_32 { list<Predicate> InsnPredicates = [HasMips3_32]; }
253 // The portions of MIPS-III that were also added to MIPS32 but were removed in
254 // MIPS32r6 and MIPS64r6.
255 class INSN_MIPS3_32_NOT_32R6_64R6 {
256 list<Predicate> InsnPredicates = [HasMips3_32, NotMips32r6, NotMips64r6];
259 // The portions of MIPS-III that were also added to MIPS32
260 class INSN_MIPS3_32R2 { list<Predicate> InsnPredicates = [HasMips3_32r2]; }
262 // The portions of MIPS-IV that were also added to MIPS32 but were removed in
263 // MIPS32r6 and MIPS64r6.
264 class INSN_MIPS4_32_NOT_32R6_64R6 {
265 list<Predicate> InsnPredicates = [HasMips4_32, NotMips32r6, NotMips64r6];
268 // The portions of MIPS-IV that were also added to MIPS32r2 but were removed in
269 // MIPS32r6 and MIPS64r6.
270 class INSN_MIPS4_32R2_NOT_32R6_64R6 {
271 list<Predicate> InsnPredicates = [HasMips4_32r2, NotMips32r6, NotMips64r6];
274 // The portions of MIPS-V that were also added to MIPS32r2 but were removed in
275 // MIPS32r6 and MIPS64r6.
276 class INSN_MIPS5_32R2_NOT_32R6_64R6 {
277 list<Predicate> InsnPredicates = [HasMips5_32r2, NotMips32r6, NotMips64r6];
280 //===----------------------------------------------------------------------===//
282 class MipsPat<dag pattern, dag result> : Pat<pattern, result>, PredicateControl {
283 let EncodingPredicates = [HasStdEnc];
286 class MipsInstAlias<string Asm, dag Result, bit Emit = 0b1> :
287 InstAlias<Asm, Result, Emit>, PredicateControl;
290 bit isCommutable = 1;
307 bit isTerminator = 1;
310 bit hasExtraSrcRegAllocReq = 1;
311 bit isCodeGenOnly = 1;
314 class IsAsCheapAsAMove {
315 bit isAsCheapAsAMove = 1;
318 class NeverHasSideEffects {
319 bit neverHasSideEffects = 1;
322 //===----------------------------------------------------------------------===//
323 // Instruction format superclass
324 //===----------------------------------------------------------------------===//
326 include "MipsInstrFormats.td"
328 //===----------------------------------------------------------------------===//
329 // Mips Operand, Complex Patterns and Transformations Definitions.
330 //===----------------------------------------------------------------------===//
332 def MipsJumpTargetAsmOperand : AsmOperandClass {
333 let Name = "JumpTarget";
334 let ParserMethod = "parseJumpTarget";
335 let PredicateMethod = "isImm";
336 let RenderMethod = "addImmOperands";
339 // Instruction operand types
340 def jmptarget : Operand<OtherVT> {
341 let EncoderMethod = "getJumpTargetOpValue";
342 let ParserMatchClass = MipsJumpTargetAsmOperand;
344 def brtarget : Operand<OtherVT> {
345 let EncoderMethod = "getBranchTargetOpValue";
346 let OperandType = "OPERAND_PCREL";
347 let DecoderMethod = "DecodeBranchTarget";
348 let ParserMatchClass = MipsJumpTargetAsmOperand;
350 def calltarget : Operand<iPTR> {
351 let EncoderMethod = "getJumpTargetOpValue";
352 let ParserMatchClass = MipsJumpTargetAsmOperand;
355 def simm9 : Operand<i32>;
356 def simm10 : Operand<i32>;
357 def simm11 : Operand<i32>;
359 def simm16 : Operand<i32> {
360 let DecoderMethod= "DecodeSimm16";
363 def simm19_lsl2 : Operand<i32> {
364 let EncoderMethod = "getSimm19Lsl2Encoding";
365 let DecoderMethod = "DecodeSimm19Lsl2";
366 let ParserMatchClass = MipsJumpTargetAsmOperand;
369 def simm18_lsl3 : Operand<i32> {
370 let EncoderMethod = "getSimm18Lsl3Encoding";
371 let DecoderMethod = "DecodeSimm18Lsl3";
372 let ParserMatchClass = MipsJumpTargetAsmOperand;
375 def simm20 : Operand<i32> {
378 def uimm20 : Operand<i32> {
381 def uimm10 : Operand<i32> {
384 def simm16_64 : Operand<i64> {
385 let DecoderMethod = "DecodeSimm16";
389 def uimmz : Operand<i32> {
390 let PrintMethod = "printUnsignedImm";
394 def uimm2 : Operand<i32> {
395 let PrintMethod = "printUnsignedImm";
398 def uimm3 : Operand<i32> {
399 let PrintMethod = "printUnsignedImm";
402 def uimm5 : Operand<i32> {
403 let PrintMethod = "printUnsignedImm";
406 def uimm6 : Operand<i32> {
407 let PrintMethod = "printUnsignedImm";
410 def uimm16 : Operand<i32> {
411 let PrintMethod = "printUnsignedImm";
414 def pcrel16 : Operand<i32> {
417 def MipsMemAsmOperand : AsmOperandClass {
419 let ParserMethod = "parseMemOperand";
422 def MipsMemSimm11AsmOperand : AsmOperandClass {
423 let Name = "MemOffsetSimm11";
424 let SuperClasses = [MipsMemAsmOperand];
425 let RenderMethod = "addMemOperands";
426 let ParserMethod = "parseMemOperand";
427 let PredicateMethod = "isMemWithSimmOffset<11>";
428 //let DiagnosticType = "Simm11";
431 def MipsInvertedImmoperand : AsmOperandClass {
433 let RenderMethod = "addImmOperands";
434 let ParserMethod = "parseInvNum";
437 def InvertedImOperand : Operand<i32> {
438 let ParserMatchClass = MipsInvertedImmoperand;
441 def InvertedImOperand64 : Operand<i64> {
442 let ParserMatchClass = MipsInvertedImmoperand;
445 class mem_generic : Operand<iPTR> {
446 let PrintMethod = "printMemOperand";
447 let MIOperandInfo = (ops ptr_rc, simm16);
448 let EncoderMethod = "getMemEncoding";
449 let ParserMatchClass = MipsMemAsmOperand;
450 let OperandType = "OPERAND_MEMORY";
454 def mem : mem_generic;
456 // MSA specific address operand
457 def mem_msa : mem_generic {
458 let MIOperandInfo = (ops ptr_rc, simm10);
459 let EncoderMethod = "getMSAMemEncoding";
462 def mem_simm9 : mem_generic {
463 let MIOperandInfo = (ops ptr_rc, simm9);
464 let EncoderMethod = "getMemEncoding";
467 def mem_simm11 : mem_generic {
468 let MIOperandInfo = (ops ptr_rc, simm11);
469 let EncoderMethod = "getMemEncoding";
470 let ParserMatchClass = MipsMemSimm11AsmOperand;
473 def mem_ea : Operand<iPTR> {
474 let PrintMethod = "printMemOperandEA";
475 let MIOperandInfo = (ops ptr_rc, simm16);
476 let EncoderMethod = "getMemEncoding";
477 let OperandType = "OPERAND_MEMORY";
480 def PtrRC : Operand<iPTR> {
481 let MIOperandInfo = (ops ptr_rc);
482 let DecoderMethod = "DecodePtrRegisterClass";
483 let ParserMatchClass = GPR32AsmOperand;
486 // size operand of ext instruction
487 def size_ext : Operand<i32> {
488 let EncoderMethod = "getSizeExtEncoding";
489 let DecoderMethod = "DecodeExtSize";
492 // size operand of ins instruction
493 def size_ins : Operand<i32> {
494 let EncoderMethod = "getSizeInsEncoding";
495 let DecoderMethod = "DecodeInsSize";
498 // Transformation Function - get the lower 16 bits.
499 def LO16 : SDNodeXForm<imm, [{
500 return getImm(N, N->getZExtValue() & 0xFFFF);
503 // Transformation Function - get the higher 16 bits.
504 def HI16 : SDNodeXForm<imm, [{
505 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
509 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
511 // Node immediate is zero (e.g. insve.d)
512 def immz : PatLeaf<(imm), [{ return N->getSExtValue() == 0; }]>;
514 // Node immediate fits as 16-bit sign extended on target immediate.
516 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
518 // Node immediate fits as 16-bit sign extended on target immediate.
520 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
522 // Node immediate fits as 15-bit sign extended on target immediate.
524 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
526 // Node immediate fits as 16-bit zero extended on target immediate.
527 // The LO16 param means that only the lower 16 bits of the node
528 // immediate are caught.
530 def immZExt16 : PatLeaf<(imm), [{
531 if (N->getValueType(0) == MVT::i32)
532 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
534 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
537 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
538 def immLow16Zero : PatLeaf<(imm), [{
539 int64_t Val = N->getSExtValue();
540 return isInt<32>(Val) && !(Val & 0xffff);
543 // shamt field must fit in 5 bits.
544 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
546 // True if (N + 1) fits in 16-bit field.
547 def immSExt16Plus1 : PatLeaf<(imm), [{
548 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
551 // Mips Address Mode! SDNode frameindex could possibily be a match
552 // since load and store instructions from stack used it.
554 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
557 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
560 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
563 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
565 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
567 //===----------------------------------------------------------------------===//
568 // Instructions specific format
569 //===----------------------------------------------------------------------===//
571 // Arithmetic and logical instructions with 3 register operands.
572 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
573 InstrItinClass Itin = NoItinerary,
574 SDPatternOperator OpNode = null_frag>:
575 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
576 !strconcat(opstr, "\t$rd, $rs, $rt"),
577 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
578 let isCommutable = isComm;
579 let isReMaterializable = 1;
580 let TwoOperandAliasConstraint = "$rd = $rs";
583 // Arithmetic and logical instructions with 2 register operands.
584 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
585 InstrItinClass Itin = NoItinerary,
586 SDPatternOperator imm_type = null_frag,
587 SDPatternOperator OpNode = null_frag> :
588 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
589 !strconcat(opstr, "\t$rt, $rs, $imm16"),
590 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
592 let isReMaterializable = 1;
593 let TwoOperandAliasConstraint = "$rs = $rt";
596 // Arithmetic Multiply ADD/SUB
597 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
598 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
599 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
600 let Defs = [HI0, LO0];
601 let Uses = [HI0, LO0];
602 let isCommutable = isComm;
606 class LogicNOR<string opstr, RegisterOperand RO>:
607 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
608 !strconcat(opstr, "\t$rd, $rs, $rt"),
609 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
610 let isCommutable = 1;
614 class shift_rotate_imm<string opstr, Operand ImmOpnd,
615 RegisterOperand RO, InstrItinClass itin,
616 SDPatternOperator OpNode = null_frag,
617 SDPatternOperator PF = null_frag> :
618 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
619 !strconcat(opstr, "\t$rd, $rt, $shamt"),
620 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr> {
621 let TwoOperandAliasConstraint = "$rt = $rd";
624 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
625 SDPatternOperator OpNode = null_frag>:
626 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
627 !strconcat(opstr, "\t$rd, $rt, $rs"),
628 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
631 // Load Upper Imediate
632 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
633 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
634 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
635 let neverHasSideEffects = 1;
636 let isReMaterializable = 1;
640 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
641 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
642 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
643 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
644 let DecoderMethod = "DecodeMem";
645 let canFoldAsLoad = 1;
649 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
650 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
651 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
652 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
653 let DecoderMethod = "DecodeMem";
657 // Load/Store Left/Right
658 let canFoldAsLoad = 1 in
659 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
660 InstrItinClass Itin> :
661 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
662 !strconcat(opstr, "\t$rt, $addr"),
663 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
664 let DecoderMethod = "DecodeMem";
665 string Constraints = "$src = $rt";
668 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
669 InstrItinClass Itin> :
670 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
671 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
672 let DecoderMethod = "DecodeMem";
676 class LW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
677 SDPatternOperator OpNode= null_frag> :
678 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
679 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
680 let DecoderMethod = "DecodeFMem2";
684 class SW_FT2<string opstr, RegisterOperand RC, InstrItinClass Itin,
685 SDPatternOperator OpNode= null_frag> :
686 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
687 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
688 let DecoderMethod = "DecodeFMem2";
693 class LW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
694 SDPatternOperator OpNode= null_frag> :
695 InstSE<(outs RC:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
696 [(set RC:$rt, (OpNode addrDefault:$addr))], Itin, FrmFI, opstr> {
697 let DecoderMethod = "DecodeFMem3";
701 class SW_FT3<string opstr, RegisterOperand RC, InstrItinClass Itin,
702 SDPatternOperator OpNode= null_frag> :
703 InstSE<(outs), (ins RC:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
704 [(OpNode RC:$rt, addrDefault:$addr)], Itin, FrmFI, opstr> {
705 let DecoderMethod = "DecodeFMem3";
709 // Conditional Branch
710 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
711 RegisterOperand RO, bit DelaySlot = 1> :
712 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
713 !strconcat(opstr, "\t$rs, $rt, $offset"),
714 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
717 let isTerminator = 1;
718 let hasDelaySlot = DelaySlot;
722 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
723 RegisterOperand RO, bit DelaySlot = 1> :
724 InstSE<(outs), (ins RO:$rs, opnd:$offset),
725 !strconcat(opstr, "\t$rs, $offset"),
726 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
729 let isTerminator = 1;
730 let hasDelaySlot = DelaySlot;
735 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
736 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
737 !strconcat(opstr, "\t$rd, $rs, $rt"),
738 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
739 II_SLT_SLTU, FrmR, opstr>;
741 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
743 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
744 !strconcat(opstr, "\t$rt, $rs, $imm16"),
745 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
746 II_SLTI_SLTIU, FrmI, opstr>;
749 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
750 SDPatternOperator targetoperator, string bopstr> :
751 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
752 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
755 let hasDelaySlot = 1;
756 let DecoderMethod = "DecodeJumpTarget";
760 // Unconditional branch
761 class UncondBranch<Instruction BEQInst> :
762 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
763 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
765 let isTerminator = 1;
767 let hasDelaySlot = 1;
768 let AdditionalPredicates = [RelocPIC];
772 // Base class for indirect branch and return instruction classes.
773 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
774 class JumpFR<string opstr, RegisterOperand RO,
775 SDPatternOperator operator = null_frag>:
776 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
780 class IndirectBranch<string opstr, RegisterOperand RO> : JumpFR<opstr, RO> {
782 let isIndirectBranch = 1;
785 // Jump and Link (Call)
786 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
787 class JumpLink<string opstr, DAGOperand opnd> :
788 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
789 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
790 let DecoderMethod = "DecodeJumpTarget";
793 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
794 Register RetReg, RegisterOperand ResRO = RO>:
795 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
796 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
798 class JumpLinkReg<string opstr, RegisterOperand RO>:
799 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
802 class BGEZAL_FT<string opstr, DAGOperand opnd,
803 RegisterOperand RO, bit DelaySlot = 1> :
804 InstSE<(outs), (ins RO:$rs, opnd:$offset),
805 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr> {
806 let hasDelaySlot = DelaySlot;
811 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
812 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
813 class TailCall<Instruction JumpInst> :
814 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
815 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
817 class TailCallReg<RegisterOperand RO, Instruction JRInst,
818 RegisterOperand ResRO = RO> :
819 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
820 PseudoInstExpansion<(JRInst ResRO:$rs)>;
823 class BAL_BR_Pseudo<Instruction RealInst> :
824 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
825 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
827 let isTerminator = 1;
829 let hasDelaySlot = 1;
834 class SYS_FT<string opstr> :
835 InstSE<(outs), (ins uimm20:$code_),
836 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
838 class BRK_FT<string opstr> :
839 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
840 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
844 class ER_FT<string opstr> :
845 InstSE<(outs), (ins),
846 opstr, [], NoItinerary, FrmOther, opstr>;
849 class DEI_FT<string opstr, RegisterOperand RO> :
850 InstSE<(outs RO:$rt), (ins),
851 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
854 class WAIT_FT<string opstr> :
855 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
858 let hasSideEffects = 1 in
859 class SYNC_FT<string opstr> :
860 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
861 NoItinerary, FrmOther, opstr>;
863 let hasSideEffects = 1 in
864 class TEQ_FT<string opstr, RegisterOperand RO> :
865 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
866 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
869 class TEQI_FT<string opstr, RegisterOperand RO> :
870 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
871 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
873 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
874 list<Register> DefRegs> :
875 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
877 let isCommutable = 1;
879 let neverHasSideEffects = 1;
882 // Pseudo multiply/divide instruction with explicit accumulator register
884 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
885 SDPatternOperator OpNode, InstrItinClass Itin,
886 bit IsComm = 1, bit HasSideEffects = 0,
887 bit UsesCustomInserter = 0> :
888 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
889 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
890 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
891 let isCommutable = IsComm;
892 let hasSideEffects = HasSideEffects;
893 let usesCustomInserter = UsesCustomInserter;
896 // Pseudo multiply add/sub instruction with explicit accumulator register
898 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
900 : PseudoSE<(outs ACC64:$ac),
901 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
903 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
905 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
906 string Constraints = "$acin = $ac";
909 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
910 list<Register> DefRegs> :
911 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
912 [], itin, FrmR, opstr> {
917 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
918 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
919 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
921 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
922 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
925 let neverHasSideEffects = 1;
928 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
929 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
930 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
933 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
934 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
937 let neverHasSideEffects = 1;
940 class EffectiveAddress<string opstr, RegisterOperand RO> :
941 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
942 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
943 !strconcat(opstr, "_lea")> {
944 let isCodeGenOnly = 1;
945 let DecoderMethod = "DecodeMem";
948 // Count Leading Ones/Zeros in Word
949 class CountLeading0<string opstr, RegisterOperand RO>:
950 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
951 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>;
953 class CountLeading1<string opstr, RegisterOperand RO>:
954 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
955 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>;
957 // Sign Extend in Register.
958 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
959 InstrItinClass itin> :
960 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
961 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr>;
964 class SubwordSwap<string opstr, RegisterOperand RO>:
965 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
966 NoItinerary, FrmR, opstr> {
967 let neverHasSideEffects = 1;
971 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
972 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
976 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
977 SDPatternOperator Op = null_frag>:
978 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
979 !strconcat(opstr, " $rt, $rs, $pos, $size"),
980 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
981 FrmR, opstr>, ISA_MIPS32R2;
983 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
984 SDPatternOperator Op = null_frag>:
985 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
986 !strconcat(opstr, " $rt, $rs, $pos, $size"),
987 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
988 NoItinerary, FrmR, opstr>, ISA_MIPS32R2 {
989 let Constraints = "$src = $rt";
992 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
993 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
994 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
995 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
997 // Atomic Compare & Swap.
998 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
999 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
1000 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
1002 class LLBase<string opstr, RegisterOperand RO> :
1003 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
1004 [], NoItinerary, FrmI> {
1005 let DecoderMethod = "DecodeMem";
1009 class SCBase<string opstr, RegisterOperand RO> :
1010 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
1011 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
1012 let DecoderMethod = "DecodeMem";
1014 let Constraints = "$rt = $dst";
1017 class MFC3OP<string asmstr, RegisterOperand RO> :
1018 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
1019 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
1021 class TrapBase<Instruction RealInst>
1022 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
1023 PseudoInstExpansion<(RealInst 0, 0)> {
1025 let isTerminator = 1;
1026 let isCodeGenOnly = 1;
1029 //===----------------------------------------------------------------------===//
1030 // Pseudo instructions
1031 //===----------------------------------------------------------------------===//
1034 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
1035 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
1037 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
1038 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
1039 [(callseq_start timm:$amt)]>;
1040 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
1041 [(callseq_end timm:$amt1, timm:$amt2)]>;
1044 let usesCustomInserter = 1 in {
1045 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
1046 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
1047 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
1048 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
1049 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
1050 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
1051 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
1052 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
1053 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
1054 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
1055 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
1056 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
1057 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
1058 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
1059 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
1060 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
1061 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
1062 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
1064 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
1065 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
1066 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
1068 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
1069 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
1070 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
1073 /// Pseudo instructions for loading and storing accumulator registers.
1074 let isPseudo = 1, isCodeGenOnly = 1 in {
1075 def LOAD_ACC64 : Load<"", ACC64>;
1076 def STORE_ACC64 : Store<"", ACC64>;
1079 // We need these two pseudo instructions to avoid offset calculation for long
1080 // branches. See the comment in file MipsLongBranch.cpp for detailed
1083 // Expands to: lui $dst, %hi($tgt - $baltgt)
1084 def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
1085 (ins brtarget:$tgt, brtarget:$baltgt), []>;
1087 // Expands to: addiu $dst, $src, %lo($tgt - $baltgt)
1088 def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
1089 (ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
1091 //===----------------------------------------------------------------------===//
1092 // Instruction definition
1093 //===----------------------------------------------------------------------===//
1094 //===----------------------------------------------------------------------===//
1095 // MipsI Instructions
1096 //===----------------------------------------------------------------------===//
1098 /// Arithmetic Instructions (ALU Immediate)
1099 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
1101 ADDI_FM<0x9>, IsAsCheapAsAMove;
1102 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>,
1103 ISA_MIPS1_NOT_32R6_64R6;
1104 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
1106 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
1108 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
1111 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
1114 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
1117 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
1119 /// Arithmetic Instructions (3-Operand, R-Type)
1120 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
1122 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
1124 let Defs = [HI0, LO0] in
1125 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
1126 ADD_FM<0x1c, 2>, ISA_MIPS32_NOT_32R6_64R6;
1127 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
1128 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
1129 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
1130 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
1131 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
1133 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
1135 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
1137 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
1139 /// Shift Instructions
1140 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
1141 immZExt5>, SRA_FM<0, 0>;
1142 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
1143 immZExt5>, SRA_FM<2, 0>;
1144 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
1145 immZExt5>, SRA_FM<3, 0>;
1146 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
1148 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
1150 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
1153 // Rotate Instructions
1154 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
1156 SRA_FM<2, 1>, ISA_MIPS32R2;
1157 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
1158 SRLV_FM<6, 1>, ISA_MIPS32R2;
1160 /// Load and Store Instructions
1162 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
1163 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
1165 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
1167 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
1168 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
1170 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
1171 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
1172 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
1174 /// load/store left/right
1175 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1176 AdditionalPredicates = [NotInMicroMips] in {
1177 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>,
1178 ISA_MIPS1_NOT_32R6_64R6;
1179 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>,
1180 ISA_MIPS1_NOT_32R6_64R6;
1181 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>,
1182 ISA_MIPS1_NOT_32R6_64R6;
1183 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>,
1184 ISA_MIPS1_NOT_32R6_64R6;
1187 // COP2 Memory Instructions
1188 def LWC2 : LW_FT2<"lwc2", COP2Opnd, NoItinerary, load>, LW_FM<0x32>,
1189 ISA_MIPS1_NOT_32R6_64R6;
1190 def SWC2 : SW_FT2<"swc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3a>,
1191 ISA_MIPS1_NOT_32R6_64R6;
1192 def LDC2 : LW_FT2<"ldc2", COP2Opnd, NoItinerary, load>, LW_FM<0x36>,
1193 ISA_MIPS2_NOT_32R6_64R6;
1194 def SDC2 : SW_FT2<"sdc2", COP2Opnd, NoItinerary, store>, LW_FM<0x3e>,
1195 ISA_MIPS2_NOT_32R6_64R6;
1197 // COP3 Memory Instructions
1198 let DecoderNamespace = "COP3_" in {
1199 def LWC3 : LW_FT3<"lwc3", COP3Opnd, NoItinerary, load>, LW_FM<0x33>;
1200 def SWC3 : SW_FT3<"swc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3b>;
1201 def LDC3 : LW_FT3<"ldc3", COP3Opnd, NoItinerary, load>, LW_FM<0x37>,
1203 def SDC3 : SW_FT3<"sdc3", COP3Opnd, NoItinerary, store>, LW_FM<0x3f>,
1207 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM, ISA_MIPS32;
1209 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>, ISA_MIPS2;
1210 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>, ISA_MIPS2;
1211 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>, ISA_MIPS2;
1212 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>, ISA_MIPS2;
1213 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>, ISA_MIPS2;
1214 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>, ISA_MIPS2;
1216 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>,
1217 ISA_MIPS2_NOT_32R6_64R6;
1218 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>,
1219 ISA_MIPS2_NOT_32R6_64R6;
1220 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>,
1221 ISA_MIPS2_NOT_32R6_64R6;
1222 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>,
1223 ISA_MIPS2_NOT_32R6_64R6;
1224 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>,
1225 ISA_MIPS2_NOT_32R6_64R6;
1226 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>,
1227 ISA_MIPS2_NOT_32R6_64R6;
1229 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1230 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1231 def TRAP : TrapBase<BREAK>;
1232 def SDBBP : SYS_FT<"sdbbp">, SDBBP_FM, ISA_MIPS32_NOT_32R6_64R6;
1234 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>, INSN_MIPS3_32;
1235 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>, ISA_MIPS32;
1237 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>, ISA_MIPS32R2;
1238 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>, ISA_MIPS32R2;
1240 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1241 AdditionalPredicates = [NotInMicroMips] in {
1242 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1244 /// Load-linked, Store-conditional
1245 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>, ISA_MIPS2_NOT_32R6_64R6;
1246 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>, ISA_MIPS2_NOT_32R6_64R6;
1249 /// Jump and Branch Instructions
1250 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1251 AdditionalRequires<[RelocStatic]>, IsBranch;
1252 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1253 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1254 def BEQL : MMRel, CBranch<"beql", brtarget, seteq, GPR32Opnd, 0>,
1255 BEQ_FM<20>, ISA_MIPS2_NOT_32R6_64R6;
1256 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1257 def BNEL : MMRel, CBranch<"bnel", brtarget, setne, GPR32Opnd, 0>,
1258 BEQ_FM<21>, ISA_MIPS2_NOT_32R6_64R6;
1259 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1261 def BGEZL : MMRel, CBranchZero<"bgezl", brtarget, setge, GPR32Opnd, 0>,
1262 BGEZ_FM<1, 3>, ISA_MIPS2_NOT_32R6_64R6;
1263 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1265 def BGTZL : MMRel, CBranchZero<"bgtzl", brtarget, setgt, GPR32Opnd, 0>,
1266 BGEZ_FM<23, 0>, ISA_MIPS2_NOT_32R6_64R6;
1267 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1269 def BLEZL : MMRel, CBranchZero<"blezl", brtarget, setle, GPR32Opnd, 0>,
1270 BGEZ_FM<22, 0>, ISA_MIPS2_NOT_32R6_64R6;
1271 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1273 def BLTZL : MMRel, CBranchZero<"bltzl", brtarget, setlt, GPR32Opnd, 0>,
1274 BGEZ_FM<1, 2>, ISA_MIPS2_NOT_32R6_64R6;
1275 def B : UncondBranch<BEQ>;
1277 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1278 let AdditionalPredicates = [NotInMicroMips] in {
1279 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1280 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1283 // FIXME: JALX really requires either MIPS16 or microMIPS in addition to MIPS32.
1284 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>, ISA_MIPS32_NOT_32R6_64R6;
1285 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>,
1286 ISA_MIPS1_NOT_32R6_64R6;
1287 def BGEZALL : MMRel, BGEZAL_FT<"bgezall", brtarget, GPR32Opnd, 0>,
1288 BGEZAL_FM<0x13>, ISA_MIPS2_NOT_32R6_64R6;
1289 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>,
1290 ISA_MIPS1_NOT_32R6_64R6;
1291 def BLTZALL : MMRel, BGEZAL_FT<"bltzall", brtarget, GPR32Opnd, 0>,
1292 BGEZAL_FM<0x12>, ISA_MIPS2_NOT_32R6_64R6;
1293 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1294 def TAILCALL : TailCall<J>;
1295 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1297 // Indirect branches are matched as PseudoIndirectBranch/PseudoIndirectBranch64
1298 // then are expanded to JR, JR64, JALR, or JALR64 depending on the ISA.
1299 class PseudoIndirectBranchBase<RegisterOperand RO> :
1300 MipsPseudo<(outs), (ins RO:$rs), [(brind RO:$rs)], IIBranch> {
1303 let hasDelaySlot = 1;
1305 let isIndirectBranch = 1;
1308 def PseudoIndirectBranch : PseudoIndirectBranchBase<GPR32Opnd>;
1310 // Return instructions are matched as a RetRA instruction, then ar expanded
1311 // into PseudoReturn/PseudoReturn64 after register allocation. Finally,
1312 // MipsAsmPrinter expands this into JR, JR64, JALR, or JALR64 depending on the
1314 class PseudoReturnBase<RegisterOperand RO> : MipsPseudo<(outs), (ins RO:$rs),
1316 let isTerminator = 1;
1318 let hasDelaySlot = 1;
1320 let isCodeGenOnly = 1;
1322 let hasExtraSrcRegAllocReq = 1;
1325 def PseudoReturn : PseudoReturnBase<GPR32Opnd>;
1327 // Exception handling related node and instructions.
1328 // The conversion sequence is:
1329 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1330 // MIPSeh_return -> (stack change + indirect branch)
1332 // MIPSeh_return takes the place of regular return instruction
1333 // but takes two arguments (V1, V0) which are used for storing
1334 // the offset and return address respectively.
1335 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1337 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1338 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1340 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1341 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1342 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1343 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1345 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1348 /// Multiply and Divide Instructions.
1349 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1350 MULT_FM<0, 0x18>, ISA_MIPS1_NOT_32R6_64R6;
1351 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1352 MULT_FM<0, 0x19>, ISA_MIPS1_NOT_32R6_64R6;
1353 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1354 MULT_FM<0, 0x1a>, ISA_MIPS1_NOT_32R6_64R6;
1355 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1356 MULT_FM<0, 0x1b>, ISA_MIPS1_NOT_32R6_64R6;
1358 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>,
1359 ISA_MIPS1_NOT_32R6_64R6;
1360 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>,
1361 ISA_MIPS1_NOT_32R6_64R6;
1362 let EncodingPredicates = []<Predicate>, // FIXME: Lack of HasStdEnc is probably a bug
1363 AdditionalPredicates = [NotInMicroMips] in {
1364 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>,
1365 ISA_MIPS1_NOT_32R6_64R6;
1366 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>,
1367 ISA_MIPS1_NOT_32R6_64R6;
1370 /// Sign Ext In Register Instructions.
1371 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>,
1372 SEB_FM<0x10, 0x20>, ISA_MIPS32R2;
1373 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>,
1374 SEB_FM<0x18, 0x20>, ISA_MIPS32R2;
1377 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>,
1378 ISA_MIPS32_NOT_32R6_64R6;
1379 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>,
1380 ISA_MIPS32_NOT_32R6_64R6;
1382 /// Word Swap Bytes Within Halfwords
1383 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>, ISA_MIPS32R2;
1386 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1388 // FrameIndexes are legalized when they are operands from load/store
1389 // instructions. The same not happens for stack address copies, so an
1390 // add op with mem ComplexPattern is used and the stack address copy
1391 // can be matched. It's similar to Sparc LEA_ADDRi
1392 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1395 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>,
1396 ISA_MIPS32_NOT_32R6_64R6;
1397 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>,
1398 ISA_MIPS32_NOT_32R6_64R6;
1399 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>,
1400 ISA_MIPS32_NOT_32R6_64R6;
1401 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>,
1402 ISA_MIPS32_NOT_32R6_64R6;
1404 let AdditionalPredicates = [NotDSP] in {
1405 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>,
1406 ISA_MIPS1_NOT_32R6_64R6;
1407 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>,
1408 ISA_MIPS1_NOT_32R6_64R6;
1409 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>, ISA_MIPS1_NOT_32R6_64R6;
1410 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>, ISA_MIPS1_NOT_32R6_64R6;
1411 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>, ISA_MIPS1_NOT_32R6_64R6;
1412 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>,
1413 ISA_MIPS32_NOT_32R6_64R6;
1414 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>,
1415 ISA_MIPS32_NOT_32R6_64R6;
1416 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>,
1417 ISA_MIPS32_NOT_32R6_64R6;
1418 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>,
1419 ISA_MIPS32_NOT_32R6_64R6;
1422 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1423 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1424 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1425 0, 1, 1>, ISA_MIPS1_NOT_32R6_64R6;
1427 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1429 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1430 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1432 /// Move Control Registers From/To CPU Registers
1433 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>, ISA_MIPS32;
1434 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>, ISA_MIPS32;
1435 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1436 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1438 class Barrier<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1440 def SSNOP : Barrier<"ssnop">, BARRIER_FM<1>;
1441 def EHB : Barrier<"ehb">, BARRIER_FM<3>;
1442 def PAUSE : Barrier<"pause">, BARRIER_FM<5>, ISA_MIPS32R2;
1444 // JR_HB and JALR_HB are defined here using the new style naming
1445 // scheme because some of this code is shared with Mips32r6InstrInfo.td
1446 // and because of that it doesn't follow the naming convention of the
1447 // rest of the file. To avoid a mixture of old vs new style, the new
1448 // style was chosen.
1449 class JR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1450 dag OutOperandList = (outs);
1451 dag InOperandList = (ins GPROpnd:$rs);
1452 string AsmString = !strconcat(instr_asm, "\t$rs");
1453 list<dag> Pattern = [];
1456 class JALR_HB_DESC_BASE<string instr_asm, RegisterOperand GPROpnd> {
1457 dag OutOperandList = (outs GPROpnd:$rd);
1458 dag InOperandList = (ins GPROpnd:$rs);
1459 string AsmString = !strconcat(instr_asm, "\t$rd, $rs");
1460 list<dag> Pattern = [];
1463 class JR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1464 JR_HB_DESC_BASE<"jr.hb", GPR32Opnd> {
1466 let isIndirectBranch=1;
1472 class JALR_HB_DESC : InstSE<(outs), (ins), "", [], NoItinerary, FrmJ>,
1473 JALR_HB_DESC_BASE<"jalr.hb", GPR32Opnd> {
1474 let isIndirectBranch=1;
1478 class JR_HB_ENC : JR_HB_FM<8>;
1479 class JALR_HB_ENC : JALR_HB_FM<9>;
1481 def JR_HB : JR_HB_DESC, JR_HB_ENC, ISA_MIPS32_NOT_32R6_64R6;
1482 def JALR_HB : JALR_HB_DESC, JALR_HB_ENC, ISA_MIPS32;
1484 class TLB<string asmstr> : InstSE<(outs), (ins), asmstr, [], NoItinerary,
1486 def TLBP : MMRel, TLB<"tlbp">, COP0_TLB_FM<0x08>;
1487 def TLBR : MMRel, TLB<"tlbr">, COP0_TLB_FM<0x01>;
1488 def TLBWI : MMRel, TLB<"tlbwi">, COP0_TLB_FM<0x02>;
1489 def TLBWR : MMRel, TLB<"tlbwr">, COP0_TLB_FM<0x06>;
1491 class CacheOp<string instr_asm, Operand MemOpnd> :
1492 InstSE<(outs), (ins MemOpnd:$addr, uimm5:$hint),
1493 !strconcat(instr_asm, "\t$hint, $addr"), [], NoItinerary, FrmOther> {
1494 let DecoderMethod = "DecodeCacheOp";
1497 def CACHE : CacheOp<"cache", mem>, CACHEOP_FM<0b101111>,
1498 INSN_MIPS3_32_NOT_32R6_64R6;
1499 def PREF : CacheOp<"pref", mem>, CACHEOP_FM<0b110011>,
1500 INSN_MIPS3_32_NOT_32R6_64R6;
1502 //===----------------------------------------------------------------------===//
1503 // Instruction aliases
1504 //===----------------------------------------------------------------------===//
1505 def : MipsInstAlias<"move $dst, $src",
1506 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1508 let AdditionalPredicates = [NotInMicroMips];
1510 def : MipsInstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>,
1511 ISA_MIPS1_NOT_32R6_64R6;
1512 def : MipsInstAlias<"addu $rs, $rt, $imm",
1513 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1514 def : MipsInstAlias<"addu $rs, $imm",
1515 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1516 def : MipsInstAlias<"add $rs, $rt, $imm",
1517 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>,
1518 ISA_MIPS1_NOT_32R6_64R6;
1519 def : MipsInstAlias<"add $rs, $imm",
1520 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>,
1521 ISA_MIPS1_NOT_32R6_64R6;
1522 def : MipsInstAlias<"and $rs, $rt, $imm",
1523 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1524 def : MipsInstAlias<"and $rs, $imm",
1525 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rs, simm16:$imm), 0>;
1526 def : MipsInstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1527 let Predicates = [NotInMicroMips] in {
1528 def : MipsInstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1530 def : MipsInstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1531 def : MipsInstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1532 def : MipsInstAlias<"jalr.hb $rs", (JALR_HB RA, GPR32Opnd:$rs), 1>, ISA_MIPS32;
1533 def : MipsInstAlias<"not $rt, $rs",
1534 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1535 def : MipsInstAlias<"neg $rt, $rs",
1536 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1537 def : MipsInstAlias<"negu $rt",
1538 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rt), 0>;
1539 def : MipsInstAlias<"negu $rt, $rs",
1540 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1541 def : MipsInstAlias<"slt $rs, $rt, $imm",
1542 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1543 def : MipsInstAlias<"sltu $rt, $rs, $imm",
1544 (SLTiu GPR32Opnd:$rt, GPR32Opnd:$rs, simm16:$imm), 0>;
1545 def : MipsInstAlias<"xor $rs, $rt, $imm",
1546 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1547 def : MipsInstAlias<"or $rs, $rt, $imm",
1548 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1549 def : MipsInstAlias<"or $rs, $imm",
1550 (ORi GPR32Opnd:$rs, GPR32Opnd:$rs, uimm16:$imm), 0>;
1551 def : MipsInstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1552 def : MipsInstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1553 def : MipsInstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1554 def : MipsInstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1555 def : MipsInstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1556 def : MipsInstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1557 def : MipsInstAlias<"bnez $rs,$offset",
1558 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1559 def : MipsInstAlias<"beqz $rs,$offset",
1560 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1561 def : MipsInstAlias<"syscall", (SYSCALL 0), 1>;
1563 def : MipsInstAlias<"break", (BREAK 0, 0), 1>;
1564 def : MipsInstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1565 def : MipsInstAlias<"ei", (EI ZERO), 1>, ISA_MIPS32R2;
1566 def : MipsInstAlias<"di", (DI ZERO), 1>, ISA_MIPS32R2;
1568 def : MipsInstAlias<"teq $rs, $rt",
1569 (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1570 def : MipsInstAlias<"tge $rs, $rt",
1571 (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1572 def : MipsInstAlias<"tgeu $rs, $rt",
1573 (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1574 def : MipsInstAlias<"tlt $rs, $rt",
1575 (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1576 def : MipsInstAlias<"tltu $rs, $rt",
1577 (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1578 def : MipsInstAlias<"tne $rs, $rt",
1579 (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>, ISA_MIPS2;
1581 def : MipsInstAlias<"sll $rd, $rt, $rs",
1582 (SLLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1583 def : MipsInstAlias<"sub, $rd, $rs, $imm",
1584 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs,
1585 InvertedImOperand:$imm), 0>, ISA_MIPS1_NOT_32R6_64R6;
1586 def : MipsInstAlias<"sub $rs, $imm",
1587 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rs, InvertedImOperand:$imm),
1588 0>, ISA_MIPS1_NOT_32R6_64R6;
1589 def : MipsInstAlias<"subu, $rd, $rs, $imm",
1590 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs,
1591 InvertedImOperand:$imm), 0>;
1592 def : MipsInstAlias<"subu $rs, $imm", (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rs,
1593 InvertedImOperand:$imm), 0>;
1594 def : MipsInstAlias<"sra $rd, $rt, $rs",
1595 (SRAV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1596 def : MipsInstAlias<"srl $rd, $rt, $rs",
1597 (SRLV GPR32Opnd:$rd, GPR32Opnd:$rt, GPR32Opnd:$rs), 0>;
1598 def : MipsInstAlias<"sdbbp", (SDBBP 0)>, ISA_MIPS32_NOT_32R6_64R6;
1599 def : MipsInstAlias<"sync",
1600 (SYNC 0), 1>, ISA_MIPS2;
1601 //===----------------------------------------------------------------------===//
1602 // Assembler Pseudo Instructions
1603 //===----------------------------------------------------------------------===//
1605 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1606 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1607 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1608 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1610 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1611 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1612 !strconcat(instr_asm, "\t$rt, $addr")> ;
1613 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1615 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1616 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1617 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1618 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1620 //===----------------------------------------------------------------------===//
1621 // Arbitrary patterns that map to one or more instructions
1622 //===----------------------------------------------------------------------===//
1624 // Load/store pattern templates.
1625 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1626 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1628 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1629 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1632 def : MipsPat<(i32 immSExt16:$in),
1633 (ADDiu ZERO, imm:$in)>;
1634 def : MipsPat<(i32 immZExt16:$in),
1635 (ORi ZERO, imm:$in)>;
1636 def : MipsPat<(i32 immLow16Zero:$in),
1637 (LUi (HI16 imm:$in))>;
1639 // Arbitrary immediates
1640 def : MipsPat<(i32 imm:$imm),
1641 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1643 // Carry MipsPatterns
1644 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1645 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1646 let AdditionalPredicates = [NotDSP] in {
1647 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1648 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1649 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1650 (ADDiu GPR32:$src, imm:$imm)>;
1654 def : MipsPat<(MipsSync (i32 immz)),
1655 (SYNC 0)>, ISA_MIPS2;
1658 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1659 (JAL tglobaladdr:$dst)>;
1660 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1661 (JAL texternalsym:$dst)>;
1662 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1663 // (JALR GPR32:$dst)>;
1666 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1667 (TAILCALL tglobaladdr:$dst)>;
1668 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1669 (TAILCALL texternalsym:$dst)>;
1671 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1672 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1673 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1674 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1675 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1676 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1678 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1679 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1680 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1681 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1682 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1683 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1685 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1686 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1687 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1688 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1689 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1690 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1691 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1692 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1693 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1694 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1697 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1698 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1699 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1700 (ADDiu GPR32:$gp, tconstpool:$in)>;
1703 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1704 MipsPat<(MipsWrapper RC:$gp, node:$in),
1705 (ADDiuOp RC:$gp, node:$in)>;
1707 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1708 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1709 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1710 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1711 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1712 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1714 // Mips does not have "not", so we expand our way
1715 def : MipsPat<(not GPR32:$in),
1716 (NOR GPR32Opnd:$in, ZERO)>;
1719 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1720 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1721 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1724 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1727 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1728 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1729 Instruction SLTiuOp, Register ZEROReg> {
1730 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1731 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1732 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1733 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1735 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1736 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1737 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1738 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1739 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1740 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1741 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1742 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1743 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1744 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1745 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1746 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1748 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1749 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1750 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1751 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1753 def : MipsPat<(brcond RC:$cond, bb:$dst),
1754 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1757 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1759 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1760 (BLEZ i32:$lhs, bb:$dst)>;
1761 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1762 (BGEZ i32:$lhs, bb:$dst)>;
1765 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1766 Instruction SLTuOp, Register ZEROReg> {
1767 def : MipsPat<(seteq RC:$lhs, 0),
1768 (SLTiuOp RC:$lhs, 1)>;
1769 def : MipsPat<(setne RC:$lhs, 0),
1770 (SLTuOp ZEROReg, RC:$lhs)>;
1771 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1772 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1773 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1774 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1777 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1778 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1779 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1780 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1781 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1784 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1785 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1786 (SLTOp RC:$rhs, RC:$lhs)>;
1787 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1788 (SLTuOp RC:$rhs, RC:$lhs)>;
1791 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1792 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1793 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1794 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1795 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1798 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1799 Instruction SLTiuOp> {
1800 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1801 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1802 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1803 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1806 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1807 defm : SetlePats<GPR32, SLT, SLTu>;
1808 defm : SetgtPats<GPR32, SLT, SLTu>;
1809 defm : SetgePats<GPR32, SLT, SLTu>;
1810 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1813 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1815 // Load halfword/word patterns.
1816 let AddedComplexity = 40 in {
1817 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1818 def : LoadRegImmPat<LH, i32, sextloadi16>;
1819 def : LoadRegImmPat<LW, i32, load>;
1822 //===----------------------------------------------------------------------===//
1823 // Floating Point Support
1824 //===----------------------------------------------------------------------===//
1826 include "MipsInstrFPU.td"
1827 include "Mips64InstrInfo.td"
1828 include "MipsCondMov.td"
1830 include "Mips32r6InstrInfo.td"
1831 include "Mips64r6InstrInfo.td"
1836 include "Mips16InstrFormats.td"
1837 include "Mips16InstrInfo.td"
1840 include "MipsDSPInstrFormats.td"
1841 include "MipsDSPInstrInfo.td"
1844 include "MipsMSAInstrFormats.td"
1845 include "MipsMSAInstrInfo.td"
1848 include "MicroMipsInstrFormats.td"
1849 include "MicroMipsInstrInfo.td"
1850 include "MicroMipsInstrFPU.td"