1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MFLOHI : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVT<1, untyped>]>;
27 def SDT_MTLOHI : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>,
28 SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
29 def SDT_MipsMultDiv : SDTypeProfile<1, 2, [SDTCisVT<0, untyped>, SDTCisInt<1>,
31 def SDT_MipsMAddMSub : SDTypeProfile<1, 3,
32 [SDTCisVT<0, untyped>, SDTCisSameAs<0, 3>,
33 SDTCisVT<1, i32>, SDTCisSameAs<1, 2>]>;
34 def SDT_MipsDivRem16 : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
36 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
38 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
40 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
42 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
43 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
46 def SDTMipsLoadLR : SDTypeProfile<1, 2,
47 [SDTCisInt<0>, SDTCisPtrTy<1>,
51 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
52 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
56 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
57 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
59 // Hi and Lo nodes are used to handle global addresses. Used on
60 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
61 // static model. (nothing to do with Mips Registers Hi and Lo)
62 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
63 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
64 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
66 // TlsGd node is used to handle General Dynamic TLS
67 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
69 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
70 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
71 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
74 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
77 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
78 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
80 // These are target-independent nodes, but have target-specific formats.
81 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
82 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
83 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
84 [SDNPHasChain, SDNPSideEffect,
85 SDNPOptInGlue, SDNPOutGlue]>;
87 // Nodes used to extract LO/HI registers.
88 def MipsMFHI : SDNode<"MipsISD::MFHI", SDT_MFLOHI>;
89 def MipsMFLO : SDNode<"MipsISD::MFLO", SDT_MFLOHI>;
91 // Node used to insert 32-bit integers to LOHI register pair.
92 def MipsMTLOHI : SDNode<"MipsISD::MTLOHI", SDT_MTLOHI>;
95 def MipsMult : SDNode<"MipsISD::Mult", SDT_MipsMultDiv>;
96 def MipsMultu : SDNode<"MipsISD::Multu", SDT_MipsMultDiv>;
99 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub>;
100 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub>;
101 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub>;
102 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub>;
105 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsMultDiv>;
106 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsMultDiv>;
107 def MipsDivRem16 : SDNode<"MipsISD::DivRem16", SDT_MipsDivRem16,
109 def MipsDivRemU16 : SDNode<"MipsISD::DivRemU16", SDT_MipsDivRem16,
112 // Target constant nodes that are not part of any isel patterns and remain
113 // unchanged can cause instructions with illegal operands to be emitted.
114 // Wrapper node patterns give the instruction selector a chance to replace
115 // target constant nodes that would otherwise remain unchanged with ADDiu
116 // nodes. Without these wrapper node patterns, the following conditional move
117 // instruction is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
119 // movn %got(d)($gp), %got(c)($gp), $4
120 // This instruction is illegal since movn can take only register operands.
122 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
124 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
126 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
127 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
129 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
130 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
131 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
132 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
133 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
134 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
136 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
137 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
138 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
139 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
140 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
141 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
143 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
144 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
146 //===----------------------------------------------------------------------===//
147 // Mips Instruction Predicate Definitions.
148 //===----------------------------------------------------------------------===//
149 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
150 AssemblerPredicate<"FeatureSEInReg">;
151 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
152 AssemblerPredicate<"FeatureBitCount">;
153 def HasSwap : Predicate<"Subtarget.hasSwap()">,
154 AssemblerPredicate<"FeatureSwap">;
155 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
156 AssemblerPredicate<"FeatureCondMov">;
157 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
158 AssemblerPredicate<"FeatureFPIdx">;
159 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
160 AssemblerPredicate<"FeatureMips32">;
161 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
162 AssemblerPredicate<"FeatureMips32r2">;
163 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
164 AssemblerPredicate<"FeatureMips64">;
165 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
166 AssemblerPredicate<"!FeatureMips64">;
167 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
168 AssemblerPredicate<"FeatureMips64r2">;
169 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
170 AssemblerPredicate<"FeatureN64">;
171 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
172 AssemblerPredicate<"FeatureMips16">;
173 def HasCnMips : Predicate<"Subtarget.hasCnMips()">,
174 AssemblerPredicate<"FeatureCnMips">;
175 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
176 AssemblerPredicate<"FeatureMips32">;
177 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
178 AssemblerPredicate<"FeatureMips32">;
179 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
180 AssemblerPredicate<"FeatureMips32">;
181 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
182 AssemblerPredicate<"!FeatureMips16">;
183 def NotDSP : Predicate<"!Subtarget.hasDSP()">;
184 def InMicroMips : Predicate<"Subtarget.inMicroMipsMode()">,
185 AssemblerPredicate<"FeatureMicroMips">;
186 def NotInMicroMips : Predicate<"!Subtarget.inMicroMipsMode()">,
187 AssemblerPredicate<"!FeatureMicroMips">;
188 def IsLE : Predicate<"Subtarget.isLittle()">;
189 def IsBE : Predicate<"!Subtarget.isLittle()">;
190 def IsNotNaCl : Predicate<"!Subtarget.isTargetNaCl()">;
192 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
193 let Predicates = [HasStdEnc];
197 bit isCommutable = 1;
214 bit isTerminator = 1;
217 bit hasExtraSrcRegAllocReq = 1;
218 bit isCodeGenOnly = 1;
221 class IsAsCheapAsAMove {
222 bit isAsCheapAsAMove = 1;
225 class NeverHasSideEffects {
226 bit neverHasSideEffects = 1;
229 //===----------------------------------------------------------------------===//
230 // Instruction format superclass
231 //===----------------------------------------------------------------------===//
233 include "MipsInstrFormats.td"
235 //===----------------------------------------------------------------------===//
236 // Mips Operand, Complex Patterns and Transformations Definitions.
237 //===----------------------------------------------------------------------===//
239 // Instruction operand types
240 def jmptarget : Operand<OtherVT> {
241 let EncoderMethod = "getJumpTargetOpValue";
243 def brtarget : Operand<OtherVT> {
244 let EncoderMethod = "getBranchTargetOpValue";
245 let OperandType = "OPERAND_PCREL";
246 let DecoderMethod = "DecodeBranchTarget";
248 def calltarget : Operand<iPTR> {
249 let EncoderMethod = "getJumpTargetOpValue";
252 def simm10 : Operand<i32>;
254 def simm16 : Operand<i32> {
255 let DecoderMethod= "DecodeSimm16";
258 def simm20 : Operand<i32> {
261 def uimm20 : Operand<i32> {
264 def uimm10 : Operand<i32> {
267 def simm16_64 : Operand<i64> {
268 let DecoderMethod = "DecodeSimm16";
272 def uimm5 : Operand<i32> {
273 let PrintMethod = "printUnsignedImm";
276 def uimm6 : Operand<i32> {
277 let PrintMethod = "printUnsignedImm";
280 def uimm16 : Operand<i32> {
281 let PrintMethod = "printUnsignedImm";
284 def pcrel16 : Operand<i32> {
287 def MipsMemAsmOperand : AsmOperandClass {
289 let ParserMethod = "parseMemOperand";
292 def MipsInvertedImmoperand : AsmOperandClass {
294 let RenderMethod = "addImmOperands";
295 let ParserMethod = "parseInvNum";
298 def PtrRegAsmOperand : AsmOperandClass {
300 let ParserMethod = "parsePtrReg";
304 def InvertedImOperand : Operand<i32> {
305 let ParserMatchClass = MipsInvertedImmoperand;
308 class mem_generic : Operand<iPTR> {
309 let PrintMethod = "printMemOperand";
310 let MIOperandInfo = (ops ptr_rc, simm16);
311 let EncoderMethod = "getMemEncoding";
312 let ParserMatchClass = MipsMemAsmOperand;
313 let OperandType = "OPERAND_MEMORY";
317 def mem : mem_generic;
319 // MSA specific address operand
320 def mem_msa : mem_generic {
321 let MIOperandInfo = (ops ptr_rc, simm10);
322 let EncoderMethod = "getMSAMemEncoding";
325 def mem_ea : Operand<iPTR> {
326 let PrintMethod = "printMemOperandEA";
327 let MIOperandInfo = (ops ptr_rc, simm16);
328 let EncoderMethod = "getMemEncoding";
329 let OperandType = "OPERAND_MEMORY";
332 def PtrRC : Operand<iPTR> {
333 let MIOperandInfo = (ops ptr_rc);
334 let DecoderMethod = "DecodePtrRegisterClass";
335 let ParserMatchClass = PtrRegAsmOperand;
338 // size operand of ext instruction
339 def size_ext : Operand<i32> {
340 let EncoderMethod = "getSizeExtEncoding";
341 let DecoderMethod = "DecodeExtSize";
344 // size operand of ins instruction
345 def size_ins : Operand<i32> {
346 let EncoderMethod = "getSizeInsEncoding";
347 let DecoderMethod = "DecodeInsSize";
350 // Transformation Function - get the lower 16 bits.
351 def LO16 : SDNodeXForm<imm, [{
352 return getImm(N, N->getZExtValue() & 0xFFFF);
355 // Transformation Function - get the higher 16 bits.
356 def HI16 : SDNodeXForm<imm, [{
357 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
361 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
363 // Node immediate fits as 16-bit sign extended on target immediate.
365 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
367 // Node immediate fits as 16-bit sign extended on target immediate.
369 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
371 // Node immediate fits as 15-bit sign extended on target immediate.
373 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
375 // Node immediate fits as 16-bit zero extended on target immediate.
376 // The LO16 param means that only the lower 16 bits of the node
377 // immediate are caught.
379 def immZExt16 : PatLeaf<(imm), [{
380 if (N->getValueType(0) == MVT::i32)
381 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
383 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
386 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
387 def immLow16Zero : PatLeaf<(imm), [{
388 int64_t Val = N->getSExtValue();
389 return isInt<32>(Val) && !(Val & 0xffff);
392 // shamt field must fit in 5 bits.
393 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
395 // True if (N + 1) fits in 16-bit field.
396 def immSExt16Plus1 : PatLeaf<(imm), [{
397 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
400 // Mips Address Mode! SDNode frameindex could possibily be a match
401 // since load and store instructions from stack used it.
403 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
406 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
409 ComplexPattern<iPTR, 2, "selectAddrRegReg", [frameindex]>;
412 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
414 def addrimm10 : ComplexPattern<iPTR, 2, "selectIntAddrMSA", [frameindex]>;
416 //===----------------------------------------------------------------------===//
417 // Instructions specific format
418 //===----------------------------------------------------------------------===//
420 // Arithmetic and logical instructions with 3 register operands.
421 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
422 InstrItinClass Itin = NoItinerary,
423 SDPatternOperator OpNode = null_frag>:
424 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
425 !strconcat(opstr, "\t$rd, $rs, $rt"),
426 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR, opstr> {
427 let isCommutable = isComm;
428 let isReMaterializable = 1;
431 // Arithmetic and logical instructions with 2 register operands.
432 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
433 InstrItinClass Itin = NoItinerary,
434 SDPatternOperator imm_type = null_frag,
435 SDPatternOperator OpNode = null_frag> :
436 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
437 !strconcat(opstr, "\t$rt, $rs, $imm16"),
438 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))],
440 let isReMaterializable = 1;
441 let TwoOperandAliasConstraint = "$rs = $rt";
444 // Arithmetic Multiply ADD/SUB
445 class MArithR<string opstr, InstrItinClass itin, bit isComm = 0> :
446 InstSE<(outs), (ins GPR32Opnd:$rs, GPR32Opnd:$rt),
447 !strconcat(opstr, "\t$rs, $rt"), [], itin, FrmR, opstr> {
448 let Defs = [HI0, LO0];
449 let Uses = [HI0, LO0];
450 let isCommutable = isComm;
454 class LogicNOR<string opstr, RegisterOperand RO>:
455 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
456 !strconcat(opstr, "\t$rd, $rs, $rt"),
457 [(set RO:$rd, (not (or RO:$rs, RO:$rt)))], II_NOR, FrmR, opstr> {
458 let isCommutable = 1;
462 class shift_rotate_imm<string opstr, Operand ImmOpnd,
463 RegisterOperand RO, InstrItinClass itin,
464 SDPatternOperator OpNode = null_frag,
465 SDPatternOperator PF = null_frag> :
466 InstSE<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt),
467 !strconcat(opstr, "\t$rd, $rt, $shamt"),
468 [(set RO:$rd, (OpNode RO:$rt, PF:$shamt))], itin, FrmR, opstr>;
470 class shift_rotate_reg<string opstr, RegisterOperand RO, InstrItinClass itin,
471 SDPatternOperator OpNode = null_frag>:
472 InstSE<(outs RO:$rd), (ins RO:$rt, GPR32Opnd:$rs),
473 !strconcat(opstr, "\t$rd, $rt, $rs"),
474 [(set RO:$rd, (OpNode RO:$rt, GPR32Opnd:$rs))], itin, FrmR,
477 // Load Upper Imediate
478 class LoadUpper<string opstr, RegisterOperand RO, Operand Imm>:
479 InstSE<(outs RO:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
480 [], II_LUI, FrmI, opstr>, IsAsCheapAsAMove {
481 let neverHasSideEffects = 1;
482 let isReMaterializable = 1;
486 class Load<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
487 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
488 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
489 [(set RO:$rt, (OpNode Addr:$addr))], Itin, FrmI, opstr> {
490 let DecoderMethod = "DecodeMem";
491 let canFoldAsLoad = 1;
495 class Store<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag,
496 InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> :
497 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
498 [(OpNode RO:$rt, Addr:$addr)], Itin, FrmI, opstr> {
499 let DecoderMethod = "DecodeMem";
503 // Load/Store Left/Right
504 let canFoldAsLoad = 1 in
505 class LoadLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
506 InstrItinClass Itin> :
507 InstSE<(outs RO:$rt), (ins mem:$addr, RO:$src),
508 !strconcat(opstr, "\t$rt, $addr"),
509 [(set RO:$rt, (OpNode addr:$addr, RO:$src))], Itin, FrmI> {
510 let DecoderMethod = "DecodeMem";
511 string Constraints = "$src = $rt";
514 class StoreLeftRight<string opstr, SDNode OpNode, RegisterOperand RO,
515 InstrItinClass Itin> :
516 InstSE<(outs), (ins RO:$rt, mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
517 [(OpNode RO:$rt, addr:$addr)], Itin, FrmI> {
518 let DecoderMethod = "DecodeMem";
521 // Conditional Branch
522 class CBranch<string opstr, DAGOperand opnd, PatFrag cond_op,
523 RegisterOperand RO> :
524 InstSE<(outs), (ins RO:$rs, RO:$rt, opnd:$offset),
525 !strconcat(opstr, "\t$rs, $rt, $offset"),
526 [(brcond (i32 (cond_op RO:$rs, RO:$rt)), bb:$offset)], IIBranch,
529 let isTerminator = 1;
530 let hasDelaySlot = 1;
534 class CBranchZero<string opstr, DAGOperand opnd, PatFrag cond_op,
535 RegisterOperand RO> :
536 InstSE<(outs), (ins RO:$rs, opnd:$offset),
537 !strconcat(opstr, "\t$rs, $offset"),
538 [(brcond (i32 (cond_op RO:$rs, 0)), bb:$offset)], IIBranch,
541 let isTerminator = 1;
542 let hasDelaySlot = 1;
547 class SetCC_R<string opstr, PatFrag cond_op, RegisterOperand RO> :
548 InstSE<(outs GPR32Opnd:$rd), (ins RO:$rs, RO:$rt),
549 !strconcat(opstr, "\t$rd, $rs, $rt"),
550 [(set GPR32Opnd:$rd, (cond_op RO:$rs, RO:$rt))],
551 II_SLT_SLTU, FrmR, opstr>;
553 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
555 InstSE<(outs GPR32Opnd:$rt), (ins RO:$rs, Od:$imm16),
556 !strconcat(opstr, "\t$rt, $rs, $imm16"),
557 [(set GPR32Opnd:$rt, (cond_op RO:$rs, imm_type:$imm16))],
558 II_SLTI_SLTIU, FrmI, opstr>;
561 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
562 SDPatternOperator targetoperator, string bopstr> :
563 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
564 [(operator targetoperator:$target)], IIBranch, FrmJ, bopstr> {
567 let hasDelaySlot = 1;
568 let DecoderMethod = "DecodeJumpTarget";
572 // Unconditional branch
573 class UncondBranch<Instruction BEQInst> :
574 PseudoSE<(outs), (ins brtarget:$offset), [(br bb:$offset)], IIBranch>,
575 PseudoInstExpansion<(BEQInst ZERO, ZERO, brtarget:$offset)> {
577 let isTerminator = 1;
579 let hasDelaySlot = 1;
580 let Predicates = [RelocPIC, HasStdEnc];
584 // Base class for indirect branch and return instruction classes.
585 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
586 class JumpFR<string opstr, RegisterOperand RO,
587 SDPatternOperator operator = null_frag>:
588 InstSE<(outs), (ins RO:$rs), "jr\t$rs", [(operator RO:$rs)], IIBranch,
592 class IndirectBranch<string opstr, RegisterOperand RO> :
593 JumpFR<opstr, RO, brind> {
595 let isIndirectBranch = 1;
598 // Return instruction
599 class RetBase<string opstr, RegisterOperand RO>: JumpFR<opstr, RO> {
601 let isCodeGenOnly = 1;
603 let hasExtraSrcRegAllocReq = 1;
606 // Jump and Link (Call)
607 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
608 class JumpLink<string opstr, DAGOperand opnd> :
609 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
610 [(MipsJmpLink imm:$target)], IIBranch, FrmJ, opstr> {
611 let DecoderMethod = "DecodeJumpTarget";
614 class JumpLinkRegPseudo<RegisterOperand RO, Instruction JALRInst,
615 Register RetReg, RegisterOperand ResRO = RO>:
616 PseudoSE<(outs), (ins RO:$rs), [(MipsJmpLink RO:$rs)], IIBranch>,
617 PseudoInstExpansion<(JALRInst RetReg, ResRO:$rs)>;
619 class JumpLinkReg<string opstr, RegisterOperand RO>:
620 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
623 class BGEZAL_FT<string opstr, DAGOperand opnd, RegisterOperand RO> :
624 InstSE<(outs), (ins RO:$rs, opnd:$offset),
625 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>;
629 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1,
630 hasExtraSrcRegAllocReq = 1, Defs = [AT] in {
631 class TailCall<Instruction JumpInst> :
632 PseudoSE<(outs), (ins calltarget:$target), [], IIBranch>,
633 PseudoInstExpansion<(JumpInst jmptarget:$target)>;
635 class TailCallReg<RegisterOperand RO, Instruction JRInst,
636 RegisterOperand ResRO = RO> :
637 PseudoSE<(outs), (ins RO:$rs), [(MipsTailCall RO:$rs)], IIBranch>,
638 PseudoInstExpansion<(JRInst ResRO:$rs)>;
641 class BAL_BR_Pseudo<Instruction RealInst> :
642 PseudoSE<(outs), (ins brtarget:$offset), [], IIBranch>,
643 PseudoInstExpansion<(RealInst ZERO, brtarget:$offset)> {
645 let isTerminator = 1;
647 let hasDelaySlot = 1;
652 class SYS_FT<string opstr> :
653 InstSE<(outs), (ins uimm20:$code_),
654 !strconcat(opstr, "\t$code_"), [], NoItinerary, FrmI, opstr>;
656 class BRK_FT<string opstr> :
657 InstSE<(outs), (ins uimm10:$code_1, uimm10:$code_2),
658 !strconcat(opstr, "\t$code_1, $code_2"), [], NoItinerary,
662 class ER_FT<string opstr> :
663 InstSE<(outs), (ins),
664 opstr, [], NoItinerary, FrmOther, opstr>;
667 class DEI_FT<string opstr, RegisterOperand RO> :
668 InstSE<(outs RO:$rt), (ins),
669 !strconcat(opstr, "\t$rt"), [], NoItinerary, FrmOther, opstr>;
672 class WAIT_FT<string opstr> :
673 InstSE<(outs), (ins), opstr, [], NoItinerary, FrmOther, opstr>;
676 let hasSideEffects = 1 in
677 class SYNC_FT<string opstr> :
678 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
679 NoItinerary, FrmOther, opstr>;
681 let hasSideEffects = 1 in
682 class TEQ_FT<string opstr, RegisterOperand RO> :
683 InstSE<(outs), (ins RO:$rs, RO:$rt, uimm16:$code_),
684 !strconcat(opstr, "\t$rs, $rt, $code_"), [], NoItinerary,
687 class TEQI_FT<string opstr, RegisterOperand RO> :
688 InstSE<(outs), (ins RO:$rs, uimm16:$imm16),
689 !strconcat(opstr, "\t$rs, $imm16"), [], NoItinerary, FrmOther, opstr>;
691 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
692 list<Register> DefRegs> :
693 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
695 let isCommutable = 1;
697 let neverHasSideEffects = 1;
700 // Pseudo multiply/divide instruction with explicit accumulator register
702 class MultDivPseudo<Instruction RealInst, RegisterClass R0, RegisterOperand R1,
703 SDPatternOperator OpNode, InstrItinClass Itin,
704 bit IsComm = 1, bit HasSideEffects = 0,
705 bit UsesCustomInserter = 0> :
706 PseudoSE<(outs R0:$ac), (ins R1:$rs, R1:$rt),
707 [(set R0:$ac, (OpNode R1:$rs, R1:$rt))], Itin>,
708 PseudoInstExpansion<(RealInst R1:$rs, R1:$rt)> {
709 let isCommutable = IsComm;
710 let hasSideEffects = HasSideEffects;
711 let usesCustomInserter = UsesCustomInserter;
714 // Pseudo multiply add/sub instruction with explicit accumulator register
716 class MAddSubPseudo<Instruction RealInst, SDPatternOperator OpNode,
718 : PseudoSE<(outs ACC64:$ac),
719 (ins GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin),
721 (OpNode GPR32Opnd:$rs, GPR32Opnd:$rt, ACC64:$acin))],
723 PseudoInstExpansion<(RealInst GPR32Opnd:$rs, GPR32Opnd:$rt)> {
724 string Constraints = "$acin = $ac";
727 class Div<string opstr, InstrItinClass itin, RegisterOperand RO,
728 list<Register> DefRegs> :
729 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$$zero, $rs, $rt"),
730 [], itin, FrmR, opstr> {
735 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
736 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
737 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
739 class MoveFromLOHI<string opstr, RegisterOperand RO, Register UseReg>:
740 InstSE<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), [], II_MFHI_MFLO,
743 let neverHasSideEffects = 1;
746 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
747 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
748 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
751 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
752 InstSE<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), [], II_MTHI_MTLO,
755 let neverHasSideEffects = 1;
758 class EffectiveAddress<string opstr, RegisterOperand RO> :
759 InstSE<(outs RO:$rt), (ins mem_ea:$addr), !strconcat(opstr, "\t$rt, $addr"),
760 [(set RO:$rt, addr:$addr)], NoItinerary, FrmI,
761 !strconcat(opstr, "_lea")> {
762 let isCodeGenOnly = 1;
763 let DecoderMethod = "DecodeMem";
766 // Count Leading Ones/Zeros in Word
767 class CountLeading0<string opstr, RegisterOperand RO>:
768 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
769 [(set RO:$rd, (ctlz RO:$rs))], II_CLZ, FrmR, opstr>,
770 Requires<[HasBitCount, HasStdEnc]>;
772 class CountLeading1<string opstr, RegisterOperand RO>:
773 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
774 [(set RO:$rd, (ctlz (not RO:$rs)))], II_CLO, FrmR, opstr>,
775 Requires<[HasBitCount, HasStdEnc]>;
777 // Sign Extend in Register.
778 class SignExtInReg<string opstr, ValueType vt, RegisterOperand RO,
779 InstrItinClass itin> :
780 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"),
781 [(set RO:$rd, (sext_inreg RO:$rt, vt))], itin, FrmR, opstr> {
782 let Predicates = [HasSEInReg, HasStdEnc];
786 class SubwordSwap<string opstr, RegisterOperand RO>:
787 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
788 NoItinerary, FrmR, opstr> {
789 let Predicates = [HasSwap, HasStdEnc];
790 let neverHasSideEffects = 1;
794 class ReadHardware<RegisterOperand CPURegOperand, RegisterOperand RO> :
795 InstSE<(outs CPURegOperand:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
799 class ExtBase<string opstr, RegisterOperand RO, Operand PosOpnd,
800 SDPatternOperator Op = null_frag>:
801 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ext:$size),
802 !strconcat(opstr, " $rt, $rs, $pos, $size"),
803 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size))], NoItinerary,
805 let Predicates = [HasMips32r2, HasStdEnc];
808 class InsBase<string opstr, RegisterOperand RO, Operand PosOpnd,
809 SDPatternOperator Op = null_frag>:
810 InstSE<(outs RO:$rt), (ins RO:$rs, PosOpnd:$pos, size_ins:$size, RO:$src),
811 !strconcat(opstr, " $rt, $rs, $pos, $size"),
812 [(set RO:$rt, (Op RO:$rs, imm:$pos, imm:$size, RO:$src))],
813 NoItinerary, FrmR, opstr> {
814 let Predicates = [HasMips32r2, HasStdEnc];
815 let Constraints = "$src = $rt";
818 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
819 class Atomic2Ops<PatFrag Op, RegisterClass DRC> :
820 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$incr),
821 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$incr))]>;
823 // Atomic Compare & Swap.
824 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC> :
825 PseudoSE<(outs DRC:$dst), (ins PtrRC:$ptr, DRC:$cmp, DRC:$swap),
826 [(set DRC:$dst, (Op iPTR:$ptr, DRC:$cmp, DRC:$swap))]>;
828 class LLBase<string opstr, RegisterOperand RO> :
829 InstSE<(outs RO:$rt), (ins mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
830 [], NoItinerary, FrmI> {
831 let DecoderMethod = "DecodeMem";
835 class SCBase<string opstr, RegisterOperand RO> :
836 InstSE<(outs RO:$dst), (ins RO:$rt, mem:$addr),
837 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
838 let DecoderMethod = "DecodeMem";
840 let Constraints = "$rt = $dst";
843 class MFC3OP<string asmstr, RegisterOperand RO> :
844 InstSE<(outs RO:$rt, RO:$rd, uimm16:$sel), (ins),
845 !strconcat(asmstr, "\t$rt, $rd, $sel"), [], NoItinerary, FrmFR>;
847 class TrapBase<Instruction RealInst>
848 : PseudoSE<(outs), (ins), [(trap)], NoItinerary>,
849 PseudoInstExpansion<(RealInst 0, 0)> {
851 let isTerminator = 1;
852 let isCodeGenOnly = 1;
855 //===----------------------------------------------------------------------===//
856 // Pseudo instructions
857 //===----------------------------------------------------------------------===//
860 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
861 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
863 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
864 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
865 [(callseq_start timm:$amt)]>;
866 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
867 [(callseq_end timm:$amt1, timm:$amt2)]>;
870 let usesCustomInserter = 1 in {
871 def ATOMIC_LOAD_ADD_I8 : Atomic2Ops<atomic_load_add_8, GPR32>;
872 def ATOMIC_LOAD_ADD_I16 : Atomic2Ops<atomic_load_add_16, GPR32>;
873 def ATOMIC_LOAD_ADD_I32 : Atomic2Ops<atomic_load_add_32, GPR32>;
874 def ATOMIC_LOAD_SUB_I8 : Atomic2Ops<atomic_load_sub_8, GPR32>;
875 def ATOMIC_LOAD_SUB_I16 : Atomic2Ops<atomic_load_sub_16, GPR32>;
876 def ATOMIC_LOAD_SUB_I32 : Atomic2Ops<atomic_load_sub_32, GPR32>;
877 def ATOMIC_LOAD_AND_I8 : Atomic2Ops<atomic_load_and_8, GPR32>;
878 def ATOMIC_LOAD_AND_I16 : Atomic2Ops<atomic_load_and_16, GPR32>;
879 def ATOMIC_LOAD_AND_I32 : Atomic2Ops<atomic_load_and_32, GPR32>;
880 def ATOMIC_LOAD_OR_I8 : Atomic2Ops<atomic_load_or_8, GPR32>;
881 def ATOMIC_LOAD_OR_I16 : Atomic2Ops<atomic_load_or_16, GPR32>;
882 def ATOMIC_LOAD_OR_I32 : Atomic2Ops<atomic_load_or_32, GPR32>;
883 def ATOMIC_LOAD_XOR_I8 : Atomic2Ops<atomic_load_xor_8, GPR32>;
884 def ATOMIC_LOAD_XOR_I16 : Atomic2Ops<atomic_load_xor_16, GPR32>;
885 def ATOMIC_LOAD_XOR_I32 : Atomic2Ops<atomic_load_xor_32, GPR32>;
886 def ATOMIC_LOAD_NAND_I8 : Atomic2Ops<atomic_load_nand_8, GPR32>;
887 def ATOMIC_LOAD_NAND_I16 : Atomic2Ops<atomic_load_nand_16, GPR32>;
888 def ATOMIC_LOAD_NAND_I32 : Atomic2Ops<atomic_load_nand_32, GPR32>;
890 def ATOMIC_SWAP_I8 : Atomic2Ops<atomic_swap_8, GPR32>;
891 def ATOMIC_SWAP_I16 : Atomic2Ops<atomic_swap_16, GPR32>;
892 def ATOMIC_SWAP_I32 : Atomic2Ops<atomic_swap_32, GPR32>;
894 def ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap<atomic_cmp_swap_8, GPR32>;
895 def ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap<atomic_cmp_swap_16, GPR32>;
896 def ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap<atomic_cmp_swap_32, GPR32>;
899 /// Pseudo instructions for loading and storing accumulator registers.
900 let isPseudo = 1, isCodeGenOnly = 1 in {
901 def LOAD_ACC64 : Load<"", ACC64>;
902 def STORE_ACC64 : Store<"", ACC64>;
905 //===----------------------------------------------------------------------===//
906 // Instruction definition
907 //===----------------------------------------------------------------------===//
908 //===----------------------------------------------------------------------===//
909 // MipsI Instructions
910 //===----------------------------------------------------------------------===//
912 /// Arithmetic Instructions (ALU Immediate)
913 def ADDiu : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd, II_ADDIU, immSExt16,
915 ADDI_FM<0x9>, IsAsCheapAsAMove;
916 def ADDi : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, ADDI_FM<0x8>;
917 def SLTi : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>,
919 def SLTiu : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>,
921 def ANDi : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd, II_ANDI, immZExt16,
924 def ORi : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd, II_ORI, immZExt16,
927 def XORi : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd, II_XORI, immZExt16,
930 def LUi : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM;
932 /// Arithmetic Instructions (3-Operand, R-Type)
933 def ADDu : MMRel, ArithLogicR<"addu", GPR32Opnd, 1, II_ADDU, add>,
935 def SUBu : MMRel, ArithLogicR<"subu", GPR32Opnd, 0, II_SUBU, sub>,
937 let Defs = [HI0, LO0] in
938 def MUL : MMRel, ArithLogicR<"mul", GPR32Opnd, 1, II_MUL, mul>,
940 def ADD : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM<0, 0x20>;
941 def SUB : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM<0, 0x22>;
942 def SLT : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM<0, 0x2a>;
943 def SLTu : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, ADD_FM<0, 0x2b>;
944 def AND : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>,
946 def OR : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>,
948 def XOR : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>,
950 def NOR : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM<0, 0x27>;
952 /// Shift Instructions
953 def SLL : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL, shl,
954 immZExt5>, SRA_FM<0, 0>;
955 def SRL : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL, srl,
956 immZExt5>, SRA_FM<2, 0>;
957 def SRA : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA, sra,
958 immZExt5>, SRA_FM<3, 0>;
959 def SLLV : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV, shl>,
961 def SRLV : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV, srl>,
963 def SRAV : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV, sra>,
966 // Rotate Instructions
967 let Predicates = [HasMips32r2, HasStdEnc] in {
968 def ROTR : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR, rotr,
969 immZExt5>, SRA_FM<2, 1>;
970 def ROTRV : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV, rotr>,
974 /// Load and Store Instructions
976 def LB : Load<"lb", GPR32Opnd, sextloadi8, II_LB>, MMRel, LW_FM<0x20>;
977 def LBu : Load<"lbu", GPR32Opnd, zextloadi8, II_LBU, addrDefault>, MMRel,
979 def LH : Load<"lh", GPR32Opnd, sextloadi16, II_LH, addrDefault>, MMRel,
981 def LHu : Load<"lhu", GPR32Opnd, zextloadi16, II_LHU>, MMRel, LW_FM<0x25>;
982 def LW : Load<"lw", GPR32Opnd, load, II_LW, addrDefault>, MMRel,
984 def SB : Store<"sb", GPR32Opnd, truncstorei8, II_SB>, MMRel, LW_FM<0x28>;
985 def SH : Store<"sh", GPR32Opnd, truncstorei16, II_SH>, MMRel, LW_FM<0x29>;
986 def SW : Store<"sw", GPR32Opnd, store, II_SW>, MMRel, LW_FM<0x2b>;
988 /// load/store left/right
989 let Predicates = [NotInMicroMips] in {
990 def LWL : LoadLeftRight<"lwl", MipsLWL, GPR32Opnd, II_LWL>, LW_FM<0x22>;
991 def LWR : LoadLeftRight<"lwr", MipsLWR, GPR32Opnd, II_LWR>, LW_FM<0x26>;
992 def SWL : StoreLeftRight<"swl", MipsSWL, GPR32Opnd, II_SWL>, LW_FM<0x2a>;
993 def SWR : StoreLeftRight<"swr", MipsSWR, GPR32Opnd, II_SWR>, LW_FM<0x2e>;
996 def SYNC : MMRel, SYNC_FT<"sync">, SYNC_FM;
997 def TEQ : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM<0x34>;
998 def TGE : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM<0x30>;
999 def TGEU : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM<0x31>;
1000 def TLT : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM<0x32>;
1001 def TLTU : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM<0x33>;
1002 def TNE : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM<0x36>;
1004 def TEQI : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM<0xc>;
1005 def TGEI : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM<0x8>;
1006 def TGEIU : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM<0x9>;
1007 def TLTI : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM<0xa>;
1008 def TTLTIU : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM<0xb>;
1009 def TNEI : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM<0xe>;
1011 def BREAK : MMRel, BRK_FT<"break">, BRK_FM<0xd>;
1012 def SYSCALL : MMRel, SYS_FT<"syscall">, SYS_FM<0xc>;
1013 def TRAP : TrapBase<BREAK>;
1015 def ERET : MMRel, ER_FT<"eret">, ER_FM<0x18>;
1016 def DERET : MMRel, ER_FT<"deret">, ER_FM<0x1f>;
1018 def EI : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM<1>;
1019 def DI : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM<0>;
1021 let Predicates = [NotInMicroMips] in {
1022 def WAIT : WAIT_FT<"wait">, WAIT_FM;
1024 /// Load-linked, Store-conditional
1025 def LL : LLBase<"ll", GPR32Opnd>, LW_FM<0x30>;
1026 def SC : SCBase<"sc", GPR32Opnd>, LW_FM<0x38>;
1029 /// Jump and Branch Instructions
1030 def J : MMRel, JumpFJ<jmptarget, "j", br, bb, "j">, FJ<2>,
1031 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
1032 def JR : MMRel, IndirectBranch<"jr", GPR32Opnd>, MTLO_FM<8>;
1033 def BEQ : MMRel, CBranch<"beq", brtarget, seteq, GPR32Opnd>, BEQ_FM<4>;
1034 def BNE : MMRel, CBranch<"bne", brtarget, setne, GPR32Opnd>, BEQ_FM<5>;
1035 def BGEZ : MMRel, CBranchZero<"bgez", brtarget, setge, GPR32Opnd>,
1037 def BGTZ : MMRel, CBranchZero<"bgtz", brtarget, setgt, GPR32Opnd>,
1039 def BLEZ : MMRel, CBranchZero<"blez", brtarget, setle, GPR32Opnd>,
1041 def BLTZ : MMRel, CBranchZero<"bltz", brtarget, setlt, GPR32Opnd>,
1043 def B : UncondBranch<BEQ>;
1045 def JAL : MMRel, JumpLink<"jal", calltarget>, FJ<3>;
1046 let Predicates = [NotInMicroMips] in {
1047 def JALR : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM;
1049 def JALX : JumpLink<"jalx", calltarget>, FJ<0x1D>;
1050 def JALRPseudo : JumpLinkRegPseudo<GPR32Opnd, JALR, RA>;
1051 def BGEZAL : MMRel, BGEZAL_FT<"bgezal", brtarget, GPR32Opnd>, BGEZAL_FM<0x11>;
1052 def BLTZAL : MMRel, BGEZAL_FT<"bltzal", brtarget, GPR32Opnd>, BGEZAL_FM<0x10>;
1053 def BAL_BR : BAL_BR_Pseudo<BGEZAL>;
1054 def TAILCALL : TailCall<J>;
1055 def TAILCALL_R : TailCallReg<GPR32Opnd, JR>;
1057 def RET : MMRel, RetBase<"ret", GPR32Opnd>, MTLO_FM<8>;
1059 // Exception handling related node and instructions.
1060 // The conversion sequence is:
1061 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
1062 // MIPSeh_return -> (stack change + indirect branch)
1064 // MIPSeh_return takes the place of regular return instruction
1065 // but takes two arguments (V1, V0) which are used for storing
1066 // the offset and return address respectively.
1067 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
1069 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
1070 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
1072 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
1073 def MIPSeh_return32 : MipsPseudo<(outs), (ins GPR32:$spoff, GPR32:$dst),
1074 [(MIPSehret GPR32:$spoff, GPR32:$dst)]>;
1075 def MIPSeh_return64 : MipsPseudo<(outs), (ins GPR64:$spoff,
1077 [(MIPSehret GPR64:$spoff, GPR64:$dst)]>;
1080 /// Multiply and Divide Instructions.
1081 def MULT : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>,
1083 def MULTu : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>,
1085 def SDIV : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>,
1087 def UDIV : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>,
1090 def MTHI : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, MTLO_FM<0x11>;
1091 def MTLO : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, MTLO_FM<0x13>;
1092 def MFHI : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, MFLO_FM<0x10>;
1093 def MFLO : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, MFLO_FM<0x12>;
1095 /// Sign Ext In Register Instructions.
1096 def SEB : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, SEB_FM<0x10, 0x20>;
1097 def SEH : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, SEB_FM<0x18, 0x20>;
1100 def CLZ : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM<0x20>;
1101 def CLO : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM<0x21>;
1103 /// Word Swap Bytes Within Halfwords
1104 def WSBH : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM<2, 0x20>;
1107 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
1109 // FrameIndexes are legalized when they are operands from load/store
1110 // instructions. The same not happens for stack address copies, so an
1111 // add op with mem ComplexPattern is used and the stack address copy
1112 // can be matched. It's similar to Sparc LEA_ADDRi
1113 def LEA_ADDiu : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, LW_FM<9>;
1116 def MADD : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM<0x1c, 0>;
1117 def MADDU : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM<0x1c, 1>;
1118 def MSUB : MMRel, MArithR<"msub", II_MSUB>, MULT_FM<0x1c, 4>;
1119 def MSUBU : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM<0x1c, 5>;
1121 let Predicates = [HasStdEnc, NotDSP] in {
1122 def PseudoMULT : MultDivPseudo<MULT, ACC64, GPR32Opnd, MipsMult, II_MULT>;
1123 def PseudoMULTu : MultDivPseudo<MULTu, ACC64, GPR32Opnd, MipsMultu, II_MULTU>;
1124 def PseudoMFHI : PseudoMFLOHI<GPR32, ACC64, MipsMFHI>;
1125 def PseudoMFLO : PseudoMFLOHI<GPR32, ACC64, MipsMFLO>;
1126 def PseudoMTLOHI : PseudoMTLOHI<ACC64, GPR32>;
1127 def PseudoMADD : MAddSubPseudo<MADD, MipsMAdd, II_MADD>;
1128 def PseudoMADDU : MAddSubPseudo<MADDU, MipsMAddu, II_MADDU>;
1129 def PseudoMSUB : MAddSubPseudo<MSUB, MipsMSub, II_MSUB>;
1130 def PseudoMSUBU : MAddSubPseudo<MSUBU, MipsMSubu, II_MSUBU>;
1133 def PseudoSDIV : MultDivPseudo<SDIV, ACC64, GPR32Opnd, MipsDivRem, II_DIV,
1135 def PseudoUDIV : MultDivPseudo<UDIV, ACC64, GPR32Opnd, MipsDivRemU, II_DIVU,
1138 def RDHWR : ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM;
1140 def EXT : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, EXT_FM<0>;
1141 def INS : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, EXT_FM<4>;
1143 /// Move Control Registers From/To CPU Registers
1144 def MFC0 : MFC3OP<"mfc0", GPR32Opnd>, MFC3OP_FM<0x10, 0>;
1145 def MTC0 : MFC3OP<"mtc0", GPR32Opnd>, MFC3OP_FM<0x10, 4>;
1146 def MFC2 : MFC3OP<"mfc2", GPR32Opnd>, MFC3OP_FM<0x12, 0>;
1147 def MTC2 : MFC3OP<"mtc2", GPR32Opnd>, MFC3OP_FM<0x12, 4>;
1149 //===----------------------------------------------------------------------===//
1150 // Instruction aliases
1151 //===----------------------------------------------------------------------===//
1152 def : InstAlias<"move $dst, $src",
1153 (ADDu GPR32Opnd:$dst, GPR32Opnd:$src,ZERO), 1>,
1154 Requires<[NotMips64, NotInMicroMips]>;
1155 def : InstAlias<"bal $offset", (BGEZAL ZERO, brtarget:$offset), 0>;
1156 def : InstAlias<"addu $rs, $rt, $imm",
1157 (ADDiu GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1158 def : InstAlias<"add $rs, $rt, $imm",
1159 (ADDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1160 def : InstAlias<"and $rs, $rt, $imm",
1161 (ANDi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1162 def : InstAlias<"j $rs", (JR GPR32Opnd:$rs), 0>;
1163 let Predicates = [NotInMicroMips] in {
1164 def : InstAlias<"jalr $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1166 def : InstAlias<"jal $rs", (JALR RA, GPR32Opnd:$rs), 0>;
1167 def : InstAlias<"jal $rd,$rs", (JALR GPR32Opnd:$rd, GPR32Opnd:$rs), 0>;
1168 def : InstAlias<"not $rt, $rs",
1169 (NOR GPR32Opnd:$rt, GPR32Opnd:$rs, ZERO), 0>;
1170 def : InstAlias<"neg $rt, $rs",
1171 (SUB GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1172 def : InstAlias<"negu $rt, $rs",
1173 (SUBu GPR32Opnd:$rt, ZERO, GPR32Opnd:$rs), 1>;
1174 def : InstAlias<"slt $rs, $rt, $imm",
1175 (SLTi GPR32Opnd:$rs, GPR32Opnd:$rt, simm16:$imm), 0>;
1176 def : InstAlias<"xor $rs, $rt, $imm",
1177 (XORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1178 def : InstAlias<"or $rs, $rt, $imm",
1179 (ORi GPR32Opnd:$rs, GPR32Opnd:$rt, uimm16:$imm), 0>;
1180 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1181 def : InstAlias<"mfc0 $rt, $rd", (MFC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1182 def : InstAlias<"mtc0 $rt, $rd", (MTC0 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1183 def : InstAlias<"mfc2 $rt, $rd", (MFC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1184 def : InstAlias<"mtc2 $rt, $rd", (MTC2 GPR32Opnd:$rt, GPR32Opnd:$rd, 0), 0>;
1185 def : InstAlias<"b $offset", (BEQ ZERO, ZERO, brtarget:$offset), 0>;
1186 def : InstAlias<"bnez $rs,$offset",
1187 (BNE GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1188 def : InstAlias<"beqz $rs,$offset",
1189 (BEQ GPR32Opnd:$rs, ZERO, brtarget:$offset), 0>;
1190 def : InstAlias<"syscall", (SYSCALL 0), 1>;
1192 def : InstAlias<"break $imm", (BREAK uimm10:$imm, 0), 1>;
1193 def : InstAlias<"break", (BREAK 0, 0), 1>;
1194 def : InstAlias<"ei", (EI ZERO), 1>;
1195 def : InstAlias<"di", (DI ZERO), 1>;
1197 def : InstAlias<"teq $rs, $rt", (TEQ GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1198 def : InstAlias<"tge $rs, $rt", (TGE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1199 def : InstAlias<"tgeu $rs, $rt", (TGEU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1200 def : InstAlias<"tlt $rs, $rt", (TLT GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1201 def : InstAlias<"tltu $rs, $rt", (TLTU GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1202 def : InstAlias<"tne $rs, $rt", (TNE GPR32Opnd:$rs, GPR32Opnd:$rt, 0), 1>;
1203 def : InstAlias<"sub, $rd, $rs, $imm",
1204 (ADDi GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1205 def : InstAlias<"subu, $rd, $rs, $imm",
1206 (ADDiu GPR32Opnd:$rd, GPR32Opnd:$rs, InvertedImOperand:$imm)>;
1208 //===----------------------------------------------------------------------===//
1209 // Assembler Pseudo Instructions
1210 //===----------------------------------------------------------------------===//
1212 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1213 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1214 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1215 def LoadImm32Reg : LoadImm32<"li", uimm5, GPR32Opnd>;
1217 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1218 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1219 !strconcat(instr_asm, "\t$rt, $addr")> ;
1220 def LoadAddr32Reg : LoadAddress<"la", mem, GPR32Opnd>;
1222 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1223 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1224 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1225 def LoadAddr32Imm : LoadAddressImm<"la", uimm5, GPR32Opnd>;
1227 //===----------------------------------------------------------------------===//
1228 // Arbitrary patterns that map to one or more instructions
1229 //===----------------------------------------------------------------------===//
1231 // Load/store pattern templates.
1232 class LoadRegImmPat<Instruction LoadInst, ValueType ValTy, PatFrag Node> :
1233 MipsPat<(ValTy (Node addrRegImm:$a)), (LoadInst addrRegImm:$a)>;
1235 class StoreRegImmPat<Instruction StoreInst, ValueType ValTy> :
1236 MipsPat<(store ValTy:$v, addrRegImm:$a), (StoreInst ValTy:$v, addrRegImm:$a)>;
1239 def : MipsPat<(i32 immSExt16:$in),
1240 (ADDiu ZERO, imm:$in)>;
1241 def : MipsPat<(i32 immZExt16:$in),
1242 (ORi ZERO, imm:$in)>;
1243 def : MipsPat<(i32 immLow16Zero:$in),
1244 (LUi (HI16 imm:$in))>;
1246 // Arbitrary immediates
1247 def : MipsPat<(i32 imm:$imm),
1248 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1250 // Carry MipsPatterns
1251 def : MipsPat<(subc GPR32:$lhs, GPR32:$rhs),
1252 (SUBu GPR32:$lhs, GPR32:$rhs)>;
1253 let Predicates = [HasStdEnc, NotDSP] in {
1254 def : MipsPat<(addc GPR32:$lhs, GPR32:$rhs),
1255 (ADDu GPR32:$lhs, GPR32:$rhs)>;
1256 def : MipsPat<(addc GPR32:$src, immSExt16:$imm),
1257 (ADDiu GPR32:$src, imm:$imm)>;
1261 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1262 (JAL tglobaladdr:$dst)>;
1263 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1264 (JAL texternalsym:$dst)>;
1265 //def : MipsPat<(MipsJmpLink GPR32:$dst),
1266 // (JALR GPR32:$dst)>;
1269 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1270 (TAILCALL tglobaladdr:$dst)>;
1271 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1272 (TAILCALL texternalsym:$dst)>;
1274 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1275 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1276 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1277 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1278 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1279 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1281 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1282 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1283 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1284 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1285 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1286 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1288 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaladdr:$lo)),
1289 (ADDiu GPR32:$hi, tglobaladdr:$lo)>;
1290 def : MipsPat<(add GPR32:$hi, (MipsLo tblockaddress:$lo)),
1291 (ADDiu GPR32:$hi, tblockaddress:$lo)>;
1292 def : MipsPat<(add GPR32:$hi, (MipsLo tjumptable:$lo)),
1293 (ADDiu GPR32:$hi, tjumptable:$lo)>;
1294 def : MipsPat<(add GPR32:$hi, (MipsLo tconstpool:$lo)),
1295 (ADDiu GPR32:$hi, tconstpool:$lo)>;
1296 def : MipsPat<(add GPR32:$hi, (MipsLo tglobaltlsaddr:$lo)),
1297 (ADDiu GPR32:$hi, tglobaltlsaddr:$lo)>;
1300 def : MipsPat<(add GPR32:$gp, (MipsGPRel tglobaladdr:$in)),
1301 (ADDiu GPR32:$gp, tglobaladdr:$in)>;
1302 def : MipsPat<(add GPR32:$gp, (MipsGPRel tconstpool:$in)),
1303 (ADDiu GPR32:$gp, tconstpool:$in)>;
1306 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1307 MipsPat<(MipsWrapper RC:$gp, node:$in),
1308 (ADDiuOp RC:$gp, node:$in)>;
1310 def : WrapperPat<tglobaladdr, ADDiu, GPR32>;
1311 def : WrapperPat<tconstpool, ADDiu, GPR32>;
1312 def : WrapperPat<texternalsym, ADDiu, GPR32>;
1313 def : WrapperPat<tblockaddress, ADDiu, GPR32>;
1314 def : WrapperPat<tjumptable, ADDiu, GPR32>;
1315 def : WrapperPat<tglobaltlsaddr, ADDiu, GPR32>;
1317 // Mips does not have "not", so we expand our way
1318 def : MipsPat<(not GPR32:$in),
1319 (NOR GPR32Opnd:$in, ZERO)>;
1322 let Predicates = [HasStdEnc] in {
1323 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1324 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1325 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1329 let Predicates = [HasStdEnc] in
1330 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1333 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1334 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1335 Instruction SLTiuOp, Register ZEROReg> {
1336 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1337 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1338 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1339 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1341 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1342 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1343 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1344 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1345 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1346 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1347 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1348 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1349 def : MipsPat<(brcond (i32 (setgt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1350 (BEQ (SLTiOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1351 def : MipsPat<(brcond (i32 (setugt RC:$lhs, immSExt16Plus1:$rhs)), bb:$dst),
1352 (BEQ (SLTiuOp RC:$lhs, (Plus1 imm:$rhs)), ZERO, bb:$dst)>;
1354 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1355 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1356 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1357 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1359 def : MipsPat<(brcond RC:$cond, bb:$dst),
1360 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1363 defm : BrcondPats<GPR32, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1365 def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
1366 (BLEZ i32:$lhs, bb:$dst)>;
1367 def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
1368 (BGEZ i32:$lhs, bb:$dst)>;
1371 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1372 Instruction SLTuOp, Register ZEROReg> {
1373 def : MipsPat<(seteq RC:$lhs, 0),
1374 (SLTiuOp RC:$lhs, 1)>;
1375 def : MipsPat<(setne RC:$lhs, 0),
1376 (SLTuOp ZEROReg, RC:$lhs)>;
1377 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1378 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1379 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1380 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1383 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1384 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1385 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1386 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1387 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1390 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1391 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1392 (SLTOp RC:$rhs, RC:$lhs)>;
1393 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1394 (SLTuOp RC:$rhs, RC:$lhs)>;
1397 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1398 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1399 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1400 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1401 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1404 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1405 Instruction SLTiuOp> {
1406 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1407 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1408 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1409 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1412 defm : SeteqPats<GPR32, SLTiu, XOR, SLTu, ZERO>;
1413 defm : SetlePats<GPR32, SLT, SLTu>;
1414 defm : SetgtPats<GPR32, SLT, SLTu>;
1415 defm : SetgePats<GPR32, SLT, SLTu>;
1416 defm : SetgeImmPats<GPR32, SLTi, SLTiu>;
1419 def : MipsPat<(bswap GPR32:$rt), (ROTR (WSBH GPR32:$rt), 16)>;
1421 // Load halfword/word patterns.
1422 let AddedComplexity = 40 in {
1423 let Predicates = [HasStdEnc] in {
1424 def : LoadRegImmPat<LBu, i32, zextloadi8>;
1425 def : LoadRegImmPat<LH, i32, sextloadi16>;
1426 def : LoadRegImmPat<LW, i32, load>;
1430 //===----------------------------------------------------------------------===//
1431 // Floating Point Support
1432 //===----------------------------------------------------------------------===//
1434 include "MipsInstrFPU.td"
1435 include "Mips64InstrInfo.td"
1436 include "MipsCondMov.td"
1441 include "Mips16InstrFormats.td"
1442 include "Mips16InstrInfo.td"
1445 include "MipsDSPInstrFormats.td"
1446 include "MipsDSPInstrInfo.td"
1449 include "MipsMSAInstrFormats.td"
1450 include "MipsMSAInstrInfo.td"
1453 include "MicroMipsInstrFormats.td"
1454 include "MicroMipsInstrInfo.td"
1455 include "MicroMipsInstrFPU.td"