1 //===- MipsInstrInfo.td - Target Description for Mips Target -*- tablegen -*-=//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Mips implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 //===----------------------------------------------------------------------===//
16 // Mips profiles and nodes
17 //===----------------------------------------------------------------------===//
19 def SDT_MipsJmpLink : SDTypeProfile<0, 1, [SDTCisVT<0, iPTR>]>;
20 def SDT_MipsCMov : SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>,
24 def SDT_MipsCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>]>;
25 def SDT_MipsCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>;
26 def SDT_MipsMAddMSub : SDTypeProfile<0, 4,
27 [SDTCisVT<0, i32>, SDTCisSameAs<0, 1>,
30 def SDT_MipsDivRem : SDTypeProfile<0, 2,
34 def SDT_MipsThreadPointer : SDTypeProfile<1, 0, [SDTCisPtrTy<0>]>;
36 def SDT_Sync : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
38 def SDT_Ext : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
39 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>]>;
40 def SDT_Ins : SDTypeProfile<1, 4, [SDTCisInt<0>, SDTCisSameAs<0, 1>,
41 SDTCisVT<2, i32>, SDTCisSameAs<2, 3>,
44 def SDTMipsLoadLR : SDTypeProfile<1, 2,
45 [SDTCisInt<0>, SDTCisPtrTy<1>,
49 def MipsJmpLink : SDNode<"MipsISD::JmpLink",SDT_MipsJmpLink,
50 [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue,
54 def MipsTailCall : SDNode<"MipsISD::TailCall", SDT_MipsJmpLink,
55 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
57 // Hi and Lo nodes are used to handle global addresses. Used on
58 // MipsISelLowering to lower stuff like GlobalAddress, ExternalSymbol
59 // static model. (nothing to do with Mips Registers Hi and Lo)
60 def MipsHi : SDNode<"MipsISD::Hi", SDTIntUnaryOp>;
61 def MipsLo : SDNode<"MipsISD::Lo", SDTIntUnaryOp>;
62 def MipsGPRel : SDNode<"MipsISD::GPRel", SDTIntUnaryOp>;
64 // TlsGd node is used to handle General Dynamic TLS
65 def MipsTlsGd : SDNode<"MipsISD::TlsGd", SDTIntUnaryOp>;
67 // TprelHi and TprelLo nodes are used to handle Local Exec TLS
68 def MipsTprelHi : SDNode<"MipsISD::TprelHi", SDTIntUnaryOp>;
69 def MipsTprelLo : SDNode<"MipsISD::TprelLo", SDTIntUnaryOp>;
72 def MipsThreadPointer: SDNode<"MipsISD::ThreadPointer", SDT_MipsThreadPointer>;
75 def MipsRet : SDNode<"MipsISD::Ret", SDTNone,
76 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
78 // These are target-independent nodes, but have target-specific formats.
79 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_MipsCallSeqStart,
80 [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>;
81 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_MipsCallSeqEnd,
82 [SDNPHasChain, SDNPSideEffect,
83 SDNPOptInGlue, SDNPOutGlue]>;
86 def MipsMAdd : SDNode<"MipsISD::MAdd", SDT_MipsMAddMSub,
87 [SDNPOptInGlue, SDNPOutGlue]>;
88 def MipsMAddu : SDNode<"MipsISD::MAddu", SDT_MipsMAddMSub,
89 [SDNPOptInGlue, SDNPOutGlue]>;
90 def MipsMSub : SDNode<"MipsISD::MSub", SDT_MipsMAddMSub,
91 [SDNPOptInGlue, SDNPOutGlue]>;
92 def MipsMSubu : SDNode<"MipsISD::MSubu", SDT_MipsMAddMSub,
93 [SDNPOptInGlue, SDNPOutGlue]>;
96 def MipsDivRem : SDNode<"MipsISD::DivRem", SDT_MipsDivRem,
98 def MipsDivRemU : SDNode<"MipsISD::DivRemU", SDT_MipsDivRem,
101 // Target constant nodes that are not part of any isel patterns and remain
102 // unchanged can cause instructions with illegal operands to be emitted.
103 // Wrapper node patterns give the instruction selector a chance to replace
104 // target constant nodes that would otherwise remain unchanged with ADDiu
105 // nodes. Without these wrapper node patterns, the following conditional move
106 // instrucion is emitted when function cmov2 in test/CodeGen/Mips/cmov.ll is
108 // movn %got(d)($gp), %got(c)($gp), $4
109 // This instruction is illegal since movn can take only register operands.
111 def MipsWrapper : SDNode<"MipsISD::Wrapper", SDTIntBinOp>;
113 def MipsSync : SDNode<"MipsISD::Sync", SDT_Sync, [SDNPHasChain,SDNPSideEffect]>;
115 def MipsExt : SDNode<"MipsISD::Ext", SDT_Ext>;
116 def MipsIns : SDNode<"MipsISD::Ins", SDT_Ins>;
118 def MipsLWL : SDNode<"MipsISD::LWL", SDTMipsLoadLR,
119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
120 def MipsLWR : SDNode<"MipsISD::LWR", SDTMipsLoadLR,
121 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
122 def MipsSWL : SDNode<"MipsISD::SWL", SDTStore,
123 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
124 def MipsSWR : SDNode<"MipsISD::SWR", SDTStore,
125 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
126 def MipsLDL : SDNode<"MipsISD::LDL", SDTMipsLoadLR,
127 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
128 def MipsLDR : SDNode<"MipsISD::LDR", SDTMipsLoadLR,
129 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand]>;
130 def MipsSDL : SDNode<"MipsISD::SDL", SDTStore,
131 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
132 def MipsSDR : SDNode<"MipsISD::SDR", SDTStore,
133 [SDNPHasChain, SDNPMayStore, SDNPMemOperand]>;
135 //===----------------------------------------------------------------------===//
136 // Mips Instruction Predicate Definitions.
137 //===----------------------------------------------------------------------===//
138 def HasSEInReg : Predicate<"Subtarget.hasSEInReg()">,
139 AssemblerPredicate<"FeatureSEInReg">;
140 def HasBitCount : Predicate<"Subtarget.hasBitCount()">,
141 AssemblerPredicate<"FeatureBitCount">;
142 def HasSwap : Predicate<"Subtarget.hasSwap()">,
143 AssemblerPredicate<"FeatureSwap">;
144 def HasCondMov : Predicate<"Subtarget.hasCondMov()">,
145 AssemblerPredicate<"FeatureCondMov">;
146 def HasFPIdx : Predicate<"Subtarget.hasFPIdx()">,
147 AssemblerPredicate<"FeatureFPIdx">;
148 def HasMips32 : Predicate<"Subtarget.hasMips32()">,
149 AssemblerPredicate<"FeatureMips32">;
150 def HasMips32r2 : Predicate<"Subtarget.hasMips32r2()">,
151 AssemblerPredicate<"FeatureMips32r2">;
152 def HasMips64 : Predicate<"Subtarget.hasMips64()">,
153 AssemblerPredicate<"FeatureMips64">;
154 def NotMips64 : Predicate<"!Subtarget.hasMips64()">,
155 AssemblerPredicate<"!FeatureMips64">;
156 def HasMips64r2 : Predicate<"Subtarget.hasMips64r2()">,
157 AssemblerPredicate<"FeatureMips64r2">;
158 def IsN64 : Predicate<"Subtarget.isABI_N64()">,
159 AssemblerPredicate<"FeatureN64">;
160 def NotN64 : Predicate<"!Subtarget.isABI_N64()">,
161 AssemblerPredicate<"!FeatureN64">;
162 def InMips16Mode : Predicate<"Subtarget.inMips16Mode()">,
163 AssemblerPredicate<"FeatureMips16">;
164 def RelocStatic : Predicate<"TM.getRelocationModel() == Reloc::Static">,
165 AssemblerPredicate<"FeatureMips32">;
166 def RelocPIC : Predicate<"TM.getRelocationModel() == Reloc::PIC_">,
167 AssemblerPredicate<"FeatureMips32">;
168 def NoNaNsFPMath : Predicate<"TM.Options.NoNaNsFPMath">,
169 AssemblerPredicate<"FeatureMips32">;
170 def HasStdEnc : Predicate<"Subtarget.hasStandardEncoding()">,
171 AssemblerPredicate<"!FeatureMips16">;
173 class MipsPat<dag pattern, dag result> : Pat<pattern, result> {
174 let Predicates = [HasStdEnc];
178 bit isCommutable = 1;
195 bit isTerminator = 1;
198 bit hasExtraSrcRegAllocReq = 1;
199 bit isCodeGenOnly = 1;
202 class IsAsCheapAsAMove {
203 bit isAsCheapAsAMove = 1;
206 class NeverHasSideEffects {
207 bit neverHasSideEffects = 1;
210 //===----------------------------------------------------------------------===//
211 // Instruction format superclass
212 //===----------------------------------------------------------------------===//
214 include "MipsInstrFormats.td"
216 //===----------------------------------------------------------------------===//
217 // Mips Operand, Complex Patterns and Transformations Definitions.
218 //===----------------------------------------------------------------------===//
220 // Instruction operand types
221 def jmptarget : Operand<OtherVT> {
222 let EncoderMethod = "getJumpTargetOpValue";
224 def brtarget : Operand<OtherVT> {
225 let EncoderMethod = "getBranchTargetOpValue";
226 let OperandType = "OPERAND_PCREL";
227 let DecoderMethod = "DecodeBranchTarget";
229 def calltarget : Operand<iPTR> {
230 let EncoderMethod = "getJumpTargetOpValue";
232 def calltarget64: Operand<i64>;
233 def simm16 : Operand<i32> {
234 let DecoderMethod= "DecodeSimm16";
237 def simm20 : Operand<i32> {
240 def simm16_64 : Operand<i64>;
241 def shamt : Operand<i32>;
244 def uimm16 : Operand<i32> {
245 let PrintMethod = "printUnsignedImm";
248 def MipsMemAsmOperand : AsmOperandClass {
250 let ParserMethod = "parseMemOperand";
254 def mem : Operand<i32> {
255 let PrintMethod = "printMemOperand";
256 let MIOperandInfo = (ops CPURegs, simm16);
257 let EncoderMethod = "getMemEncoding";
258 let ParserMatchClass = MipsMemAsmOperand;
261 def mem64 : Operand<i64> {
262 let PrintMethod = "printMemOperand";
263 let MIOperandInfo = (ops CPU64Regs, simm16_64);
264 let EncoderMethod = "getMemEncoding";
265 let ParserMatchClass = MipsMemAsmOperand;
268 def mem_ea : Operand<i32> {
269 let PrintMethod = "printMemOperandEA";
270 let MIOperandInfo = (ops CPURegs, simm16);
271 let EncoderMethod = "getMemEncoding";
274 def mem_ea_64 : Operand<i64> {
275 let PrintMethod = "printMemOperandEA";
276 let MIOperandInfo = (ops CPU64Regs, simm16_64);
277 let EncoderMethod = "getMemEncoding";
280 // size operand of ext instruction
281 def size_ext : Operand<i32> {
282 let EncoderMethod = "getSizeExtEncoding";
283 let DecoderMethod = "DecodeExtSize";
286 // size operand of ins instruction
287 def size_ins : Operand<i32> {
288 let EncoderMethod = "getSizeInsEncoding";
289 let DecoderMethod = "DecodeInsSize";
292 // Transformation Function - get the lower 16 bits.
293 def LO16 : SDNodeXForm<imm, [{
294 return getImm(N, N->getZExtValue() & 0xFFFF);
297 // Transformation Function - get the higher 16 bits.
298 def HI16 : SDNodeXForm<imm, [{
299 return getImm(N, (N->getZExtValue() >> 16) & 0xFFFF);
303 def Plus1 : SDNodeXForm<imm, [{ return getImm(N, N->getSExtValue() + 1); }]>;
305 // Node immediate fits as 16-bit sign extended on target immediate.
307 def immSExt8 : PatLeaf<(imm), [{ return isInt<8>(N->getSExtValue()); }]>;
309 // Node immediate fits as 16-bit sign extended on target immediate.
311 def immSExt16 : PatLeaf<(imm), [{ return isInt<16>(N->getSExtValue()); }]>;
313 // Node immediate fits as 15-bit sign extended on target immediate.
315 def immSExt15 : PatLeaf<(imm), [{ return isInt<15>(N->getSExtValue()); }]>;
317 // Node immediate fits as 16-bit zero extended on target immediate.
318 // The LO16 param means that only the lower 16 bits of the node
319 // immediate are caught.
321 def immZExt16 : PatLeaf<(imm), [{
322 if (N->getValueType(0) == MVT::i32)
323 return (uint32_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
325 return (uint64_t)N->getZExtValue() == (unsigned short)N->getZExtValue();
328 // Immediate can be loaded with LUi (32-bit int with lower 16-bit cleared).
329 def immLow16Zero : PatLeaf<(imm), [{
330 int64_t Val = N->getSExtValue();
331 return isInt<32>(Val) && !(Val & 0xffff);
334 // shamt field must fit in 5 bits.
335 def immZExt5 : ImmLeaf<i32, [{return Imm == (Imm & 0x1f);}]>;
337 // True if (N + 1) fits in 16-bit field.
338 def immSExt16Plus1 : PatLeaf<(imm), [{
339 return isInt<17>(N->getSExtValue()) && isInt<16>(N->getSExtValue() + 1);
342 // Mips Address Mode! SDNode frameindex could possibily be a match
343 // since load and store instructions from stack used it.
345 ComplexPattern<iPTR, 2, "selectIntAddr", [frameindex]>;
348 ComplexPattern<iPTR, 2, "selectAddrRegImm", [frameindex]>;
351 ComplexPattern<iPTR, 2, "selectAddrDefault", [frameindex]>;
353 //===----------------------------------------------------------------------===//
354 // Instructions specific format
355 //===----------------------------------------------------------------------===//
357 // Arithmetic and logical instructions with 3 register operands.
358 class ArithLogicR<string opstr, RegisterOperand RO, bit isComm = 0,
359 InstrItinClass Itin = NoItinerary,
360 SDPatternOperator OpNode = null_frag>:
361 InstSE<(outs RO:$rd), (ins RO:$rs, RO:$rt),
362 !strconcat(opstr, "\t$rd, $rs, $rt"),
363 [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> {
364 let isCommutable = isComm;
365 let isReMaterializable = 1;
370 // Arithmetic and logical instructions with 2 register operands.
371 class ArithLogicI<string opstr, Operand Od, RegisterOperand RO,
372 SDPatternOperator imm_type = null_frag,
373 SDPatternOperator OpNode = null_frag> :
374 InstSE<(outs RO:$rt), (ins RO:$rs, Od:$imm16),
375 !strconcat(opstr, "\t$rt, $rs, $imm16"),
376 [(set RO:$rt, (OpNode RO:$rs, imm_type:$imm16))], IIAlu, FrmI> {
377 let isReMaterializable = 1;
380 // Arithmetic Multiply ADD/SUB
381 class MArithR<string opstr, SDPatternOperator op = null_frag, bit isComm = 0> :
382 InstSE<(outs), (ins CPURegsOpnd:$rs, CPURegsOpnd:$rt),
383 !strconcat(opstr, "\t$rs, $rt"),
384 [(op CPURegsOpnd:$rs, CPURegsOpnd:$rt, LO, HI)], IIImul, FrmR> {
387 let isCommutable = isComm;
391 class LogicNOR<string opstr, RegisterOperand RC>:
392 InstSE<(outs RC:$rd), (ins RC:$rs, RC:$rt),
393 !strconcat(opstr, "\t$rd, $rs, $rt"),
394 [(set RC:$rd, (not (or RC:$rs, RC:$rt)))], IIAlu, FrmR> {
395 let isCommutable = 1;
399 class shift_rotate_imm<string opstr, Operand ImmOpnd,
400 RegisterOperand RC, SDPatternOperator OpNode = null_frag,
401 SDPatternOperator PF = null_frag> :
402 InstSE<(outs RC:$rd), (ins RC:$rt, ImmOpnd:$shamt),
403 !strconcat(opstr, "\t$rd, $rt, $shamt"),
404 [(set RC:$rd, (OpNode RC:$rt, PF:$shamt))], IIAlu, FrmR>;
406 class shift_rotate_reg<string opstr, RegisterOperand RC,
407 SDPatternOperator OpNode = null_frag>:
408 InstSE<(outs RC:$rd), (ins CPURegsOpnd:$rs, RC:$rt),
409 !strconcat(opstr, "\t$rd, $rt, $rs"),
410 [(set RC:$rd, (OpNode RC:$rt, CPURegsOpnd:$rs))], IIAlu, FrmR>;
412 // Load Upper Imediate
413 class LoadUpper<string opstr, RegisterClass RC, Operand Imm>:
414 InstSE<(outs RC:$rt), (ins Imm:$imm16), !strconcat(opstr, "\t$rt, $imm16"),
415 [], IIAlu, FrmI>, IsAsCheapAsAMove {
416 let neverHasSideEffects = 1;
417 let isReMaterializable = 1;
420 class FMem<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
421 InstrItinClass itin>: FFI<op, outs, ins, asmstr, pattern> {
423 let Inst{25-21} = addr{20-16};
424 let Inst{15-0} = addr{15-0};
425 let DecoderMethod = "DecodeMem";
429 class Load<string opstr, SDPatternOperator OpNode, RegisterClass RC,
431 InstSE<(outs RC:$rt), (ins MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
432 [(set RC:$rt, (OpNode addr:$addr))], NoItinerary, FrmI> {
433 let DecoderMethod = "DecodeMem";
434 let canFoldAsLoad = 1;
437 class Store<string opstr, SDPatternOperator OpNode, RegisterClass RC,
439 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
440 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
441 let DecoderMethod = "DecodeMem";
444 multiclass LoadM<string opstr, RegisterClass RC,
445 SDPatternOperator OpNode = null_frag> {
446 def NAME : Load<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
447 def _P8 : Load<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
448 let DecoderNamespace = "Mips64";
449 let isCodeGenOnly = 1;
453 multiclass StoreM<string opstr, RegisterClass RC,
454 SDPatternOperator OpNode = null_frag> {
455 def NAME : Store<opstr, OpNode, RC, mem>, Requires<[NotN64, HasStdEnc]>;
456 def _P8 : Store<opstr, OpNode, RC, mem64>, Requires<[IsN64, HasStdEnc]> {
457 let DecoderNamespace = "Mips64";
458 let isCodeGenOnly = 1;
462 // Load/Store Left/Right
463 let canFoldAsLoad = 1 in
464 class LoadLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
466 InstSE<(outs RC:$rt), (ins MemOpnd:$addr, RC:$src),
467 !strconcat(opstr, "\t$rt, $addr"),
468 [(set RC:$rt, (OpNode addr:$addr, RC:$src))], NoItinerary, FrmI> {
469 let DecoderMethod = "DecodeMem";
470 string Constraints = "$src = $rt";
473 class StoreLeftRight<string opstr, SDNode OpNode, RegisterClass RC,
475 InstSE<(outs), (ins RC:$rt, MemOpnd:$addr), !strconcat(opstr, "\t$rt, $addr"),
476 [(OpNode RC:$rt, addr:$addr)], NoItinerary, FrmI> {
477 let DecoderMethod = "DecodeMem";
480 multiclass LoadLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
481 def NAME : LoadLeftRight<opstr, OpNode, RC, mem>,
482 Requires<[NotN64, HasStdEnc]>;
483 def _P8 : LoadLeftRight<opstr, OpNode, RC, mem64>,
484 Requires<[IsN64, HasStdEnc]> {
485 let DecoderNamespace = "Mips64";
486 let isCodeGenOnly = 1;
490 multiclass StoreLeftRightM<string opstr, SDNode OpNode, RegisterClass RC> {
491 def NAME : StoreLeftRight<opstr, OpNode, RC, mem>,
492 Requires<[NotN64, HasStdEnc]>;
493 def _P8 : StoreLeftRight<opstr, OpNode, RC, mem64>,
494 Requires<[IsN64, HasStdEnc]> {
495 let DecoderNamespace = "Mips64";
496 let isCodeGenOnly = 1;
500 // Conditional Branch
501 class CBranch<string opstr, PatFrag cond_op, RegisterClass RC> :
502 InstSE<(outs), (ins RC:$rs, RC:$rt, brtarget:$offset),
503 !strconcat(opstr, "\t$rs, $rt, $offset"),
504 [(brcond (i32 (cond_op RC:$rs, RC:$rt)), bb:$offset)], IIBranch,
507 let isTerminator = 1;
508 let hasDelaySlot = 1;
512 class CBranchZero<string opstr, PatFrag cond_op, RegisterClass RC> :
513 InstSE<(outs), (ins RC:$rs, brtarget:$offset),
514 !strconcat(opstr, "\t$rs, $offset"),
515 [(brcond (i32 (cond_op RC:$rs, 0)), bb:$offset)], IIBranch, FrmI> {
517 let isTerminator = 1;
518 let hasDelaySlot = 1;
523 class SetCC_R<string opstr, PatFrag cond_op, RegisterClass RC> :
524 InstSE<(outs CPURegsOpnd:$rd), (ins RC:$rs, RC:$rt),
525 !strconcat(opstr, "\t$rd, $rs, $rt"),
526 [(set CPURegsOpnd:$rd, (cond_op RC:$rs, RC:$rt))], IIAlu, FrmR>;
528 class SetCC_I<string opstr, PatFrag cond_op, Operand Od, PatLeaf imm_type,
530 InstSE<(outs CPURegsOpnd:$rt), (ins RC:$rs, Od:$imm16),
531 !strconcat(opstr, "\t$rt, $rs, $imm16"),
532 [(set CPURegsOpnd:$rt, (cond_op RC:$rs, imm_type:$imm16))],
536 class JumpFJ<DAGOperand opnd, string opstr, SDPatternOperator operator,
537 SDPatternOperator targetoperator> :
538 InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"),
539 [(operator targetoperator:$target)], IIBranch, FrmJ> {
542 let hasDelaySlot = 1;
543 let DecoderMethod = "DecodeJumpTarget";
547 // Unconditional branch
548 class UncondBranch<string opstr> :
549 InstSE<(outs), (ins brtarget:$offset), !strconcat(opstr, "\t$offset"),
550 [(br bb:$offset)], IIBranch, FrmI> {
552 let isTerminator = 1;
554 let hasDelaySlot = 1;
555 let Predicates = [RelocPIC, HasStdEnc];
559 // Base class for indirect branch and return instruction classes.
560 let isTerminator=1, isBarrier=1, hasDelaySlot = 1 in
561 class JumpFR<RegisterClass RC, SDPatternOperator operator = null_frag>:
562 InstSE<(outs), (ins RC:$rs), "jr\t$rs", [(operator RC:$rs)], IIBranch, FrmR>;
565 class IndirectBranch<RegisterClass RC>: JumpFR<RC, brind> {
567 let isIndirectBranch = 1;
570 // Return instruction
571 class RetBase<RegisterClass RC>: JumpFR<RC> {
573 let isCodeGenOnly = 1;
575 let hasExtraSrcRegAllocReq = 1;
578 // Jump and Link (Call)
579 let isCall=1, hasDelaySlot=1, Defs = [RA] in {
580 class JumpLink<string opstr> :
581 InstSE<(outs), (ins calltarget:$target), !strconcat(opstr, "\t$target"),
582 [(MipsJmpLink imm:$target)], IIBranch, FrmJ> {
583 let DecoderMethod = "DecodeJumpTarget";
586 class JumpLinkRegPseudo<RegisterClass RC, Instruction JALRInst,
588 PseudoSE<(outs), (ins RC:$rs), [(MipsJmpLink RC:$rs)], IIBranch>,
589 PseudoInstExpansion<(JALRInst RetReg, RC:$rs)>;
591 class JumpLinkReg<string opstr, RegisterClass RC>:
592 InstSE<(outs RC:$rd), (ins RC:$rs), !strconcat(opstr, "\t$rd, $rs"),
595 class BGEZAL_FT<string opstr, RegisterOperand RO> :
596 InstSE<(outs), (ins RO:$rs, brtarget:$offset),
597 !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI>;
602 InstSE<(outs), (ins brtarget:$offset), "bal\t$offset", [], IIBranch, FrmI> {
604 let isTerminator = 1;
606 let hasDelaySlot = 1;
611 let hasSideEffects = 1 in
613 InstSE<(outs), (ins i32imm:$stype), "sync $stype", [(MipsSync imm:$stype)],
614 NoItinerary, FrmOther>;
617 class Mult<string opstr, InstrItinClass itin, RegisterOperand RO,
618 list<Register> DefRegs> :
619 InstSE<(outs), (ins RO:$rs, RO:$rt), !strconcat(opstr, "\t$rs, $rt"), [],
621 let isCommutable = 1;
623 let neverHasSideEffects = 1;
626 class Div<SDNode op, string opstr, InstrItinClass itin, RegisterOperand RO,
627 list<Register> DefRegs> :
628 InstSE<(outs), (ins RO:$rs, RO:$rt),
629 !strconcat(opstr, "\t$$zero, $rs, $rt"), [(op RO:$rs, RO:$rt)], itin,
635 class MoveFromLOHI<string opstr, RegisterClass RC, list<Register> UseRegs>:
636 InstSE<(outs RC:$rd), (ins), !strconcat(opstr, "\t$rd"), [], IIHiLo, FrmR> {
638 let neverHasSideEffects = 1;
641 class MoveToLOHI<string opstr, RegisterClass RC, list<Register> DefRegs>:
642 InstSE<(outs), (ins RC:$rs), !strconcat(opstr, "\t$rs"), [], IIHiLo, FrmR> {
644 let neverHasSideEffects = 1;
647 class EffectiveAddress<string opstr, RegisterClass RC, Operand Mem> :
648 InstSE<(outs RC:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
649 [(set RC:$rt, addr:$addr)], NoItinerary, FrmI> {
650 let isCodeGenOnly = 1;
651 let DecoderMethod = "DecodeMem";
654 // Count Leading Ones/Zeros in Word
655 class CountLeading0<string opstr, RegisterOperand RO>:
656 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
657 [(set RO:$rd, (ctlz RO:$rs))], IIAlu, FrmR>,
658 Requires<[HasBitCount, HasStdEnc]>;
660 class CountLeading1<string opstr, RegisterOperand RO>:
661 InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
662 [(set RO:$rd, (ctlz (not RO:$rs)))], IIAlu, FrmR>,
663 Requires<[HasBitCount, HasStdEnc]>;
666 // Sign Extend in Register.
667 class SignExtInReg<string opstr, ValueType vt, RegisterClass RC> :
668 InstSE<(outs RC:$rd), (ins RC:$rt), !strconcat(opstr, "\t$rd, $rt"),
669 [(set RC:$rd, (sext_inreg RC:$rt, vt))], NoItinerary, FrmR> {
670 let Predicates = [HasSEInReg, HasStdEnc];
674 class SubwordSwap<string opstr, RegisterOperand RO>:
675 InstSE<(outs RO:$rd), (ins RO:$rt), !strconcat(opstr, "\t$rd, $rt"), [],
677 let Predicates = [HasSwap, HasStdEnc];
678 let neverHasSideEffects = 1;
682 class ReadHardware<RegisterClass CPURegClass, RegisterOperand RO> :
683 InstSE<(outs CPURegClass:$rt), (ins RO:$rd), "rdhwr\t$rt, $rd", [],
687 class ExtBase<string opstr, RegisterOperand RO>:
688 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ext:$size),
689 !strconcat(opstr, " $rt, $rs, $pos, $size"),
690 [(set RO:$rt, (MipsExt RO:$rs, imm:$pos, imm:$size))], NoItinerary,
692 let Predicates = [HasMips32r2, HasStdEnc];
695 class InsBase<string opstr, RegisterOperand RO>:
696 InstSE<(outs RO:$rt), (ins RO:$rs, uimm16:$pos, size_ins:$size, RO:$src),
697 !strconcat(opstr, " $rt, $rs, $pos, $size"),
698 [(set RO:$rt, (MipsIns RO:$rs, imm:$pos, imm:$size, RO:$src))],
700 let Predicates = [HasMips32r2, HasStdEnc];
701 let Constraints = "$src = $rt";
704 // Atomic instructions with 2 source operands (ATOMIC_SWAP & ATOMIC_LOAD_*).
705 class Atomic2Ops<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
706 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$incr),
707 [(set DRC:$dst, (Op PRC:$ptr, DRC:$incr))]>;
709 multiclass Atomic2Ops32<PatFrag Op> {
710 def NAME : Atomic2Ops<Op, CPURegs, CPURegs>, Requires<[NotN64, HasStdEnc]>;
711 def _P8 : Atomic2Ops<Op, CPURegs, CPU64Regs>,
712 Requires<[IsN64, HasStdEnc]> {
713 let DecoderNamespace = "Mips64";
717 // Atomic Compare & Swap.
718 class AtomicCmpSwap<PatFrag Op, RegisterClass DRC, RegisterClass PRC> :
719 PseudoSE<(outs DRC:$dst), (ins PRC:$ptr, DRC:$cmp, DRC:$swap),
720 [(set DRC:$dst, (Op PRC:$ptr, DRC:$cmp, DRC:$swap))]>;
722 multiclass AtomicCmpSwap32<PatFrag Op> {
723 def NAME : AtomicCmpSwap<Op, CPURegs, CPURegs>,
724 Requires<[NotN64, HasStdEnc]>;
725 def _P8 : AtomicCmpSwap<Op, CPURegs, CPU64Regs>,
726 Requires<[IsN64, HasStdEnc]> {
727 let DecoderNamespace = "Mips64";
731 class LLBase<string opstr, RegisterOperand RO, Operand Mem> :
732 InstSE<(outs RO:$rt), (ins Mem:$addr), !strconcat(opstr, "\t$rt, $addr"),
733 [], NoItinerary, FrmI> {
734 let DecoderMethod = "DecodeMem";
738 class SCBase<string opstr, RegisterOperand RO, Operand Mem> :
739 InstSE<(outs RO:$dst), (ins RO:$rt, Mem:$addr),
740 !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> {
741 let DecoderMethod = "DecodeMem";
743 let Constraints = "$rt = $dst";
746 class MFC3OP<dag outs, dag ins, string asmstr> :
747 InstSE<outs, ins, asmstr, [], NoItinerary, FrmFR>;
749 //===----------------------------------------------------------------------===//
750 // Pseudo instructions
751 //===----------------------------------------------------------------------===//
754 let isReturn=1, isTerminator=1, hasDelaySlot=1, isBarrier=1, hasCtrlDep=1 in
755 def RetRA : PseudoSE<(outs), (ins), [(MipsRet)]>;
757 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
758 def ADJCALLSTACKDOWN : MipsPseudo<(outs), (ins i32imm:$amt),
759 [(callseq_start timm:$amt)]>;
760 def ADJCALLSTACKUP : MipsPseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
761 [(callseq_end timm:$amt1, timm:$amt2)]>;
764 let usesCustomInserter = 1 in {
765 defm ATOMIC_LOAD_ADD_I8 : Atomic2Ops32<atomic_load_add_8>;
766 defm ATOMIC_LOAD_ADD_I16 : Atomic2Ops32<atomic_load_add_16>;
767 defm ATOMIC_LOAD_ADD_I32 : Atomic2Ops32<atomic_load_add_32>;
768 defm ATOMIC_LOAD_SUB_I8 : Atomic2Ops32<atomic_load_sub_8>;
769 defm ATOMIC_LOAD_SUB_I16 : Atomic2Ops32<atomic_load_sub_16>;
770 defm ATOMIC_LOAD_SUB_I32 : Atomic2Ops32<atomic_load_sub_32>;
771 defm ATOMIC_LOAD_AND_I8 : Atomic2Ops32<atomic_load_and_8>;
772 defm ATOMIC_LOAD_AND_I16 : Atomic2Ops32<atomic_load_and_16>;
773 defm ATOMIC_LOAD_AND_I32 : Atomic2Ops32<atomic_load_and_32>;
774 defm ATOMIC_LOAD_OR_I8 : Atomic2Ops32<atomic_load_or_8>;
775 defm ATOMIC_LOAD_OR_I16 : Atomic2Ops32<atomic_load_or_16>;
776 defm ATOMIC_LOAD_OR_I32 : Atomic2Ops32<atomic_load_or_32>;
777 defm ATOMIC_LOAD_XOR_I8 : Atomic2Ops32<atomic_load_xor_8>;
778 defm ATOMIC_LOAD_XOR_I16 : Atomic2Ops32<atomic_load_xor_16>;
779 defm ATOMIC_LOAD_XOR_I32 : Atomic2Ops32<atomic_load_xor_32>;
780 defm ATOMIC_LOAD_NAND_I8 : Atomic2Ops32<atomic_load_nand_8>;
781 defm ATOMIC_LOAD_NAND_I16 : Atomic2Ops32<atomic_load_nand_16>;
782 defm ATOMIC_LOAD_NAND_I32 : Atomic2Ops32<atomic_load_nand_32>;
784 defm ATOMIC_SWAP_I8 : Atomic2Ops32<atomic_swap_8>;
785 defm ATOMIC_SWAP_I16 : Atomic2Ops32<atomic_swap_16>;
786 defm ATOMIC_SWAP_I32 : Atomic2Ops32<atomic_swap_32>;
788 defm ATOMIC_CMP_SWAP_I8 : AtomicCmpSwap32<atomic_cmp_swap_8>;
789 defm ATOMIC_CMP_SWAP_I16 : AtomicCmpSwap32<atomic_cmp_swap_16>;
790 defm ATOMIC_CMP_SWAP_I32 : AtomicCmpSwap32<atomic_cmp_swap_32>;
793 //===----------------------------------------------------------------------===//
794 // Instruction definition
795 //===----------------------------------------------------------------------===//
796 //===----------------------------------------------------------------------===//
797 // MipsI Instructions
798 //===----------------------------------------------------------------------===//
800 /// Arithmetic Instructions (ALU Immediate)
801 def ADDiu : ArithLogicI<"addiu", simm16, CPURegsOpnd, immSExt16, add>,
802 ADDI_FM<0x9>, IsAsCheapAsAMove;
803 def ADDi : ArithLogicI<"addi", simm16, CPURegsOpnd>, ADDI_FM<0x8>;
804 def SLTi : SetCC_I<"slti", setlt, simm16, immSExt16, CPURegs>, SLTI_FM<0xa>;
805 def SLTiu : SetCC_I<"sltiu", setult, simm16, immSExt16, CPURegs>, SLTI_FM<0xb>;
806 def ANDi : ArithLogicI<"andi", uimm16, CPURegsOpnd, immZExt16, and>,
808 def ORi : ArithLogicI<"ori", uimm16, CPURegsOpnd, immZExt16, or>,
810 def XORi : ArithLogicI<"xori", uimm16, CPURegsOpnd, immZExt16, xor>,
812 def LUi : LoadUpper<"lui", CPURegs, uimm16>, LUI_FM;
814 /// Arithmetic Instructions (3-Operand, R-Type)
815 def ADDu : ArithLogicR<"addu", CPURegsOpnd, 1, IIAlu, add>, ADD_FM<0, 0x21>;
816 def SUBu : ArithLogicR<"subu", CPURegsOpnd, 0, IIAlu, sub>, ADD_FM<0, 0x23>;
817 def MUL : ArithLogicR<"mul", CPURegsOpnd, 1, IIImul, mul>, ADD_FM<0x1c, 2>;
818 def ADD : ArithLogicR<"add", CPURegsOpnd>, ADD_FM<0, 0x20>;
819 def SUB : ArithLogicR<"sub", CPURegsOpnd>, ADD_FM<0, 0x22>;
820 def SLT : SetCC_R<"slt", setlt, CPURegs>, ADD_FM<0, 0x2a>;
821 def SLTu : SetCC_R<"sltu", setult, CPURegs>, ADD_FM<0, 0x2b>;
822 def AND : ArithLogicR<"and", CPURegsOpnd, 1, IIAlu, and>, ADD_FM<0, 0x24>;
823 def OR : ArithLogicR<"or", CPURegsOpnd, 1, IIAlu, or>, ADD_FM<0, 0x25>;
824 def XOR : ArithLogicR<"xor", CPURegsOpnd, 1, IIAlu, xor>, ADD_FM<0, 0x26>;
825 def NOR : LogicNOR<"nor", CPURegsOpnd>, ADD_FM<0, 0x27>;
827 /// Shift Instructions
828 def SLL : shift_rotate_imm<"sll", shamt, CPURegsOpnd, shl, immZExt5>,
830 def SRL : shift_rotate_imm<"srl", shamt, CPURegsOpnd, srl, immZExt5>,
832 def SRA : shift_rotate_imm<"sra", shamt, CPURegsOpnd, sra, immZExt5>,
834 def SLLV : shift_rotate_reg<"sllv", CPURegsOpnd, shl>, SRLV_FM<4, 0>;
835 def SRLV : shift_rotate_reg<"srlv", CPURegsOpnd, srl>, SRLV_FM<6, 0>;
836 def SRAV : shift_rotate_reg<"srav", CPURegsOpnd, sra>, SRLV_FM<7, 0>;
838 // Rotate Instructions
839 let Predicates = [HasMips32r2, HasStdEnc] in {
840 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>,
842 def ROTRV : shift_rotate_reg<"rotrv", CPURegsOpnd, rotr>, SRLV_FM<6, 1>;
845 /// Load and Store Instructions
847 defm LB : LoadM<"lb", CPURegs, sextloadi8>, LW_FM<0x20>;
848 defm LBu : LoadM<"lbu", CPURegs, zextloadi8>, LW_FM<0x24>;
849 defm LH : LoadM<"lh", CPURegs, sextloadi16>, LW_FM<0x21>;
850 defm LHu : LoadM<"lhu", CPURegs, zextloadi16>, LW_FM<0x25>;
851 defm LW : LoadM<"lw", CPURegs, load>, LW_FM<0x23>;
852 defm SB : StoreM<"sb", CPURegs, truncstorei8>, LW_FM<0x28>;
853 defm SH : StoreM<"sh", CPURegs, truncstorei16>, LW_FM<0x29>;
854 defm SW : StoreM<"sw", CPURegs, store>, LW_FM<0x2b>;
856 /// load/store left/right
857 defm LWL : LoadLeftRightM<"lwl", MipsLWL, CPURegs>, LW_FM<0x22>;
858 defm LWR : LoadLeftRightM<"lwr", MipsLWR, CPURegs>, LW_FM<0x26>;
859 defm SWL : StoreLeftRightM<"swl", MipsSWL, CPURegs>, LW_FM<0x2a>;
860 defm SWR : StoreLeftRightM<"swr", MipsSWR, CPURegs>, LW_FM<0x2e>;
862 def SYNC : SYNC_FT, SYNC_FM;
864 /// Load-linked, Store-conditional
865 let Predicates = [NotN64, HasStdEnc] in {
866 def LL : LLBase<"ll", CPURegsOpnd, mem>, LW_FM<0x30>;
867 def SC : SCBase<"sc", CPURegsOpnd, mem>, LW_FM<0x38>;
870 let Predicates = [IsN64, HasStdEnc], DecoderNamespace = "Mips64" in {
871 def LL_P8 : LLBase<"ll", CPURegsOpnd, mem64>, LW_FM<0x30>;
872 def SC_P8 : SCBase<"sc", CPURegsOpnd, mem64>, LW_FM<0x38>;
875 /// Jump and Branch Instructions
876 def J : JumpFJ<jmptarget, "j", br, bb>, FJ<2>,
877 Requires<[RelocStatic, HasStdEnc]>, IsBranch;
878 def JR : IndirectBranch<CPURegs>, MTLO_FM<8>;
879 def B : UncondBranch<"b">, B_FM;
880 def BEQ : CBranch<"beq", seteq, CPURegs>, BEQ_FM<4>;
881 def BNE : CBranch<"bne", setne, CPURegs>, BEQ_FM<5>;
882 def BGEZ : CBranchZero<"bgez", setge, CPURegs>, BGEZ_FM<1, 1>;
883 def BGTZ : CBranchZero<"bgtz", setgt, CPURegs>, BGEZ_FM<7, 0>;
884 def BLEZ : CBranchZero<"blez", setle, CPURegs>, BGEZ_FM<6, 0>;
885 def BLTZ : CBranchZero<"bltz", setlt, CPURegs>, BGEZ_FM<1, 0>;
887 def BAL_BR: BAL_FT, BAL_FM;
889 def JAL : JumpLink<"jal">, FJ<3>;
890 def JALR : JumpLinkReg<"jalr", CPURegs>, JALR_FM;
891 def JALRPseudo : JumpLinkRegPseudo<CPURegs, JALR, RA>;
892 def BGEZAL : BGEZAL_FT<"bgezal", CPURegsOpnd>, BGEZAL_FM<0x11>;
893 def BLTZAL : BGEZAL_FT<"bltzal", CPURegsOpnd>, BGEZAL_FM<0x10>;
894 def TAILCALL : JumpFJ<calltarget, "j", MipsTailCall, imm>, FJ<2>, IsTailCall;
895 def TAILCALL_R : JumpFR<CPURegs, MipsTailCall>, MTLO_FM<8>, IsTailCall;
897 def RET : RetBase<CPURegs>, MTLO_FM<8>;
899 // Exception handling related node and instructions.
900 // The conversion sequence is:
901 // ISD::EH_RETURN -> MipsISD::EH_RETURN ->
902 // MIPSeh_return -> (stack change + indirect branch)
904 // MIPSeh_return takes the place of regular return instruction
905 // but takes two arguments (V1, V0) which are used for storing
906 // the offset and return address respectively.
907 def SDT_MipsEHRET : SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisPtrTy<1>]>;
909 def MIPSehret : SDNode<"MipsISD::EH_RETURN", SDT_MipsEHRET,
910 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
912 let Uses = [V0, V1], isTerminator = 1, isReturn = 1, isBarrier = 1 in {
913 def MIPSeh_return32 : MipsPseudo<(outs), (ins CPURegs:$spoff, CPURegs:$dst),
914 [(MIPSehret CPURegs:$spoff, CPURegs:$dst)]>;
915 def MIPSeh_return64 : MipsPseudo<(outs), (ins CPU64Regs:$spoff,
917 [(MIPSehret CPU64Regs:$spoff, CPU64Regs:$dst)]>;
920 /// Multiply and Divide Instructions.
921 def MULT : Mult<"mult", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x18>;
922 def MULTu : Mult<"multu", IIImul, CPURegsOpnd, [HI, LO]>, MULT_FM<0, 0x19>;
923 def SDIV : Div<MipsDivRem, "div", IIIdiv, CPURegsOpnd, [HI, LO]>,
925 def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
928 def MTHI : MoveToLOHI<"mthi", CPURegs, [HI]>, MTLO_FM<0x11>;
929 def MTLO : MoveToLOHI<"mtlo", CPURegs, [LO]>, MTLO_FM<0x13>;
930 def MFHI : MoveFromLOHI<"mfhi", CPURegs, [HI]>, MFLO_FM<0x10>;
931 def MFLO : MoveFromLOHI<"mflo", CPURegs, [LO]>, MFLO_FM<0x12>;
933 /// Sign Ext In Register Instructions.
934 def SEB : SignExtInReg<"seb", i8, CPURegs>, SEB_FM<0x10, 0x20>;
935 def SEH : SignExtInReg<"seh", i16, CPURegs>, SEB_FM<0x18, 0x20>;
938 def CLZ : CountLeading0<"clz", CPURegsOpnd>, CLO_FM<0x20>;
939 def CLO : CountLeading1<"clo", CPURegsOpnd>, CLO_FM<0x21>;
941 /// Word Swap Bytes Within Halfwords
942 def WSBH : SubwordSwap<"wsbh", CPURegsOpnd>, SEB_FM<2, 0x20>;
945 def NOP : PseudoSE<(outs), (ins), []>, PseudoInstExpansion<(SLL ZERO, ZERO, 0)>;
947 // FrameIndexes are legalized when they are operands from load/store
948 // instructions. The same not happens for stack address copies, so an
949 // add op with mem ComplexPattern is used and the stack address copy
950 // can be matched. It's similar to Sparc LEA_ADDRi
951 def LEA_ADDiu : EffectiveAddress<"addiu", CPURegs, mem_ea>, LW_FM<9>;
954 def MADD : MArithR<"madd", MipsMAdd, 1>, MULT_FM<0x1c, 0>;
955 def MADDU : MArithR<"maddu", MipsMAddu, 1>, MULT_FM<0x1c, 1>;
956 def MSUB : MArithR<"msub", MipsMSub>, MULT_FM<0x1c, 4>;
957 def MSUBU : MArithR<"msubu", MipsMSubu>, MULT_FM<0x1c, 5>;
959 def RDHWR : ReadHardware<CPURegs, HWRegsOpnd>, RDHWR_FM;
961 def EXT : ExtBase<"ext", CPURegsOpnd>, EXT_FM<0>;
962 def INS : InsBase<"ins", CPURegsOpnd>, EXT_FM<4>;
964 /// Move Control Registers From/To CPU Registers
965 def MFC0_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
966 (ins CPURegsOpnd:$rd, uimm16:$sel),
967 "mfc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 0>;
969 def MTC0_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
970 (ins CPURegsOpnd:$rt),
971 "mtc0\t$rt, $rd, $sel">, MFC3OP_FM<0x10, 4>;
973 def MFC2_3OP : MFC3OP<(outs CPURegsOpnd:$rt),
974 (ins CPURegsOpnd:$rd, uimm16:$sel),
975 "mfc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 0>;
977 def MTC2_3OP : MFC3OP<(outs CPURegsOpnd:$rd, uimm16:$sel),
978 (ins CPURegsOpnd:$rt),
979 "mtc2\t$rt, $rd, $sel">, MFC3OP_FM<0x12, 4>;
981 //===----------------------------------------------------------------------===//
982 // Instruction aliases
983 //===----------------------------------------------------------------------===//
984 def : InstAlias<"move $dst, $src",
985 (ADDu CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 1>,
986 Requires<[NotMips64]>;
987 def : InstAlias<"move $dst, $src",
988 (OR CPURegsOpnd:$dst, CPURegsOpnd:$src,ZERO), 0>,
989 Requires<[NotMips64]>;
990 def : InstAlias<"bal $offset", (BGEZAL RA, brtarget:$offset), 1>;
991 def : InstAlias<"addu $rs, $rt, $imm",
992 (ADDiu CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
993 def : InstAlias<"add $rs, $rt, $imm",
994 (ADDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
995 def : InstAlias<"and $rs, $rt, $imm",
996 (ANDi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>;
997 def : InstAlias<"j $rs", (JR CPURegs:$rs), 0>,
998 Requires<[NotMips64]>;
999 def : InstAlias<"jalr $rs", (JALR RA, CPURegs:$rs)>, Requires<[NotMips64]>;
1000 def : InstAlias<"not $rt, $rs",
1001 (NOR CPURegsOpnd:$rt, CPURegsOpnd:$rs, ZERO), 1>;
1002 def : InstAlias<"neg $rt, $rs",
1003 (SUB CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1004 def : InstAlias<"negu $rt, $rs",
1005 (SUBu CPURegsOpnd:$rt, ZERO, CPURegsOpnd:$rs), 1>;
1006 def : InstAlias<"slt $rs, $rt, $imm",
1007 (SLTi CPURegsOpnd:$rs, CPURegs:$rt, simm16:$imm), 0>;
1008 def : InstAlias<"xor $rs, $rt, $imm",
1009 (XORi CPURegsOpnd:$rs, CPURegsOpnd:$rt, simm16:$imm), 0>,
1010 Requires<[NotMips64]>;
1011 def : InstAlias<"nop", (SLL ZERO, ZERO, 0), 1>;
1012 def : InstAlias<"mfc0 $rt, $rd",
1013 (MFC0_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1014 def : InstAlias<"mtc0 $rt, $rd",
1015 (MTC0_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1016 def : InstAlias<"mfc2 $rt, $rd",
1017 (MFC2_3OP CPURegsOpnd:$rt, CPURegsOpnd:$rd, 0), 0>;
1018 def : InstAlias<"mtc2 $rt, $rd",
1019 (MTC2_3OP CPURegsOpnd:$rd, 0, CPURegsOpnd:$rt), 0>;
1021 //===----------------------------------------------------------------------===//
1022 // Assembler Pseudo Instructions
1023 //===----------------------------------------------------------------------===//
1025 class LoadImm32< string instr_asm, Operand Od, RegisterOperand RO> :
1026 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1027 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1028 def LoadImm32Reg : LoadImm32<"li", shamt,CPURegsOpnd>;
1030 class LoadAddress<string instr_asm, Operand MemOpnd, RegisterOperand RO> :
1031 MipsAsmPseudoInst<(outs RO:$rt), (ins MemOpnd:$addr),
1032 !strconcat(instr_asm, "\t$rt, $addr")> ;
1033 def LoadAddr32Reg : LoadAddress<"la", mem, CPURegsOpnd>;
1035 class LoadAddressImm<string instr_asm, Operand Od, RegisterOperand RO> :
1036 MipsAsmPseudoInst<(outs RO:$rt), (ins Od:$imm32),
1037 !strconcat(instr_asm, "\t$rt, $imm32")> ;
1038 def LoadAddr32Imm : LoadAddressImm<"la", shamt,CPURegsOpnd>;
1042 //===----------------------------------------------------------------------===//
1043 // Arbitrary patterns that map to one or more instructions
1044 //===----------------------------------------------------------------------===//
1047 def : MipsPat<(i32 immSExt16:$in),
1048 (ADDiu ZERO, imm:$in)>;
1049 def : MipsPat<(i32 immZExt16:$in),
1050 (ORi ZERO, imm:$in)>;
1051 def : MipsPat<(i32 immLow16Zero:$in),
1052 (LUi (HI16 imm:$in))>;
1054 // Arbitrary immediates
1055 def : MipsPat<(i32 imm:$imm),
1056 (ORi (LUi (HI16 imm:$imm)), (LO16 imm:$imm))>;
1058 // Carry MipsPatterns
1059 def : MipsPat<(subc CPURegs:$lhs, CPURegs:$rhs),
1060 (SUBu CPURegs:$lhs, CPURegs:$rhs)>;
1061 def : MipsPat<(addc CPURegs:$lhs, CPURegs:$rhs),
1062 (ADDu CPURegs:$lhs, CPURegs:$rhs)>;
1063 def : MipsPat<(addc CPURegs:$src, immSExt16:$imm),
1064 (ADDiu CPURegs:$src, imm:$imm)>;
1067 def : MipsPat<(MipsJmpLink (i32 tglobaladdr:$dst)),
1068 (JAL tglobaladdr:$dst)>;
1069 def : MipsPat<(MipsJmpLink (i32 texternalsym:$dst)),
1070 (JAL texternalsym:$dst)>;
1071 //def : MipsPat<(MipsJmpLink CPURegs:$dst),
1072 // (JALR CPURegs:$dst)>;
1075 def : MipsPat<(MipsTailCall (iPTR tglobaladdr:$dst)),
1076 (TAILCALL tglobaladdr:$dst)>;
1077 def : MipsPat<(MipsTailCall (iPTR texternalsym:$dst)),
1078 (TAILCALL texternalsym:$dst)>;
1080 def : MipsPat<(MipsHi tglobaladdr:$in), (LUi tglobaladdr:$in)>;
1081 def : MipsPat<(MipsHi tblockaddress:$in), (LUi tblockaddress:$in)>;
1082 def : MipsPat<(MipsHi tjumptable:$in), (LUi tjumptable:$in)>;
1083 def : MipsPat<(MipsHi tconstpool:$in), (LUi tconstpool:$in)>;
1084 def : MipsPat<(MipsHi tglobaltlsaddr:$in), (LUi tglobaltlsaddr:$in)>;
1085 def : MipsPat<(MipsHi texternalsym:$in), (LUi texternalsym:$in)>;
1087 def : MipsPat<(MipsLo tglobaladdr:$in), (ADDiu ZERO, tglobaladdr:$in)>;
1088 def : MipsPat<(MipsLo tblockaddress:$in), (ADDiu ZERO, tblockaddress:$in)>;
1089 def : MipsPat<(MipsLo tjumptable:$in), (ADDiu ZERO, tjumptable:$in)>;
1090 def : MipsPat<(MipsLo tconstpool:$in), (ADDiu ZERO, tconstpool:$in)>;
1091 def : MipsPat<(MipsLo tglobaltlsaddr:$in), (ADDiu ZERO, tglobaltlsaddr:$in)>;
1092 def : MipsPat<(MipsLo texternalsym:$in), (ADDiu ZERO, texternalsym:$in)>;
1094 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaladdr:$lo)),
1095 (ADDiu CPURegs:$hi, tglobaladdr:$lo)>;
1096 def : MipsPat<(add CPURegs:$hi, (MipsLo tblockaddress:$lo)),
1097 (ADDiu CPURegs:$hi, tblockaddress:$lo)>;
1098 def : MipsPat<(add CPURegs:$hi, (MipsLo tjumptable:$lo)),
1099 (ADDiu CPURegs:$hi, tjumptable:$lo)>;
1100 def : MipsPat<(add CPURegs:$hi, (MipsLo tconstpool:$lo)),
1101 (ADDiu CPURegs:$hi, tconstpool:$lo)>;
1102 def : MipsPat<(add CPURegs:$hi, (MipsLo tglobaltlsaddr:$lo)),
1103 (ADDiu CPURegs:$hi, tglobaltlsaddr:$lo)>;
1106 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tglobaladdr:$in)),
1107 (ADDiu CPURegs:$gp, tglobaladdr:$in)>;
1108 def : MipsPat<(add CPURegs:$gp, (MipsGPRel tconstpool:$in)),
1109 (ADDiu CPURegs:$gp, tconstpool:$in)>;
1112 class WrapperPat<SDNode node, Instruction ADDiuOp, RegisterClass RC>:
1113 MipsPat<(MipsWrapper RC:$gp, node:$in),
1114 (ADDiuOp RC:$gp, node:$in)>;
1116 def : WrapperPat<tglobaladdr, ADDiu, CPURegs>;
1117 def : WrapperPat<tconstpool, ADDiu, CPURegs>;
1118 def : WrapperPat<texternalsym, ADDiu, CPURegs>;
1119 def : WrapperPat<tblockaddress, ADDiu, CPURegs>;
1120 def : WrapperPat<tjumptable, ADDiu, CPURegs>;
1121 def : WrapperPat<tglobaltlsaddr, ADDiu, CPURegs>;
1123 // Mips does not have "not", so we expand our way
1124 def : MipsPat<(not CPURegs:$in),
1125 (NOR CPURegsOpnd:$in, ZERO)>;
1128 let Predicates = [NotN64, HasStdEnc] in {
1129 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu addr:$src)>;
1130 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu addr:$src)>;
1131 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu addr:$src)>;
1133 let Predicates = [IsN64, HasStdEnc] in {
1134 def : MipsPat<(i32 (extloadi1 addr:$src)), (LBu_P8 addr:$src)>;
1135 def : MipsPat<(i32 (extloadi8 addr:$src)), (LBu_P8 addr:$src)>;
1136 def : MipsPat<(i32 (extloadi16 addr:$src)), (LHu_P8 addr:$src)>;
1140 let Predicates = [NotN64, HasStdEnc] in {
1141 def : MipsPat<(store (i32 0), addr:$dst), (SW ZERO, addr:$dst)>;
1143 let Predicates = [IsN64, HasStdEnc] in {
1144 def : MipsPat<(store (i32 0), addr:$dst), (SW_P8 ZERO, addr:$dst)>;
1148 multiclass BrcondPats<RegisterClass RC, Instruction BEQOp, Instruction BNEOp,
1149 Instruction SLTOp, Instruction SLTuOp, Instruction SLTiOp,
1150 Instruction SLTiuOp, Register ZEROReg> {
1151 def : MipsPat<(brcond (i32 (setne RC:$lhs, 0)), bb:$dst),
1152 (BNEOp RC:$lhs, ZEROReg, bb:$dst)>;
1153 def : MipsPat<(brcond (i32 (seteq RC:$lhs, 0)), bb:$dst),
1154 (BEQOp RC:$lhs, ZEROReg, bb:$dst)>;
1156 def : MipsPat<(brcond (i32 (setge RC:$lhs, RC:$rhs)), bb:$dst),
1157 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1158 def : MipsPat<(brcond (i32 (setuge RC:$lhs, RC:$rhs)), bb:$dst),
1159 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1160 def : MipsPat<(brcond (i32 (setge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1161 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1162 def : MipsPat<(brcond (i32 (setuge RC:$lhs, immSExt16:$rhs)), bb:$dst),
1163 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1165 def : MipsPat<(brcond (i32 (setle RC:$lhs, RC:$rhs)), bb:$dst),
1166 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1167 def : MipsPat<(brcond (i32 (setule RC:$lhs, RC:$rhs)), bb:$dst),
1168 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1170 def : MipsPat<(brcond RC:$cond, bb:$dst),
1171 (BNEOp RC:$cond, ZEROReg, bb:$dst)>;
1174 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
1177 multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
1178 Instruction SLTuOp, Register ZEROReg> {
1179 def : MipsPat<(seteq RC:$lhs, RC:$rhs),
1180 (SLTiuOp (XOROp RC:$lhs, RC:$rhs), 1)>;
1181 def : MipsPat<(setne RC:$lhs, RC:$rhs),
1182 (SLTuOp ZEROReg, (XOROp RC:$lhs, RC:$rhs))>;
1185 multiclass SetlePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1186 def : MipsPat<(setle RC:$lhs, RC:$rhs),
1187 (XORi (SLTOp RC:$rhs, RC:$lhs), 1)>;
1188 def : MipsPat<(setule RC:$lhs, RC:$rhs),
1189 (XORi (SLTuOp RC:$rhs, RC:$lhs), 1)>;
1192 multiclass SetgtPats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1193 def : MipsPat<(setgt RC:$lhs, RC:$rhs),
1194 (SLTOp RC:$rhs, RC:$lhs)>;
1195 def : MipsPat<(setugt RC:$lhs, RC:$rhs),
1196 (SLTuOp RC:$rhs, RC:$lhs)>;
1199 multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> {
1200 def : MipsPat<(setge RC:$lhs, RC:$rhs),
1201 (XORi (SLTOp RC:$lhs, RC:$rhs), 1)>;
1202 def : MipsPat<(setuge RC:$lhs, RC:$rhs),
1203 (XORi (SLTuOp RC:$lhs, RC:$rhs), 1)>;
1206 multiclass SetgeImmPats<RegisterClass RC, Instruction SLTiOp,
1207 Instruction SLTiuOp> {
1208 def : MipsPat<(setge RC:$lhs, immSExt16:$rhs),
1209 (XORi (SLTiOp RC:$lhs, immSExt16:$rhs), 1)>;
1210 def : MipsPat<(setuge RC:$lhs, immSExt16:$rhs),
1211 (XORi (SLTiuOp RC:$lhs, immSExt16:$rhs), 1)>;
1214 defm : SeteqPats<CPURegs, SLTiu, XOR, SLTu, ZERO>;
1215 defm : SetlePats<CPURegs, SLT, SLTu>;
1216 defm : SetgtPats<CPURegs, SLT, SLTu>;
1217 defm : SetgePats<CPURegs, SLT, SLTu>;
1218 defm : SetgeImmPats<CPURegs, SLTi, SLTiu>;
1221 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
1223 //===----------------------------------------------------------------------===//
1224 // Floating Point Support
1225 //===----------------------------------------------------------------------===//
1227 include "MipsInstrFPU.td"
1228 include "Mips64InstrInfo.td"
1229 include "MipsCondMov.td"
1234 include "Mips16InstrFormats.td"
1235 include "Mips16InstrInfo.td"
1238 include "MipsDSPInstrFormats.td"
1239 include "MipsDSPInstrInfo.td"