1 //===-- MipsLongBranch.cpp - Emit long branches ---------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This pass expands a branch or jump instruction into a long branch if its
11 // offset is too large to fit into its immediate field.
13 // FIXME: Fix pc-region jump instructions which cross 256MB segment boundaries.
14 //===----------------------------------------------------------------------===//
17 #include "MCTargetDesc/MipsBaseInfo.h"
18 #include "MCTargetDesc/MipsMCNaCl.h"
19 #include "MipsMachineFunction.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/Statistic.h"
22 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/Support/CommandLine.h"
26 #include "llvm/Support/MathExtras.h"
27 #include "llvm/Target/TargetInstrInfo.h"
28 #include "llvm/Target/TargetMachine.h"
29 #include "llvm/Target/TargetRegisterInfo.h"
33 #define DEBUG_TYPE "mips-long-branch"
35 STATISTIC(LongBranches, "Number of long branches.");
37 static cl::opt<bool> SkipLongBranch(
38 "skip-mips-long-branch",
40 cl::desc("MIPS: Skip long branch pass."),
43 static cl::opt<bool> ForceLongBranch(
44 "force-mips-long-branch",
46 cl::desc("MIPS: Expand all branches to long format."),
50 typedef MachineBasicBlock::iterator Iter;
51 typedef MachineBasicBlock::reverse_iterator ReverseIter;
54 uint64_t Size, Address;
58 MBBInfo() : Size(0), HasLongBranch(false), Br(nullptr) {}
61 class MipsLongBranch : public MachineFunctionPass {
65 MipsLongBranch(TargetMachine &tm)
66 : MachineFunctionPass(ID), TM(tm),
67 IsPIC(TM.getRelocationModel() == Reloc::PIC_),
68 ABI(static_cast<const MipsTargetMachine &>(TM).getABI()) {}
70 const char *getPassName() const override {
71 return "Mips Long Branch";
74 bool runOnMachineFunction(MachineFunction &F) override;
77 void splitMBB(MachineBasicBlock *MBB);
79 int64_t computeOffset(const MachineInstr *Br);
80 void replaceBranch(MachineBasicBlock &MBB, Iter Br, DebugLoc DL,
81 MachineBasicBlock *MBBOpnd);
82 void expandToLongBranch(MBBInfo &Info);
84 const TargetMachine &TM;
86 SmallVector<MBBInfo, 16> MBBInfos;
89 unsigned LongBranchSeqSize;
92 char MipsLongBranch::ID = 0;
93 } // end of anonymous namespace
95 /// createMipsLongBranchPass - Returns a pass that converts branches to long
97 FunctionPass *llvm::createMipsLongBranchPass(MipsTargetMachine &tm) {
98 return new MipsLongBranch(tm);
101 /// Iterate over list of Br's operands and search for a MachineBasicBlock
103 static MachineBasicBlock *getTargetMBB(const MachineInstr &Br) {
104 for (unsigned I = 0, E = Br.getDesc().getNumOperands(); I < E; ++I) {
105 const MachineOperand &MO = Br.getOperand(I);
111 llvm_unreachable("This instruction does not have an MBB operand.");
114 // Traverse the list of instructions backwards until a non-debug instruction is
115 // found or it reaches E.
116 static ReverseIter getNonDebugInstr(ReverseIter B, ReverseIter E) {
118 if (!B->isDebugValue())
124 // Split MBB if it has two direct jumps/branches.
125 void MipsLongBranch::splitMBB(MachineBasicBlock *MBB) {
126 ReverseIter End = MBB->rend();
127 ReverseIter LastBr = getNonDebugInstr(MBB->rbegin(), End);
129 // Return if MBB has no branch instructions.
130 if ((LastBr == End) ||
131 (!LastBr->isConditionalBranch() && !LastBr->isUnconditionalBranch()))
134 ReverseIter FirstBr = getNonDebugInstr(std::next(LastBr), End);
136 // MBB has only one branch instruction if FirstBr is not a branch
138 if ((FirstBr == End) ||
139 (!FirstBr->isConditionalBranch() && !FirstBr->isUnconditionalBranch()))
142 assert(!FirstBr->isIndirectBranch() && "Unexpected indirect branch found.");
144 // Create a new MBB. Move instructions in MBB to the newly created MBB.
145 MachineBasicBlock *NewMBB =
146 MF->CreateMachineBasicBlock(MBB->getBasicBlock());
148 // Insert NewMBB and fix control flow.
149 MachineBasicBlock *Tgt = getTargetMBB(*FirstBr);
150 NewMBB->transferSuccessors(MBB);
151 NewMBB->removeSuccessor(Tgt);
152 MBB->addSuccessor(NewMBB);
153 MBB->addSuccessor(Tgt);
154 MF->insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
156 NewMBB->splice(NewMBB->end(), MBB, (++LastBr).base(), MBB->end());
160 void MipsLongBranch::initMBBInfo() {
161 // Split the MBBs if they have two branches. Each basic block should have at
162 // most one branch after this loop is executed.
163 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E;)
166 MF->RenumberBlocks();
168 MBBInfos.resize(MF->size());
170 const MipsInstrInfo *TII =
171 static_cast<const MipsInstrInfo *>(MF->getSubtarget().getInstrInfo());
172 for (unsigned I = 0, E = MBBInfos.size(); I < E; ++I) {
173 MachineBasicBlock *MBB = MF->getBlockNumbered(I);
175 // Compute size of MBB.
176 for (MachineBasicBlock::instr_iterator MI = MBB->instr_begin();
177 MI != MBB->instr_end(); ++MI)
178 MBBInfos[I].Size += TII->GetInstSizeInBytes(&*MI);
180 // Search for MBB's branch instruction.
181 ReverseIter End = MBB->rend();
182 ReverseIter Br = getNonDebugInstr(MBB->rbegin(), End);
184 if ((Br != End) && !Br->isIndirectBranch() &&
185 (Br->isConditionalBranch() ||
186 (Br->isUnconditionalBranch() &&
187 TM.getRelocationModel() == Reloc::PIC_)))
188 MBBInfos[I].Br = (++Br).base();
192 // Compute offset of branch in number of bytes.
193 int64_t MipsLongBranch::computeOffset(const MachineInstr *Br) {
195 int ThisMBB = Br->getParent()->getNumber();
196 int TargetMBB = getTargetMBB(*Br)->getNumber();
198 // Compute offset of a forward branch.
199 if (ThisMBB < TargetMBB) {
200 for (int N = ThisMBB + 1; N < TargetMBB; ++N)
201 Offset += MBBInfos[N].Size;
206 // Compute offset of a backward branch.
207 for (int N = ThisMBB; N >= TargetMBB; --N)
208 Offset += MBBInfos[N].Size;
213 // Replace Br with a branch which has the opposite condition code and a
214 // MachineBasicBlock operand MBBOpnd.
215 void MipsLongBranch::replaceBranch(MachineBasicBlock &MBB, Iter Br,
216 DebugLoc DL, MachineBasicBlock *MBBOpnd) {
217 const MipsInstrInfo *TII = static_cast<const MipsInstrInfo *>(
218 MBB.getParent()->getSubtarget().getInstrInfo());
219 unsigned NewOpc = TII->getOppositeBranchOpc(Br->getOpcode());
220 const MCInstrDesc &NewDesc = TII->get(NewOpc);
222 MachineInstrBuilder MIB = BuildMI(MBB, Br, DL, NewDesc);
224 for (unsigned I = 0, E = Br->getDesc().getNumOperands(); I < E; ++I) {
225 MachineOperand &MO = Br->getOperand(I);
228 assert(MO.isMBB() && "MBB operand expected.");
232 MIB.addReg(MO.getReg());
237 if (Br->hasDelaySlot()) {
238 // Bundle the instruction in the delay slot to the newly created branch
239 // and erase the original branch.
240 assert(Br->isBundledWithSucc());
241 MachineBasicBlock::instr_iterator II(Br);
242 MIBundleBuilder(&*MIB).append((++II)->removeFromBundle());
244 Br->eraseFromParent();
247 // Expand branch instructions to long branches.
248 // TODO: This function has to be fixed for beqz16 and bnez16, because it
249 // currently assumes that all branches have 16-bit offsets, and will produce
250 // wrong code if branches whose allowed offsets are [-128, -126, ..., 126]
252 void MipsLongBranch::expandToLongBranch(MBBInfo &I) {
253 MachineBasicBlock::iterator Pos;
254 MachineBasicBlock *MBB = I.Br->getParent(), *TgtMBB = getTargetMBB(*I.Br);
255 DebugLoc DL = I.Br->getDebugLoc();
256 const BasicBlock *BB = MBB->getBasicBlock();
257 MachineFunction::iterator FallThroughMBB = ++MachineFunction::iterator(MBB);
258 MachineBasicBlock *LongBrMBB = MF->CreateMachineBasicBlock(BB);
259 const MipsSubtarget &Subtarget =
260 static_cast<const MipsSubtarget &>(MF->getSubtarget());
261 const MipsInstrInfo *TII =
262 static_cast<const MipsInstrInfo *>(Subtarget.getInstrInfo());
264 MF->insert(FallThroughMBB, LongBrMBB);
265 MBB->removeSuccessor(TgtMBB);
266 MBB->addSuccessor(LongBrMBB);
269 MachineBasicBlock *BalTgtMBB = MF->CreateMachineBasicBlock(BB);
270 MF->insert(FallThroughMBB, BalTgtMBB);
271 LongBrMBB->addSuccessor(BalTgtMBB);
272 BalTgtMBB->addSuccessor(TgtMBB);
274 // We must select between the MIPS32r6/MIPS64r6 BAL (which is a normal
275 // instruction) and the pre-MIPS32r6/MIPS64r6 definition (which is an
276 // pseudo-instruction wrapping BGEZAL).
277 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
281 // addiu $sp, $sp, -8
283 // lui $at, %hi($tgt - $baltgt)
285 // addiu $at, $at, %lo($tgt - $baltgt)
287 // addu $at, $ra, $at
294 Pos = LongBrMBB->begin();
296 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
297 .addReg(Mips::SP).addImm(-8);
298 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SW)).addReg(Mips::RA)
299 .addReg(Mips::SP).addImm(0);
301 // LUi and ADDiu instructions create 32-bit offset of the target basic
302 // block from the target of BAL instruction. We cannot use immediate
303 // value for this offset because it cannot be determined accurately when
304 // the program has inline assembly statements. We therefore use the
305 // relocation expressions %hi($tgt-$baltgt) and %lo($tgt-$baltgt) which
306 // are resolved during the fixup, so the values will always be correct.
308 // Since we cannot create %hi($tgt-$baltgt) and %lo($tgt-$baltgt)
309 // expressions at this point (it is possible only at the MC layer),
310 // we replace LUi and ADDiu with pseudo instructions
311 // LONG_BRANCH_LUi and LONG_BRANCH_ADDiu, and add both basic
312 // blocks as operands to these instructions. When lowering these pseudo
313 // instructions to LUi and ADDiu in the MC layer, we will create
314 // %hi($tgt-$baltgt) and %lo($tgt-$baltgt) expressions and add them as
315 // operands to lowered instructions.
317 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_LUi), Mips::AT)
318 .addMBB(TgtMBB).addMBB(BalTgtMBB);
319 MIBundleBuilder(*LongBrMBB, Pos)
320 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
321 .append(BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_ADDiu), Mips::AT)
326 Pos = BalTgtMBB->begin();
328 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDu), Mips::AT)
329 .addReg(Mips::RA).addReg(Mips::AT);
330 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LW), Mips::RA)
331 .addReg(Mips::SP).addImm(0);
333 if (!Subtarget.isTargetNaCl()) {
334 MIBundleBuilder(*BalTgtMBB, Pos)
335 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
336 .append(BuildMI(*MF, DL, TII->get(Mips::ADDiu), Mips::SP)
337 .addReg(Mips::SP).addImm(8));
339 // In NaCl, modifying the sp is not allowed in branch delay slot.
340 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP)
341 .addReg(Mips::SP).addImm(8);
343 MIBundleBuilder(*BalTgtMBB, Pos)
344 .append(BuildMI(*MF, DL, TII->get(Mips::JR)).addReg(Mips::AT))
345 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
347 // Bundle-align the target of indirect branch JR.
348 TgtMBB->setAlignment(MIPS_NACL_BUNDLE_ALIGN);
352 // daddiu $sp, $sp, -16
354 // daddiu $at, $zero, %hi($tgt - $baltgt)
357 // daddiu $at, $at, %lo($tgt - $baltgt)
359 // daddu $at, $ra, $at
362 // daddiu $sp, $sp, 16
366 // We assume the branch is within-function, and that offset is within
367 // +/- 2GB. High 32 bits will therefore always be zero.
369 // Note that this will work even if the offset is negative, because
370 // of the +1 modification that's added in that case. For example, if the
371 // offset is -1MB (0xFFFFFFFFFFF00000), the computation for %higher is
373 // 0xFFFFFFFFFFF00000 + 0x80008000 = 0x000000007FF08000
375 // and the bits [47:32] are zero. For %highest
377 // 0xFFFFFFFFFFF00000 + 0x800080008000 = 0x000080007FF08000
379 // and the bits [63:48] are zero.
381 Pos = LongBrMBB->begin();
383 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DADDiu), Mips::SP_64)
384 .addReg(Mips::SP_64).addImm(-16);
385 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::SD)).addReg(Mips::RA_64)
386 .addReg(Mips::SP_64).addImm(0);
387 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::LONG_BRANCH_DADDiu),
388 Mips::AT_64).addReg(Mips::ZERO_64)
389 .addMBB(TgtMBB, MipsII::MO_ABS_HI).addMBB(BalTgtMBB);
390 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::DSLL), Mips::AT_64)
391 .addReg(Mips::AT_64).addImm(16);
393 MIBundleBuilder(*LongBrMBB, Pos)
394 .append(BuildMI(*MF, DL, TII->get(BalOp)).addMBB(BalTgtMBB))
396 BuildMI(*MF, DL, TII->get(Mips::LONG_BRANCH_DADDiu), Mips::AT_64)
398 .addMBB(TgtMBB, MipsII::MO_ABS_LO)
401 Pos = BalTgtMBB->begin();
403 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::DADDu), Mips::AT_64)
404 .addReg(Mips::RA_64).addReg(Mips::AT_64);
405 BuildMI(*BalTgtMBB, Pos, DL, TII->get(Mips::LD), Mips::RA_64)
406 .addReg(Mips::SP_64).addImm(0);
408 MIBundleBuilder(*BalTgtMBB, Pos)
409 .append(BuildMI(*MF, DL, TII->get(Mips::JR64)).addReg(Mips::AT_64))
410 .append(BuildMI(*MF, DL, TII->get(Mips::DADDiu), Mips::SP_64)
411 .addReg(Mips::SP_64).addImm(16));
414 assert(LongBrMBB->size() + BalTgtMBB->size() == LongBranchSeqSize);
421 Pos = LongBrMBB->begin();
422 LongBrMBB->addSuccessor(TgtMBB);
423 MIBundleBuilder(*LongBrMBB, Pos)
424 .append(BuildMI(*MF, DL, TII->get(Mips::J)).addMBB(TgtMBB))
425 .append(BuildMI(*MF, DL, TII->get(Mips::NOP)));
427 assert(LongBrMBB->size() == LongBranchSeqSize);
430 if (I.Br->isUnconditionalBranch()) {
431 // Change branch destination.
432 assert(I.Br->getDesc().getNumOperands() == 1);
433 I.Br->RemoveOperand(0);
434 I.Br->addOperand(MachineOperand::CreateMBB(LongBrMBB));
436 // Change branch destination and reverse condition.
437 replaceBranch(*MBB, I.Br, DL, FallThroughMBB);
440 static void emitGPDisp(MachineFunction &F, const MipsInstrInfo *TII) {
441 MachineBasicBlock &MBB = F.front();
442 MachineBasicBlock::iterator I = MBB.begin();
443 DebugLoc DL = MBB.findDebugLoc(MBB.begin());
444 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0)
445 .addExternalSymbol("_gp_disp", MipsII::MO_ABS_HI);
446 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0)
447 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO);
448 MBB.removeLiveIn(Mips::V0);
451 bool MipsLongBranch::runOnMachineFunction(MachineFunction &F) {
452 const MipsSubtarget &STI =
453 static_cast<const MipsSubtarget &>(F.getSubtarget());
454 const MipsInstrInfo *TII =
455 static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
457 !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
459 if (STI.inMips16Mode() || !STI.enableLongBranchPass())
461 if ((TM.getRelocationModel() == Reloc::PIC_) &&
462 static_cast<const MipsTargetMachine &>(TM).getABI().IsO32() &&
463 F.getInfo<MipsFunctionInfo>()->globalBaseRegSet())
472 SmallVectorImpl<MBBInfo>::iterator I, E = MBBInfos.end();
473 bool EverMadeChange = false, MadeChange = true;
478 for (I = MBBInfos.begin(); I != E; ++I) {
479 // Skip if this MBB doesn't have a branch or the branch has already been
480 // converted to a long branch.
481 if (!I->Br || I->HasLongBranch)
484 int ShVal = STI.inMicroMipsMode() ? 2 : 4;
485 int64_t Offset = computeOffset(I->Br) / ShVal;
487 if (STI.isTargetNaCl()) {
488 // The offset calculation does not include sandboxing instructions
489 // that will be added later in the MC layer. Since at this point we
490 // don't know the exact amount of code that "sandboxing" will add, we
491 // conservatively estimate that code will not grow more than 100%.
495 // Check if offset fits into 16-bit immediate field of branches.
496 if (!ForceLongBranch && isInt<16>(Offset))
499 I->HasLongBranch = true;
500 I->Size += LongBranchSeqSize * 4;
502 EverMadeChange = MadeChange = true;
509 // Compute basic block addresses.
510 if (TM.getRelocationModel() == Reloc::PIC_) {
511 uint64_t Address = 0;
513 for (I = MBBInfos.begin(); I != E; Address += I->Size, ++I)
514 I->Address = Address;
518 for (I = MBBInfos.begin(); I != E; ++I)
519 if (I->HasLongBranch)
520 expandToLongBranch(*I);
522 MF->RenumberBlocks();